1 2 /* 3 * Called from l.s in EPROM to set up a minimal working environment. 4 * Since there is no DRAM yet, and therefore no stack, no function 5 * calls may be made from sysinit, and values can't be stored, 6 * except to INTMEM. Global values are accessed by offset from SB, 7 * which has been set by l.s to point into EPROM. 8 */ 9 10 #include "u.h" 11 #include "lib.h" 12 #include "mem.h" 13 #include "dat.h" 14 #include "fns.h" 15 #include "io.h" 16 17 #include "archrpcg.h" 18 19 #define MB (1024*1024) 20 21 enum { 22 UPMSIZE = 64, /* memory controller instruction RAM */ 23 DRAMSIZE = 16*MB, 24 FLASHSIZE = 4*MB, 25 26 WriteRAM = 0<<30, 27 ReadRAM = 1<<30, 28 ExecRAM = 2<<30, 29 30 SelUPMA = 0<<23, 31 SelUPMB = 1<<23, 32 }; 33 /* RPCG values for RPXLite AW */ 34 static ulong upma50[UPMSIZE] = { 35 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC04, 0x03AFCC08, 36 0x3FBFCC27, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 37 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, 38 0x3FBFCC27, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 39 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 40 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 41 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, 42 0x3FFFCC27, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 43 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC84, 0x03FFCC84, 44 0x0CFFCC00, 0x33FFCC27, 0xFFFFCC25, 0xFFFFCC25, 45 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 46 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 47 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, 48 0x3FFFCC27, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 49 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 50 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 0xFFFFCC25, 51 }; 52 53 void 54 sysinit0(int inrom) 55 { 56 ulong *upm; 57 IMM *io; 58 int i; 59 60 io = (IMM*)INTMEM; /* running before maps, no KADDR */ 61 io->siumcr = 0x01012440; 62 io->sypcr = 0xFFFFFF88; 63 io->tbscrk = KEEP_ALIVE_KEY; 64 io->tbscr = 0xC3; 65 io->rtcsck = KEEP_ALIVE_KEY; 66 io->rtcsc = 0xC1; 67 io->rtcsck = ~KEEP_ALIVE_KEY; 68 io->piscrk = KEEP_ALIVE_KEY; 69 io->piscr = 0x82; 70 return; 71 io->memc[BCSRCS].option = 0xFFFF8910; /* 32k block, all types access, CSNT, CS early negate, burst inhibit, 1 ws */ 72 io->memc[BCSRCS].base = BCSRMEM | 1; /* base, 32-bit port, no parity, GPCM */ 73 74 io->memc[BOOTCS].base = FLASHMEM | 0x801; /* base, 16 bit port */ 75 io->memc[BOOTCS].option = ~(FLASHSIZE-1)|(1<<8)|(4<<4); /* mask, BIH, 4 wait states */ 76 77 if(1||!inrom) 78 return; /* can't initialise DRAM controller from DRAM */ 79 80 /* TO DO: could check DRAM size and speed now */ 81 82 upm = upma50; 83 for(i=0; i<nelem(upma50); i++){ 84 io->mdr = upm[i]; 85 io->mcr = WriteRAM | SelUPMA | i; 86 } 87 io->mptpr = 0x0800; /* divide by 8 */ 88 io->mamr = (0x58<<24) | 0xA01430; /* 40MHz BRGCLK */ 89 io->memc[DRAM1].option = ~(DRAMSIZE-1)|0x0E00; /* address mask, SAM=1, G5LA/S=3 */ 90 io->memc[DRAM1].base = 0 | 0x81; /* base at 0, 32-bit port size, no parity, UPMA */ 91 } 92