xref: /inferno-os/DragonFly/386/include/fpuctl.h (revision 07f684ffc61236e171b449cfe9f91cef1e62866b)
1*07f684ffSforsyth /*
2*07f684ffSforsyth  * Linux 386 fpu support
3*07f684ffSforsyth  * Mimic Plan9 floating point support
4*07f684ffSforsyth  */
5*07f684ffSforsyth 
6*07f684ffSforsyth static void
setfcr(ulong fcr)7*07f684ffSforsyth setfcr(ulong fcr)
8*07f684ffSforsyth {
9*07f684ffSforsyth 	__asm__(	"xorb	$0x3f, %%al\n\t"
10*07f684ffSforsyth 			"pushw	%%ax\n\t"
11*07f684ffSforsyth 			"fwait\n\t"
12*07f684ffSforsyth 			"fldcw	(%%esp)\n\t"
13*07f684ffSforsyth 			"popw	%%ax\n\t"
14*07f684ffSforsyth 			: /* no output */
15*07f684ffSforsyth 			: "al" (fcr)
16*07f684ffSforsyth 	);
17*07f684ffSforsyth }
18*07f684ffSforsyth 
19*07f684ffSforsyth static ulong
getfcr(void)20*07f684ffSforsyth getfcr(void)
21*07f684ffSforsyth {
22*07f684ffSforsyth 	ulong fcr = 0;
23*07f684ffSforsyth 
24*07f684ffSforsyth 	__asm__(	"pushl	%%eax\n\t"
25*07f684ffSforsyth 			"fwait\n\t"
26*07f684ffSforsyth 			"fstcw	(%%esp)\n\t"
27*07f684ffSforsyth 			"popl	%%eax\n\t"
28*07f684ffSforsyth 			"xorb	$0x3f, %%al\n\t"
29*07f684ffSforsyth 			: "=a"  (fcr)
30*07f684ffSforsyth 			: "eax"	(fcr)
31*07f684ffSforsyth 	);
32*07f684ffSforsyth 	return fcr;
33*07f684ffSforsyth }
34*07f684ffSforsyth 
35*07f684ffSforsyth static ulong
getfsr(void)36*07f684ffSforsyth getfsr(void)
37*07f684ffSforsyth {
38*07f684ffSforsyth 	ulong fsr = -1;
39*07f684ffSforsyth 
40*07f684ffSforsyth 	__asm__(	"fwait\n\t"
41*07f684ffSforsyth 			"fstsw	(%%eax)\n\t"
42*07f684ffSforsyth 			"movl	(%%eax), %%eax\n\t"
43*07f684ffSforsyth 			"andl	$0xffff, %%eax\n\t"
44*07f684ffSforsyth 			: "=a"  (fsr)
45*07f684ffSforsyth 			: "eax" (&fsr)
46*07f684ffSforsyth 	);
47*07f684ffSforsyth 	return fsr;
48*07f684ffSforsyth }
49*07f684ffSforsyth 
50*07f684ffSforsyth static void
setfsr(ulong fsr)51*07f684ffSforsyth setfsr(ulong fsr)
52*07f684ffSforsyth {
53*07f684ffSforsyth 	__asm__("fclex\n\t");
54*07f684ffSforsyth }
55*07f684ffSforsyth 
56*07f684ffSforsyth /* FCR */
57*07f684ffSforsyth #define	FPINEX	(1<<5)
58*07f684ffSforsyth #define	FPUNFL	((1<<4)|(1<<1))
59*07f684ffSforsyth #define	FPOVFL	(1<<3)
60*07f684ffSforsyth #define	FPZDIV	(1<<2)
61*07f684ffSforsyth #define	FPINVAL	(1<<0)
62*07f684ffSforsyth #define	FPRNR	(0<<10)
63*07f684ffSforsyth #define	FPRZ	(3<<10)
64*07f684ffSforsyth #define	FPRPINF	(2<<10)
65*07f684ffSforsyth #define	FPRNINF	(1<<10)
66*07f684ffSforsyth #define	FPRMASK	(3<<10)
67*07f684ffSforsyth #define	FPPEXT	(3<<8)
68*07f684ffSforsyth #define	FPPSGL	(0<<8)
69*07f684ffSforsyth #define	FPPDBL	(2<<8)
70*07f684ffSforsyth #define	FPPMASK	(3<<8)
71*07f684ffSforsyth /* FSR */
72*07f684ffSforsyth #define	FPAINEX	FPINEX
73*07f684ffSforsyth #define	FPAOVFL	FPOVFL
74*07f684ffSforsyth #define	FPAUNFL	FPUNFL
75*07f684ffSforsyth #define	FPAZDIV	FPZDIV
76*07f684ffSforsyth #define	FPAINVAL	FPINVAL
77