1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/stdint.h> 32 #include <sys/stddef.h> 33 #include <sys/param.h> 34 #include <sys/queue.h> 35 #include <sys/types.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/module.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/sysctl.h> 44 #include <sys/sx.h> 45 #include <sys/unistd.h> 46 #include <sys/callout.h> 47 #include <sys/malloc.h> 48 #include <sys/priv.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 53 #include <dev/usb/usb_core.h> 54 #include <dev/usb/usb_busdma.h> 55 #include <dev/usb/usb_process.h> 56 #include <dev/usb/usb_util.h> 57 58 #include <dev/usb/usb_controller.h> 59 #include <dev/usb/usb_bus.h> 60 #include <dev/usb/usb_pci.h> 61 #include <dev/usb/controller/xhci.h> 62 #include <dev/usb/controller/xhcireg.h> 63 #include "usb_if.h" 64 65 static device_probe_t xhci_pci_probe; 66 static device_detach_t xhci_pci_detach; 67 static usb_take_controller_t xhci_pci_take_controller; 68 69 static device_method_t xhci_device_methods[] = { 70 /* device interface */ 71 DEVMETHOD(device_probe, xhci_pci_probe), 72 DEVMETHOD(device_attach, xhci_pci_attach), 73 DEVMETHOD(device_detach, xhci_pci_detach), 74 DEVMETHOD(device_suspend, bus_generic_suspend), 75 DEVMETHOD(device_resume, bus_generic_resume), 76 DEVMETHOD(device_shutdown, bus_generic_shutdown), 77 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 78 79 DEVMETHOD_END 80 }; 81 82 DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, 83 sizeof(struct xhci_softc)); 84 85 static devclass_t xhci_devclass; 86 87 DRIVER_MODULE(xhci, pci, xhci_pci_driver, xhci_devclass, NULL, NULL); 88 MODULE_DEPEND(xhci, usb, 1, 1, 1); 89 90 static const char * 91 xhci_pci_match(device_t self) 92 { 93 uint32_t device_id = pci_get_devid(self); 94 95 switch (device_id) { 96 case 0x145c1022: 97 return ("AMD KERNCZ USB 3.0 controller"); 98 case 0x43ba1022: 99 return ("AMD X399 USB 3.0 controller"); 100 case 0x43b91022: /* X370 */ 101 case 0x43bb1022: /* B350 */ 102 return ("AMD 300 Series USB 3.0 controller"); 103 case 0x78141022: 104 return ("AMD FCH USB 3.0 controller"); 105 106 case 0x145f1d94: 107 return ("Hygon USB 3.0 controller"); 108 109 case 0x01941033: 110 return ("NEC uPD720200 USB 3.0 controller"); 111 case 0x00151912: 112 return ("NEC uPD720202 USB 3.0 controller"); 113 114 case 0x10001b73: 115 return ("Fresco Logic FL1000G USB 3.0 controller"); 116 case 0x11001b73: 117 return ("Fresco Logic FL1100 USB 3.0 controller"); 118 119 case 0x10421b21: 120 return ("ASMedia ASM1042 USB 3.0 controller"); 121 case 0x11421b21: 122 return ("ASMedia ASM1042A USB 3.0 controller"); 123 124 case 0x0b278086: 125 return ("Intel Goshen Ridge Thunderbolt 4 USB controller"); 126 case 0x0f358086: 127 return ("Intel BayTrail USB 3.0 controller"); 128 case 0x11388086: 129 return ("Intel Maple Ridge Thunderbolt 4 USB controller"); 130 case 0x15c18086: 131 case 0x15d48086: 132 case 0x15db8086: 133 return ("Intel Alpine Ridge Thunderbolt 3 USB controller"); 134 case 0x15e98086: 135 case 0x15ec8086: 136 case 0x15f08086: 137 return ("Intel Titan Ridge Thunderbolt 3 USB controller"); 138 case 0x19d08086: 139 return ("Intel Denverton USB 3.0 controller"); 140 case 0x9c318086: 141 case 0x1e318086: 142 return ("Intel Panther Point USB 3.0 controller"); 143 case 0x22b58086: 144 return ("Intel Braswell USB 3.0 controller"); 145 case 0x31a88086: 146 return ("Intel Gemini Lake USB 3.0 controller"); 147 case 0x34ed8086: 148 return ("Intel Ice Lake-LP USB 3.1 controller"); 149 case 0x43ed8086: 150 return ("Intel Tiger Lake-H USB 3.2 controller"); 151 case 0x461e8086: 152 return ("Intel Alder Lake-P Thunderbolt 4 USB controller"); 153 case 0x51ed8086: 154 return ("Intel Alder Lake USB 3.2 controller"); 155 case 0x5aa88086: 156 return ("Intel Apollo Lake USB 3.0 controller"); 157 case 0x7ae08086: 158 return ("Intel Alder Lake USB 3.2 controller"); 159 case 0x8a138086: 160 return ("Intel Ice Lake Thunderbolt 3 USB controller"); 161 case 0x8c318086: 162 return ("Intel Lynx Point USB 3.0 controller"); 163 case 0x8cb18086: 164 return ("Intel Wildcat Point USB 3.0 controller"); 165 case 0x8d318086: 166 return ("Intel Wellsburg USB 3.0 controller"); 167 case 0x9a138086: 168 return ("Intel Tiger Lake-LP Thunderbolt 4 USB controller"); 169 case 0x9a178086: 170 return ("Intel Tiger Lake-H Thunderbolt 4 USB controller"); 171 case 0x9cb18086: 172 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller"); 173 case 0x9d2f8086: 174 return ("Intel Sunrise Point-LP USB 3.0 controller"); 175 case 0xa0ed8086: 176 return ("Intel Tiger Lake-LP USB 3.2 controller"); 177 case 0xa12f8086: 178 return ("Intel Sunrise Point USB 3.0 controller"); 179 case 0xa1af8086: 180 return ("Intel Lewisburg USB 3.0 controller"); 181 case 0xa2af8086: 182 return ("Intel Union Point USB 3.0 controller"); 183 case 0xa36d8086: 184 return ("Intel Cannon Lake USB 3.1 controller"); 185 186 case 0xa01b177d: 187 return ("Cavium ThunderX USB 3.0 controller"); 188 189 default: 190 break; 191 } 192 193 if ((pci_get_class(self) == PCIC_SERIALBUS) 194 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 195 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 196 return ("XHCI (generic) USB 3.0 controller"); 197 } 198 return (NULL); /* dunno */ 199 } 200 201 static int 202 xhci_pci_probe(device_t self) 203 { 204 const char *desc = xhci_pci_match(self); 205 206 if (desc) { 207 device_set_desc(self, desc); 208 return (BUS_PROBE_DEFAULT); 209 } else { 210 return (ENXIO); 211 } 212 } 213 214 static int xhci_use_msi = 1; 215 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 216 static int xhci_use_msix = 1; 217 TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix); 218 219 static void 220 xhci_interrupt_poll(void *_sc) 221 { 222 struct xhci_softc *sc = _sc; 223 USB_BUS_UNLOCK(&sc->sc_bus); 224 xhci_interrupt(sc); 225 USB_BUS_LOCK(&sc->sc_bus); 226 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 227 } 228 229 static int 230 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 231 { 232 uint32_t temp; 233 uint32_t usb3_mask; 234 uint32_t usb2_mask; 235 236 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 237 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 238 239 temp |= set; 240 temp &= ~clear; 241 242 /* Don't set bits which the hardware doesn't support */ 243 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 244 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 245 246 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 247 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 248 249 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 250 251 return (0); 252 } 253 254 int 255 xhci_pci_attach(device_t self) 256 { 257 struct xhci_softc *sc = device_get_softc(self); 258 int count, err, msix_table, rid; 259 uint8_t usemsi = 1; 260 uint8_t usedma32 = 0; 261 262 rid = PCI_XHCI_CBMEM; 263 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 264 RF_ACTIVE); 265 if (!sc->sc_io_res) { 266 device_printf(self, "Could not map memory\n"); 267 return (ENOMEM); 268 } 269 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 270 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 271 sc->sc_io_size = rman_get_size(sc->sc_io_res); 272 273 switch (pci_get_devid(self)) { 274 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 275 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 276 /* Don't use 64-bit DMA on these controllers. */ 277 usedma32 = 1; 278 break; 279 case 0x10001b73: /* FL1000G */ 280 /* Fresco Logic host doesn't support MSI. */ 281 usemsi = 0; 282 break; 283 case 0x0f358086: /* BayTrail */ 284 case 0x9c318086: /* Panther Point */ 285 case 0x1e318086: /* Panther Point */ 286 case 0x8c318086: /* Lynx Point */ 287 case 0x8cb18086: /* Wildcat Point */ 288 case 0x9cb18086: /* Broadwell Mobile Integrated */ 289 /* 290 * On Intel chipsets, reroute ports from EHCI to XHCI 291 * controller and use a different IMOD value. 292 */ 293 sc->sc_port_route = &xhci_pci_port_route; 294 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 295 sc->sc_ctlstep = 1; 296 break; 297 } 298 299 if (xhci_init(sc, self, usedma32)) { 300 device_printf(self, "Could not initialize softc\n"); 301 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 302 sc->sc_io_res); 303 return (ENXIO); 304 } 305 306 pci_enable_busmaster(self); 307 308 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 309 310 rid = 0; 311 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) { 312 if (msix_table == PCI_XHCI_CBMEM) { 313 sc->sc_msix_res = sc->sc_io_res; 314 } else { 315 sc->sc_msix_res = bus_alloc_resource_any(self, 316 SYS_RES_MEMORY, &msix_table, RF_ACTIVE); 317 if (sc->sc_msix_res == NULL) { 318 /* May not be enabled */ 319 device_printf(self, 320 "Unable to map MSI-X table\n"); 321 } 322 } 323 if (sc->sc_msix_res != NULL) { 324 count = 1; 325 if (pci_alloc_msix(self, &count) == 0) { 326 if (bootverbose) 327 device_printf(self, "MSI-X enabled\n"); 328 rid = 1; 329 } else { 330 if (sc->sc_msix_res != sc->sc_io_res) { 331 bus_release_resource(self, 332 SYS_RES_MEMORY, 333 msix_table, sc->sc_msix_res); 334 } 335 sc->sc_msix_res = NULL; 336 } 337 } 338 } 339 if (rid == 0 && xhci_use_msi && usemsi) { 340 count = 1; 341 if (pci_alloc_msi(self, &count) == 0) { 342 if (bootverbose) 343 device_printf(self, "MSI enabled\n"); 344 rid = 1; 345 } 346 } 347 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 348 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 349 if (sc->sc_irq_res == NULL) { 350 pci_release_msi(self); 351 device_printf(self, "Could not allocate IRQ\n"); 352 /* goto error; FALLTHROUGH - use polling */ 353 } 354 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 355 if (sc->sc_bus.bdev == NULL) { 356 device_printf(self, "Could not add USB device\n"); 357 goto error; 358 } 359 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 360 361 sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 362 363 if (sc->sc_irq_res != NULL) { 364 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 365 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 366 if (err != 0) { 367 bus_release_resource(self, SYS_RES_IRQ, 368 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 369 sc->sc_irq_res = NULL; 370 pci_release_msi(self); 371 device_printf(self, "Could not setup IRQ, err=%d\n", err); 372 sc->sc_intr_hdl = NULL; 373 } 374 } 375 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 376 if (xhci_use_polling() != 0) { 377 device_printf(self, "Interrupt polling at %dHz\n", hz); 378 USB_BUS_LOCK(&sc->sc_bus); 379 xhci_interrupt_poll(sc); 380 USB_BUS_UNLOCK(&sc->sc_bus); 381 } else 382 goto error; 383 } 384 385 xhci_pci_take_controller(self); 386 387 err = xhci_halt_controller(sc); 388 389 if (err == 0) 390 err = xhci_start_controller(sc); 391 392 if (err == 0) 393 err = device_probe_and_attach(sc->sc_bus.bdev); 394 395 if (err) { 396 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 397 goto error; 398 } 399 return (0); 400 401 error: 402 xhci_pci_detach(self); 403 return (ENXIO); 404 } 405 406 static int 407 xhci_pci_detach(device_t self) 408 { 409 struct xhci_softc *sc = device_get_softc(self); 410 411 /* during module unload there are lots of children leftover */ 412 device_delete_children(self); 413 414 usb_callout_drain(&sc->sc_callout); 415 xhci_halt_controller(sc); 416 xhci_reset_controller(sc); 417 418 pci_disable_busmaster(self); 419 420 if (sc->sc_irq_res && sc->sc_intr_hdl) { 421 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 422 sc->sc_intr_hdl = NULL; 423 } 424 if (sc->sc_irq_res) { 425 bus_release_resource(self, SYS_RES_IRQ, 426 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 427 sc->sc_irq_res = NULL; 428 pci_release_msi(self); 429 } 430 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) { 431 bus_release_resource(self, SYS_RES_MEMORY, 432 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res); 433 sc->sc_msix_res = NULL; 434 } 435 if (sc->sc_io_res) { 436 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 437 sc->sc_io_res); 438 sc->sc_io_res = NULL; 439 } 440 441 xhci_uninit(sc); 442 443 return (0); 444 } 445 446 static int 447 xhci_pci_take_controller(device_t self) 448 { 449 struct xhci_softc *sc = device_get_softc(self); 450 uint32_t cparams; 451 uint32_t eecp; 452 uint32_t eec; 453 uint16_t to; 454 uint8_t bios_sem; 455 456 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 457 458 eec = -1; 459 460 /* Synchronise with the BIOS if it owns the controller. */ 461 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 462 eecp += XHCI_XECP_NEXT(eec) << 2) { 463 eec = XREAD4(sc, capa, eecp); 464 465 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 466 continue; 467 bios_sem = XREAD1(sc, capa, eecp + 468 XHCI_XECP_BIOS_SEM); 469 if (bios_sem == 0) 470 continue; 471 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 472 "to give up control\n"); 473 XWRITE1(sc, capa, eecp + 474 XHCI_XECP_OS_SEM, 1); 475 to = 500; 476 while (1) { 477 bios_sem = XREAD1(sc, capa, eecp + 478 XHCI_XECP_BIOS_SEM); 479 if (bios_sem == 0) 480 break; 481 482 if (--to == 0) { 483 device_printf(sc->sc_bus.bdev, 484 "timed out waiting for BIOS\n"); 485 break; 486 } 487 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 488 } 489 } 490 return (0); 491 } 492