1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 4 * Copyright (c) 2010-2011 Aleksandr Rybalko. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * This file contains the driver for the DesignWare series USB 2.0 OTG 30 * Controller. 31 */ 32 33 /* 34 * LIMITATION: Drivers must be bound to all OUT endpoints in the 35 * active configuration for this driver to work properly. Blocking any 36 * OUT endpoint will block all OUT endpoints including the control 37 * endpoint. Usually this is not a problem. 38 */ 39 40 /* 41 * NOTE: Writing to non-existing registers appears to cause an 42 * internal reset. 43 */ 44 45 #ifdef USB_GLOBAL_INCLUDE_FILE 46 #include USB_GLOBAL_INCLUDE_FILE 47 #else 48 #include <sys/stdint.h> 49 #include <sys/stddef.h> 50 #include <sys/param.h> 51 #include <sys/queue.h> 52 #include <sys/types.h> 53 #include <sys/systm.h> 54 #include <sys/kernel.h> 55 #include <sys/bus.h> 56 #include <sys/module.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/condvar.h> 60 #include <sys/sysctl.h> 61 #include <sys/sx.h> 62 #include <sys/unistd.h> 63 #include <sys/callout.h> 64 #include <sys/malloc.h> 65 #include <sys/priv.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 70 #define USB_DEBUG_VAR dwc_otg_debug 71 72 #include <dev/usb/usb_core.h> 73 #include <dev/usb/usb_debug.h> 74 #include <dev/usb/usb_busdma.h> 75 #include <dev/usb/usb_process.h> 76 #include <dev/usb/usb_transfer.h> 77 #include <dev/usb/usb_device.h> 78 #include <dev/usb/usb_hub.h> 79 #include <dev/usb/usb_util.h> 80 81 #include <dev/usb/usb_controller.h> 82 #include <dev/usb/usb_bus.h> 83 #endif /* USB_GLOBAL_INCLUDE_FILE */ 84 85 #include <dev/usb/controller/dwc_otg.h> 86 #include <dev/usb/controller/dwc_otgreg.h> 87 88 #define DWC_OTG_BUS2SC(bus) \ 89 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 90 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 91 92 #define DWC_OTG_PC2UDEV(pc) \ 93 (USB_DMATAG_TO_XROOT((pc)->tag_parent)->udev) 94 95 #define DWC_OTG_MSK_GINT_ENABLED \ 96 (GINTMSK_ENUMDONEMSK | \ 97 GINTMSK_USBRSTMSK | \ 98 GINTMSK_USBSUSPMSK | \ 99 GINTMSK_IEPINTMSK | \ 100 GINTMSK_SESSREQINTMSK | \ 101 GINTMSK_RXFLVLMSK | \ 102 GINTMSK_HCHINTMSK | \ 103 GINTMSK_OTGINTMSK | \ 104 GINTMSK_PRTINTMSK) 105 106 #define DWC_OTG_MSK_GINT_THREAD_IRQ \ 107 (GINTSTS_USBRST | GINTSTS_ENUMDONE | GINTSTS_PRTINT | \ 108 GINTSTS_WKUPINT | GINTSTS_USBSUSP | GINTMSK_OTGINTMSK | \ 109 GINTSTS_SESSREQINT) 110 111 #define DWC_OTG_PHY_ULPI 0 112 #define DWC_OTG_PHY_HSIC 1 113 #define DWC_OTG_PHY_INTERNAL 2 114 115 #ifndef DWC_OTG_PHY_DEFAULT 116 #define DWC_OTG_PHY_DEFAULT DWC_OTG_PHY_ULPI 117 #endif 118 119 static int dwc_otg_phy_type = DWC_OTG_PHY_DEFAULT; 120 121 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 122 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, phy_type, CTLFLAG_RDTUN, 123 &dwc_otg_phy_type, 0, "DWC OTG PHY TYPE - 0/1/2 - ULPI/HSIC/INTERNAL"); 124 125 #ifdef USB_DEBUG 126 static int dwc_otg_debug; 127 128 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RWTUN, 129 &dwc_otg_debug, 0, "DWC OTG debug level"); 130 #endif 131 132 #define DWC_OTG_INTR_ENDPT 1 133 134 /* prototypes */ 135 136 static const struct usb_bus_methods dwc_otg_bus_methods; 137 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 138 static const struct usb_pipe_methods dwc_otg_device_isoc_methods; 139 140 static dwc_otg_cmd_t dwc_otg_setup_rx; 141 static dwc_otg_cmd_t dwc_otg_data_rx; 142 static dwc_otg_cmd_t dwc_otg_data_tx; 143 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 144 145 static dwc_otg_cmd_t dwc_otg_host_setup_tx; 146 static dwc_otg_cmd_t dwc_otg_host_data_tx; 147 static dwc_otg_cmd_t dwc_otg_host_data_rx; 148 149 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 150 static void dwc_otg_do_poll(struct usb_bus *); 151 static void dwc_otg_standard_done(struct usb_xfer *); 152 static void dwc_otg_root_intr(struct dwc_otg_softc *); 153 static void dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *); 154 static void dwc_otg_host_channel_disable(struct dwc_otg_softc *, uint8_t); 155 156 /* 157 * Here is a configuration that the chip supports. 158 */ 159 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 160 161 [0] = { 162 .max_in_frame_size = 64,/* fixed */ 163 .max_out_frame_size = 64, /* fixed */ 164 .is_simplex = 1, 165 .support_control = 1, 166 } 167 }; 168 169 static void 170 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 171 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 172 { 173 struct dwc_otg_softc *sc; 174 175 sc = DWC_OTG_BUS2SC(udev->bus); 176 177 if (ep_addr < sc->sc_dev_ep_max) 178 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 179 else 180 *ppf = NULL; 181 } 182 183 static int 184 dwc_otg_init_fifo(struct dwc_otg_softc *sc, uint8_t mode) 185 { 186 struct dwc_otg_profile *pf; 187 uint32_t fifo_size; 188 uint32_t fifo_regs; 189 uint32_t tx_start; 190 uint8_t x; 191 192 fifo_size = sc->sc_fifo_size; 193 194 /* 195 * NOTE: Reserved fixed size area at end of RAM, which must 196 * not be allocated to the FIFOs: 197 */ 198 fifo_regs = 4 * 16; 199 200 if (fifo_size < fifo_regs) { 201 DPRINTF("Too little FIFO\n"); 202 return (EINVAL); 203 } 204 205 /* subtract FIFO regs from total once */ 206 fifo_size -= fifo_regs; 207 208 /* split equally for IN and OUT */ 209 fifo_size /= 2; 210 211 /* align to 4 bytes boundary */ 212 fifo_size &= ~3; 213 214 /* set global receive FIFO size */ 215 DWC_OTG_WRITE_4(sc, DOTG_GRXFSIZ, fifo_size / 4); 216 217 tx_start = fifo_size; 218 219 if (fifo_size < 64) { 220 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 221 return (EINVAL); 222 } 223 224 /* disable any leftover host channels */ 225 for (x = 0; x != sc->sc_host_ch_max; x++) { 226 if (sc->sc_chan_state[x].wait_sof == 0) 227 continue; 228 dwc_otg_host_channel_disable(sc, x); 229 } 230 231 if (mode == DWC_MODE_HOST) { 232 233 /* reset active endpoints */ 234 sc->sc_active_rx_ep = 0; 235 236 /* split equally for periodic and non-periodic */ 237 fifo_size /= 2; 238 239 /* align to 4 bytes boundary */ 240 fifo_size &= ~3; 241 242 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 243 ((fifo_size / 4) << 16) | 244 (tx_start / 4)); 245 246 tx_start += fifo_size; 247 248 for (x = 0; x != sc->sc_host_ch_max; x++) { 249 /* disable all host interrupts */ 250 DWC_OTG_WRITE_4(sc, DOTG_HCINTMSK(x), 251 HCINT_DEFAULT_MASK); 252 } 253 254 DWC_OTG_WRITE_4(sc, DOTG_HPTXFSIZ, 255 ((fifo_size / 4) << 16) | 256 (tx_start / 4)); 257 258 /* reset host channel state */ 259 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 260 261 /* reset FIFO TX levels */ 262 sc->sc_tx_cur_p_level = 0; 263 sc->sc_tx_cur_np_level = 0; 264 265 /* store maximum periodic and non-periodic FIFO TX size */ 266 sc->sc_tx_max_size = fifo_size; 267 268 /* enable all host channel interrupts */ 269 DWC_OTG_WRITE_4(sc, DOTG_HAINTMSK, 270 (1U << sc->sc_host_ch_max) - 1U); 271 } 272 273 if (mode == DWC_MODE_DEVICE) { 274 275 DWC_OTG_WRITE_4(sc, DOTG_GNPTXFSIZ, 276 (0x10 << 16) | (tx_start / 4)); 277 fifo_size -= 0x40; 278 tx_start += 0x40; 279 280 /* setup control endpoint profile */ 281 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 282 283 /* reset active endpoints */ 284 sc->sc_active_rx_ep = 1; 285 286 for (x = 1; x != sc->sc_dev_ep_max; x++) { 287 288 pf = sc->sc_hw_ep_profile + x; 289 290 pf->usb.max_out_frame_size = 1024 * 3; 291 pf->usb.is_simplex = 0; /* assume duplex */ 292 pf->usb.support_bulk = 1; 293 pf->usb.support_interrupt = 1; 294 pf->usb.support_isochronous = 1; 295 pf->usb.support_out = 1; 296 297 if (x < sc->sc_dev_in_ep_max) { 298 uint32_t limit; 299 300 limit = (x == 1) ? MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 301 DWC_OTG_MAX_TXN) : MIN(DWC_OTG_MAX_TXN / 2, 302 DWC_OTG_TX_MAX_FIFO_SIZE); 303 304 /* see if there is enough FIFO space */ 305 if (limit <= fifo_size) { 306 pf->max_buffer = limit; 307 pf->usb.support_in = 1; 308 } else { 309 limit = MIN(DWC_OTG_TX_MAX_FIFO_SIZE, 0x40); 310 if (limit <= fifo_size) { 311 pf->usb.support_in = 1; 312 } else { 313 pf->usb.is_simplex = 1; 314 limit = 0; 315 } 316 } 317 /* set FIFO size */ 318 DWC_OTG_WRITE_4(sc, DOTG_DIEPTXF(x), 319 ((limit / 4) << 16) | (tx_start / 4)); 320 tx_start += limit; 321 fifo_size -= limit; 322 pf->usb.max_in_frame_size = limit; 323 } else { 324 pf->usb.is_simplex = 1; 325 } 326 327 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 328 pf->usb.max_in_frame_size, 329 pf->usb.max_out_frame_size); 330 } 331 } 332 333 /* reset RX FIFO */ 334 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 335 GRSTCTL_RXFFLSH); 336 337 if (mode != DWC_MODE_OTG) { 338 /* reset all TX FIFOs */ 339 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 340 GRSTCTL_TXFIFO(0x10) | 341 GRSTCTL_TXFFLSH); 342 } else { 343 /* reset active endpoints */ 344 sc->sc_active_rx_ep = 0; 345 346 /* reset periodic and non-periodic FIFO TX size */ 347 sc->sc_tx_max_size = fifo_size; 348 349 /* reset host channel state */ 350 memset(sc->sc_chan_state, 0, sizeof(sc->sc_chan_state)); 351 352 /* reset FIFO TX levels */ 353 sc->sc_tx_cur_p_level = 0; 354 sc->sc_tx_cur_np_level = 0; 355 } 356 return (0); 357 } 358 359 static void 360 dwc_otg_update_host_frame_interval(struct dwc_otg_softc *sc) 361 { 362 363 /* 364 * Disabled until further. Assuming that the register is already 365 * programmed correctly by the boot loader. 366 */ 367 #if 0 368 uint32_t temp; 369 370 /* setup HOST frame interval register, based on existing value */ 371 temp = DWC_OTG_READ_4(sc, DOTG_HFIR) & HFIR_FRINT_MASK; 372 if (temp >= 10000) 373 temp /= 1000; 374 else 375 temp /= 125; 376 377 /* figure out nearest X-tal value */ 378 if (temp >= 54) 379 temp = 60; /* MHz */ 380 else if (temp >= 39) 381 temp = 48; /* MHz */ 382 else 383 temp = 30; /* MHz */ 384 385 if (sc->sc_flags.status_high_speed) 386 temp *= 125; 387 else 388 temp *= 1000; 389 390 DPRINTF("HFIR=0x%08x\n", temp); 391 392 DWC_OTG_WRITE_4(sc, DOTG_HFIR, temp); 393 #endif 394 } 395 396 static void 397 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 398 { 399 if (sc->sc_flags.clocks_off && 400 sc->sc_flags.port_powered) { 401 402 DPRINTFN(5, "\n"); 403 404 /* TODO - platform specific */ 405 406 sc->sc_flags.clocks_off = 0; 407 } 408 } 409 410 static void 411 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 412 { 413 if (!sc->sc_flags.clocks_off) { 414 415 DPRINTFN(5, "\n"); 416 417 /* TODO - platform specific */ 418 419 sc->sc_flags.clocks_off = 1; 420 } 421 } 422 423 static void 424 dwc_otg_pull_up(struct dwc_otg_softc *sc) 425 { 426 uint32_t temp; 427 428 /* pullup D+, if possible */ 429 430 if (!sc->sc_flags.d_pulled_up && 431 sc->sc_flags.port_powered) { 432 sc->sc_flags.d_pulled_up = 1; 433 434 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 435 temp &= ~DCTL_SFTDISCON; 436 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 437 } 438 } 439 440 static void 441 dwc_otg_pull_down(struct dwc_otg_softc *sc) 442 { 443 uint32_t temp; 444 445 /* pulldown D+, if possible */ 446 447 if (sc->sc_flags.d_pulled_up) { 448 sc->sc_flags.d_pulled_up = 0; 449 450 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 451 temp |= DCTL_SFTDISCON; 452 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 453 } 454 } 455 456 static void 457 dwc_otg_enable_sof_irq(struct dwc_otg_softc *sc) 458 { 459 /* In device mode we don't use the SOF interrupt */ 460 if (sc->sc_flags.status_device_mode != 0 || 461 (sc->sc_irq_mask & GINTMSK_SOFMSK) != 0) 462 return; 463 sc->sc_irq_mask |= GINTMSK_SOFMSK; 464 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 465 } 466 467 static void 468 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 469 { 470 if (sc->sc_flags.status_suspend) { 471 /* update status bits */ 472 sc->sc_flags.status_suspend = 0; 473 sc->sc_flags.change_suspend = 1; 474 475 if (sc->sc_flags.status_device_mode) { 476 /* 477 * Disable resume interrupt and enable suspend 478 * interrupt: 479 */ 480 sc->sc_irq_mask &= ~GINTMSK_WKUPINTMSK; 481 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 482 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 483 } 484 485 /* complete root HUB interrupt endpoint */ 486 dwc_otg_root_intr(sc); 487 } 488 } 489 490 static void 491 dwc_otg_suspend_irq(struct dwc_otg_softc *sc) 492 { 493 if (!sc->sc_flags.status_suspend) { 494 /* update status bits */ 495 sc->sc_flags.status_suspend = 1; 496 sc->sc_flags.change_suspend = 1; 497 498 if (sc->sc_flags.status_device_mode) { 499 /* 500 * Disable suspend interrupt and enable resume 501 * interrupt: 502 */ 503 sc->sc_irq_mask &= ~GINTMSK_USBSUSPMSK; 504 sc->sc_irq_mask |= GINTMSK_WKUPINTMSK; 505 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 506 } 507 508 /* complete root HUB interrupt endpoint */ 509 dwc_otg_root_intr(sc); 510 } 511 } 512 513 static void 514 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 515 { 516 if (!sc->sc_flags.status_suspend) 517 return; 518 519 DPRINTFN(5, "Remote wakeup\n"); 520 521 if (sc->sc_flags.status_device_mode) { 522 uint32_t temp; 523 524 /* enable remote wakeup signalling */ 525 temp = DWC_OTG_READ_4(sc, DOTG_DCTL); 526 temp |= DCTL_RMTWKUPSIG; 527 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 528 529 /* Wait 8ms for remote wakeup to complete. */ 530 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 531 532 temp &= ~DCTL_RMTWKUPSIG; 533 DWC_OTG_WRITE_4(sc, DOTG_DCTL, temp); 534 } else { 535 /* enable USB port */ 536 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 537 538 /* wait 10ms */ 539 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 540 541 /* resume port */ 542 sc->sc_hprt_val |= HPRT_PRTRES; 543 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 544 545 /* Wait 100ms for resume signalling to complete. */ 546 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 10); 547 548 /* clear suspend and resume */ 549 sc->sc_hprt_val &= ~(HPRT_PRTSUSP | HPRT_PRTRES); 550 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 551 552 /* Wait 4ms */ 553 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 554 } 555 556 /* need to fake resume IRQ */ 557 dwc_otg_resume_irq(sc); 558 } 559 560 static void 561 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 562 { 563 uint32_t temp; 564 565 DPRINTFN(5, "addr=%d\n", addr); 566 567 temp = DWC_OTG_READ_4(sc, DOTG_DCFG); 568 temp &= ~DCFG_DEVADDR_SET(0x7F); 569 temp |= DCFG_DEVADDR_SET(addr); 570 DWC_OTG_WRITE_4(sc, DOTG_DCFG, temp); 571 } 572 573 static void 574 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 575 { 576 DPRINTFN(5, "RX status clear\n"); 577 578 /* enable RX FIFO level interrupt */ 579 sc->sc_irq_mask |= GINTMSK_RXFLVLMSK; 580 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 581 582 /* clear cached status */ 583 sc->sc_last_rx_status = 0; 584 } 585 586 static void 587 dwc_otg_clear_hcint(struct dwc_otg_softc *sc, uint8_t x) 588 { 589 uint32_t hcint; 590 591 /* clear all pending interrupts */ 592 hcint = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 593 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), hcint); 594 595 /* clear buffered interrupts */ 596 sc->sc_chan_state[x].hcint = 0; 597 } 598 599 static uint8_t 600 dwc_otg_host_channel_alloc(struct dwc_otg_softc *sc, struct dwc_otg_td *td, uint8_t is_out) 601 { 602 uint32_t tx_p_size; 603 uint32_t tx_np_size; 604 uint8_t x; 605 606 if (td->channel < DWC_OTG_MAX_CHANNELS) 607 return (0); /* already allocated */ 608 609 /* check if device is suspended */ 610 if (DWC_OTG_PC2UDEV(td->pc)->flags.self_suspended != 0) 611 return (1); /* busy - cannot transfer data */ 612 613 /* compute needed TX FIFO size */ 614 if (is_out != 0) { 615 if (td->ep_type == UE_ISOCHRONOUS) { 616 tx_p_size = td->max_packet_size; 617 tx_np_size = 0; 618 if (td->hcsplt != 0 && tx_p_size > HCSPLT_XACTLEN_BURST) 619 tx_p_size = HCSPLT_XACTLEN_BURST; 620 if ((sc->sc_tx_cur_p_level + tx_p_size) > sc->sc_tx_max_size) { 621 DPRINTF("Too little FIFO space\n"); 622 return (1); /* too little FIFO */ 623 } 624 } else { 625 tx_p_size = 0; 626 tx_np_size = td->max_packet_size; 627 if (td->hcsplt != 0 && tx_np_size > HCSPLT_XACTLEN_BURST) 628 tx_np_size = HCSPLT_XACTLEN_BURST; 629 if ((sc->sc_tx_cur_np_level + tx_np_size) > sc->sc_tx_max_size) { 630 DPRINTF("Too little FIFO space\n"); 631 return (1); /* too little FIFO */ 632 } 633 } 634 } else { 635 /* not a TX transaction */ 636 tx_p_size = 0; 637 tx_np_size = 0; 638 } 639 640 for (x = 0; x != sc->sc_host_ch_max; x++) { 641 if (sc->sc_chan_state[x].allocated != 0) 642 continue; 643 /* check if channel is still enabled */ 644 if (sc->sc_chan_state[x].wait_sof != 0) 645 continue; 646 647 sc->sc_chan_state[x].allocated = 1; 648 sc->sc_chan_state[x].tx_p_size = tx_p_size; 649 sc->sc_chan_state[x].tx_np_size = tx_np_size; 650 651 /* keep track of used TX FIFO, if any */ 652 sc->sc_tx_cur_p_level += tx_p_size; 653 sc->sc_tx_cur_np_level += tx_np_size; 654 655 /* clear interrupts */ 656 dwc_otg_clear_hcint(sc, x); 657 658 DPRINTF("CH=%d HCCHAR=0x%08x " 659 "HCSPLT=0x%08x\n", x, td->hcchar, td->hcsplt); 660 661 /* set active channel */ 662 sc->sc_active_rx_ep |= (1 << x); 663 664 /* set channel */ 665 td->channel = x; 666 667 return (0); /* allocated */ 668 } 669 /* wait a bit */ 670 dwc_otg_enable_sof_irq(sc); 671 return (1); /* busy */ 672 } 673 674 static void 675 dwc_otg_host_channel_free(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 676 { 677 uint8_t x; 678 679 if (td->channel >= DWC_OTG_MAX_CHANNELS) 680 return; /* already freed */ 681 682 /* free channel */ 683 x = td->channel; 684 td->channel = DWC_OTG_MAX_CHANNELS; 685 686 DPRINTF("CH=%d\n", x); 687 688 /* 689 * We need to let programmed host channels run till complete 690 * else the host channel will stop functioning. Assume that 691 * after a fixed given amount of time the host channel is no 692 * longer doing any USB traffic: 693 */ 694 if (td->ep_type == UE_ISOCHRONOUS) { 695 /* double buffered */ 696 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MAX; 697 } else { 698 /* single buffered */ 699 sc->sc_chan_state[x].wait_sof = DWC_OTG_SLOT_IDLE_MIN; 700 } 701 702 sc->sc_chan_state[x].allocated = 0; 703 704 /* ack any pending messages */ 705 if (sc->sc_last_rx_status != 0 && 706 GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) == x) { 707 dwc_otg_common_rx_ack(sc); 708 } 709 710 /* clear active channel */ 711 sc->sc_active_rx_ep &= ~(1 << x); 712 } 713 714 static void 715 dwc_otg_host_dump_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 716 { 717 /* dump any pending messages */ 718 if (sc->sc_last_rx_status != 0) { 719 if (td->channel < DWC_OTG_MAX_CHANNELS && 720 td->channel == GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status)) { 721 dwc_otg_common_rx_ack(sc); 722 } 723 } 724 } 725 726 static uint8_t 727 dwc_otg_host_setup_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 728 { 729 struct usb_device_request req __aligned(4); 730 uint32_t hcint; 731 uint32_t hcchar; 732 uint8_t delta; 733 734 dwc_otg_host_dump_rx(sc, td); 735 736 if (td->channel < DWC_OTG_MAX_CHANNELS) { 737 hcint = sc->sc_chan_state[td->channel].hcint; 738 739 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 740 td->channel, td->state, hcint, 741 DWC_OTG_READ_4(sc, DOTG_HCCHAR(td->channel)), 742 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(td->channel))); 743 } else { 744 hcint = 0; 745 goto check_state; 746 } 747 748 if (hcint & (HCINT_RETRY | 749 HCINT_ACK | HCINT_NYET)) { 750 /* give success bits priority over failure bits */ 751 } else if (hcint & HCINT_STALL) { 752 DPRINTF("CH=%d STALL\n", td->channel); 753 td->error_stall = 1; 754 td->error_any = 1; 755 goto complete; 756 } else if (hcint & HCINT_ERRORS) { 757 DPRINTF("CH=%d ERROR\n", td->channel); 758 td->errcnt++; 759 if (td->hcsplt != 0 || td->errcnt >= 3) { 760 td->error_any = 1; 761 goto complete; 762 } 763 } 764 765 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 766 HCINT_ACK | HCINT_NYET)) { 767 if (!(hcint & HCINT_ERRORS)) 768 td->errcnt = 0; 769 } 770 771 check_state: 772 switch (td->state) { 773 case DWC_CHAN_ST_START: 774 goto send_pkt; 775 776 case DWC_CHAN_ST_WAIT_ANE: 777 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 778 td->did_nak++; 779 td->tt_scheduled = 0; 780 goto send_pkt; 781 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 782 td->offset += td->tx_bytes; 783 td->remainder -= td->tx_bytes; 784 td->toggle = 1; 785 td->tt_scheduled = 0; 786 goto complete; 787 } 788 break; 789 790 case DWC_CHAN_ST_WAIT_S_ANE: 791 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 792 td->did_nak++; 793 td->tt_scheduled = 0; 794 goto send_pkt; 795 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 796 goto send_cpkt; 797 } 798 break; 799 800 case DWC_CHAN_ST_WAIT_C_ANE: 801 if (hcint & HCINT_NYET) { 802 goto send_cpkt; 803 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 804 td->did_nak++; 805 td->tt_scheduled = 0; 806 goto send_pkt; 807 } else if (hcint & HCINT_ACK) { 808 td->offset += td->tx_bytes; 809 td->remainder -= td->tx_bytes; 810 td->toggle = 1; 811 goto complete; 812 } 813 break; 814 815 case DWC_CHAN_ST_WAIT_C_PKT: 816 goto send_cpkt; 817 818 default: 819 break; 820 } 821 goto busy; 822 823 send_pkt: 824 /* free existing channel, if any */ 825 dwc_otg_host_channel_free(sc, td); 826 827 if (sizeof(req) != td->remainder) { 828 td->error_any = 1; 829 goto complete; 830 } 831 832 if (td->hcsplt != 0) { 833 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 834 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 835 td->state = DWC_CHAN_ST_START; 836 goto busy; 837 } 838 delta = sc->sc_last_frame_num - td->tt_start_slot; 839 if (delta > 5) { 840 /* missed it */ 841 td->tt_scheduled = 0; 842 td->state = DWC_CHAN_ST_START; 843 goto busy; 844 } 845 } 846 847 /* allocate a new channel */ 848 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 849 td->state = DWC_CHAN_ST_START; 850 goto busy; 851 } 852 853 if (td->hcsplt != 0) { 854 td->hcsplt &= ~HCSPLT_COMPSPLT; 855 td->state = DWC_CHAN_ST_WAIT_S_ANE; 856 } else { 857 td->state = DWC_CHAN_ST_WAIT_ANE; 858 } 859 860 usbd_copy_out(td->pc, 0, &req, sizeof(req)); 861 862 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 863 (sizeof(req) << HCTSIZ_XFERSIZE_SHIFT) | 864 (1 << HCTSIZ_PKTCNT_SHIFT) | 865 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 866 867 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 868 869 hcchar = td->hcchar; 870 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 871 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 872 873 /* must enable channel before writing data to FIFO */ 874 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 875 876 /* transfer data into FIFO */ 877 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 878 DOTG_DFIFO(td->channel), (uint32_t *)&req, sizeof(req) / 4); 879 880 /* wait until next slot before trying complete split */ 881 td->tt_complete_slot = sc->sc_last_frame_num + 1; 882 883 /* store number of bytes transmitted */ 884 td->tx_bytes = sizeof(req); 885 goto busy; 886 887 send_cpkt: 888 /* free existing channel, if any */ 889 dwc_otg_host_channel_free(sc, td); 890 891 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 892 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 893 td->state = DWC_CHAN_ST_WAIT_C_PKT; 894 goto busy; 895 } 896 delta = sc->sc_last_frame_num - td->tt_start_slot; 897 if (delta > DWC_OTG_TT_SLOT_MAX) { 898 /* we missed the service interval */ 899 if (td->ep_type != UE_ISOCHRONOUS) 900 td->error_any = 1; 901 goto complete; 902 } 903 /* allocate a new channel */ 904 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 905 td->state = DWC_CHAN_ST_WAIT_C_PKT; 906 goto busy; 907 } 908 909 /* wait until next slot before trying complete split */ 910 td->tt_complete_slot = sc->sc_last_frame_num + 1; 911 912 td->hcsplt |= HCSPLT_COMPSPLT; 913 td->state = DWC_CHAN_ST_WAIT_C_ANE; 914 915 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(td->channel), 916 (HCTSIZ_PID_SETUP << HCTSIZ_PID_SHIFT)); 917 918 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(td->channel), td->hcsplt); 919 920 hcchar = td->hcchar; 921 hcchar &= ~(HCCHAR_EPDIR_IN | HCCHAR_EPTYPE_MASK); 922 hcchar |= UE_CONTROL << HCCHAR_EPTYPE_SHIFT; 923 924 /* must enable channel before writing data to FIFO */ 925 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(td->channel), hcchar); 926 927 busy: 928 return (1); /* busy */ 929 930 complete: 931 dwc_otg_host_channel_free(sc, td); 932 return (0); /* complete */ 933 } 934 935 static uint8_t 936 dwc_otg_setup_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 937 { 938 struct usb_device_request req __aligned(4); 939 uint32_t temp; 940 uint16_t count; 941 942 /* check endpoint status */ 943 944 if (sc->sc_last_rx_status == 0) 945 goto not_complete; 946 947 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != 0) 948 goto not_complete; 949 950 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != 951 GRXSTSRD_DPID_DATA0) { 952 /* release FIFO */ 953 dwc_otg_common_rx_ack(sc); 954 goto not_complete; 955 } 956 957 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 958 GRXSTSRD_STP_DATA) { 959 /* release FIFO */ 960 dwc_otg_common_rx_ack(sc); 961 goto not_complete; 962 } 963 964 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 965 966 /* clear did stall */ 967 td->did_stall = 0; 968 969 /* get the packet byte count */ 970 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 971 972 /* verify data length */ 973 if (count != td->remainder) { 974 DPRINTFN(0, "Invalid SETUP packet " 975 "length, %d bytes\n", count); 976 /* release FIFO */ 977 dwc_otg_common_rx_ack(sc); 978 goto not_complete; 979 } 980 if (count != sizeof(req)) { 981 DPRINTFN(0, "Unsupported SETUP packet " 982 "length, %d bytes\n", count); 983 /* release FIFO */ 984 dwc_otg_common_rx_ack(sc); 985 goto not_complete; 986 } 987 988 /* copy in control request */ 989 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 990 991 /* copy data into real buffer */ 992 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 993 994 td->offset = sizeof(req); 995 td->remainder = 0; 996 997 /* sneak peek the set address */ 998 if ((req.bmRequestType == UT_WRITE_DEVICE) && 999 (req.bRequest == UR_SET_ADDRESS)) { 1000 /* must write address before ZLP */ 1001 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 1002 } 1003 1004 /* don't send any data by default */ 1005 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(0), 1006 DXEPTSIZ_SET_NPKT(0) | 1007 DXEPTSIZ_SET_NBYTES(0)); 1008 1009 temp = sc->sc_in_ctl[0]; 1010 1011 /* enable IN endpoint */ 1012 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1013 temp | DIEPCTL_EPENA); 1014 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1015 temp | DIEPCTL_SNAK); 1016 1017 /* reset IN endpoint buffer */ 1018 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 1019 GRSTCTL_TXFIFO(0) | 1020 GRSTCTL_TXFFLSH); 1021 1022 /* acknowledge RX status */ 1023 dwc_otg_common_rx_ack(sc); 1024 return (0); /* complete */ 1025 1026 not_complete: 1027 /* abort any ongoing transfer, before enabling again */ 1028 1029 temp = sc->sc_out_ctl[0]; 1030 1031 temp |= DOEPCTL_EPENA | 1032 DOEPCTL_SNAK; 1033 1034 /* enable OUT endpoint */ 1035 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), temp); 1036 1037 if (!td->did_stall) { 1038 td->did_stall = 1; 1039 1040 DPRINTFN(5, "stalling IN and OUT direction\n"); 1041 1042 /* set stall after enabling endpoint */ 1043 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(0), 1044 temp | DOEPCTL_STALL); 1045 1046 temp = sc->sc_in_ctl[0]; 1047 1048 /* set stall assuming endpoint is enabled */ 1049 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(0), 1050 temp | DIEPCTL_STALL); 1051 } 1052 1053 /* setup number of buffers to receive */ 1054 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1055 DXEPTSIZ_SET_MULTI(3) | 1056 DXEPTSIZ_SET_NPKT(1) | 1057 DXEPTSIZ_SET_NBYTES(sizeof(req))); 1058 1059 return (1); /* not complete */ 1060 } 1061 1062 static uint8_t 1063 dwc_otg_host_rate_check_interrupt(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1064 { 1065 uint8_t delta; 1066 1067 delta = sc->sc_tmr_val - td->tmr_val; 1068 if (delta >= 128) 1069 return (1); /* busy */ 1070 1071 td->tmr_val = sc->sc_tmr_val + td->tmr_res; 1072 1073 /* set toggle, if any */ 1074 if (td->set_toggle) { 1075 td->set_toggle = 0; 1076 td->toggle = 1; 1077 } 1078 return (0); 1079 } 1080 1081 static uint8_t 1082 dwc_otg_host_rate_check(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1083 { 1084 if (td->ep_type == UE_ISOCHRONOUS) { 1085 /* non TT isochronous traffic */ 1086 if ((td->tmr_val != 0) || 1087 (sc->sc_last_frame_num & (td->tmr_res - 1))) { 1088 goto busy; 1089 } 1090 td->tmr_val = 1; /* executed */ 1091 td->toggle = 0; 1092 1093 } else if (td->ep_type == UE_INTERRUPT) { 1094 if (!td->tt_scheduled) 1095 goto busy; 1096 td->tt_scheduled = 0; 1097 } else if (td->did_nak >= DWC_OTG_NAK_MAX) { 1098 goto busy; 1099 } else if (td->set_toggle) { 1100 td->set_toggle = 0; 1101 td->toggle = 1; 1102 } 1103 return (0); 1104 busy: 1105 return (1); 1106 } 1107 1108 static uint8_t 1109 dwc_otg_host_data_rx_sub(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1110 { 1111 uint32_t count; 1112 uint8_t channel; 1113 1114 /* check endpoint status */ 1115 if (sc->sc_last_rx_status == 0) 1116 goto busy; 1117 1118 channel = td->channel; 1119 if (channel >= DWC_OTG_MAX_CHANNELS) 1120 goto busy; 1121 1122 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != channel) 1123 goto busy; 1124 1125 switch (sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) { 1126 case GRXSTSRH_IN_DATA: 1127 1128 DPRINTF("DATA ST=%d STATUS=0x%08x\n", 1129 (int)td->state, (int)sc->sc_last_rx_status); 1130 1131 if (sc->sc_chan_state[channel].hcint & HCINT_SOFTWARE_ONLY) { 1132 /* 1133 * When using SPLIT transactions on interrupt 1134 * endpoints, sometimes data occurs twice. 1135 */ 1136 DPRINTF("Data already received\n"); 1137 break; 1138 } 1139 1140 /* get the packet byte count */ 1141 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1142 1143 /* check for isochronous transfer or high-speed bandwidth endpoint */ 1144 if (td->ep_type == UE_ISOCHRONOUS || td->max_packet_count > 1) { 1145 if ((sc->sc_last_rx_status & GRXSTSRD_DPID_MASK) != GRXSTSRD_DPID_DATA0) { 1146 td->tt_xactpos = HCSPLT_XACTPOS_MIDDLE; 1147 } else { 1148 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 1149 1150 /* verify the packet byte count */ 1151 if (count < td->max_packet_size) { 1152 /* we have a short packet */ 1153 td->short_pkt = 1; 1154 td->got_short = 1; 1155 } 1156 } 1157 td->toggle = 0; 1158 } else { 1159 /* verify the packet byte count */ 1160 if (count != td->max_packet_size) { 1161 if (count < td->max_packet_size) { 1162 /* we have a short packet */ 1163 td->short_pkt = 1; 1164 td->got_short = 1; 1165 } else { 1166 /* invalid USB packet */ 1167 td->error_any = 1; 1168 1169 /* release FIFO */ 1170 dwc_otg_common_rx_ack(sc); 1171 goto complete; 1172 } 1173 } 1174 td->toggle ^= 1; 1175 td->tt_scheduled = 0; 1176 } 1177 1178 /* verify the packet byte count */ 1179 if (count > td->remainder) { 1180 /* invalid USB packet */ 1181 td->error_any = 1; 1182 1183 /* release FIFO */ 1184 dwc_otg_common_rx_ack(sc); 1185 goto complete; 1186 } 1187 1188 usbd_copy_in(td->pc, td->offset, 1189 sc->sc_rx_bounce_buffer, count); 1190 1191 td->remainder -= count; 1192 td->offset += count; 1193 sc->sc_chan_state[channel].hcint |= HCINT_SOFTWARE_ONLY; 1194 break; 1195 default: 1196 break; 1197 } 1198 /* release FIFO */ 1199 dwc_otg_common_rx_ack(sc); 1200 busy: 1201 return (0); 1202 complete: 1203 return (1); 1204 } 1205 1206 static uint8_t 1207 dwc_otg_host_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1208 { 1209 uint32_t hcint; 1210 uint32_t hcchar; 1211 uint8_t delta; 1212 uint8_t channel; 1213 1214 channel = td->channel; 1215 1216 if (channel < DWC_OTG_MAX_CHANNELS) { 1217 hcint = sc->sc_chan_state[channel].hcint; 1218 1219 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1220 channel, td->state, hcint, 1221 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1222 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1223 1224 /* check interrupt bits */ 1225 if (hcint & (HCINT_RETRY | 1226 HCINT_ACK | HCINT_NYET)) { 1227 /* give success bits priority over failure bits */ 1228 } else if (hcint & HCINT_STALL) { 1229 DPRINTF("CH=%d STALL\n", channel); 1230 td->error_stall = 1; 1231 td->error_any = 1; 1232 goto complete; 1233 } else if (hcint & HCINT_ERRORS) { 1234 DPRINTF("CH=%d ERROR\n", channel); 1235 td->errcnt++; 1236 if (td->hcsplt != 0 || td->errcnt >= 3) { 1237 if (td->ep_type != UE_ISOCHRONOUS) { 1238 td->error_any = 1; 1239 goto complete; 1240 } 1241 } 1242 } 1243 1244 /* check channels for data, if any */ 1245 if (dwc_otg_host_data_rx_sub(sc, td)) 1246 goto complete; 1247 1248 /* refresh interrupt status */ 1249 hcint = sc->sc_chan_state[channel].hcint; 1250 1251 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1252 HCINT_ACK | HCINT_NYET)) { 1253 if (!(hcint & HCINT_ERRORS)) 1254 td->errcnt = 0; 1255 } 1256 } else { 1257 hcint = 0; 1258 } 1259 1260 switch (td->state) { 1261 case DWC_CHAN_ST_START: 1262 if (td->hcsplt != 0) 1263 goto receive_spkt; 1264 else 1265 goto receive_pkt; 1266 1267 case DWC_CHAN_ST_WAIT_ANE: 1268 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1269 if (td->ep_type == UE_INTERRUPT) { 1270 /* 1271 * The USB specification does not 1272 * mandate a particular data toggle 1273 * value for USB INTERRUPT 1274 * transfers. Switch the data toggle 1275 * value to receive the packet 1276 * correctly: 1277 */ 1278 if (hcint & HCINT_DATATGLERR) { 1279 DPRINTF("Retrying packet due to " 1280 "data toggle error\n"); 1281 td->toggle ^= 1; 1282 goto receive_pkt; 1283 } 1284 } 1285 td->did_nak++; 1286 td->tt_scheduled = 0; 1287 if (td->hcsplt != 0) 1288 goto receive_spkt; 1289 else 1290 goto receive_pkt; 1291 } else if (hcint & HCINT_NYET) { 1292 if (td->hcsplt != 0) { 1293 /* try again */ 1294 goto receive_pkt; 1295 } else { 1296 /* not a valid token for IN endpoints */ 1297 td->error_any = 1; 1298 goto complete; 1299 } 1300 } else if (hcint & HCINT_ACK) { 1301 /* wait for data - ACK arrived first */ 1302 if (!(hcint & HCINT_SOFTWARE_ONLY)) 1303 goto busy; 1304 1305 if (td->ep_type == UE_ISOCHRONOUS) { 1306 /* check if we are complete */ 1307 if ((td->remainder == 0) || 1308 (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN)) { 1309 goto complete; 1310 } 1311 /* get another packet */ 1312 goto receive_pkt; 1313 } else { 1314 /* check if we are complete */ 1315 if ((td->remainder == 0) || (td->got_short != 0)) { 1316 if (td->short_pkt) 1317 goto complete; 1318 1319 /* 1320 * Else need to receive a zero length 1321 * packet. 1322 */ 1323 } 1324 td->tt_scheduled = 0; 1325 td->did_nak = 0; 1326 if (td->hcsplt != 0) 1327 goto receive_spkt; 1328 else 1329 goto receive_pkt; 1330 } 1331 } 1332 break; 1333 1334 case DWC_CHAN_ST_WAIT_S_ANE: 1335 /* 1336 * NOTE: The DWC OTG hardware provides a fake ACK in 1337 * case of interrupt and isochronous transfers: 1338 */ 1339 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1340 td->did_nak++; 1341 td->tt_scheduled = 0; 1342 goto receive_spkt; 1343 } else if (hcint & HCINT_NYET) { 1344 td->tt_scheduled = 0; 1345 goto receive_spkt; 1346 } else if (hcint & HCINT_ACK) { 1347 td->did_nak = 0; 1348 goto receive_pkt; 1349 } 1350 break; 1351 1352 case DWC_CHAN_ST_WAIT_C_PKT: 1353 goto receive_pkt; 1354 1355 default: 1356 break; 1357 } 1358 goto busy; 1359 1360 receive_pkt: 1361 /* free existing channel, if any */ 1362 dwc_otg_host_channel_free(sc, td); 1363 1364 if (td->hcsplt != 0) { 1365 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1366 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1367 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1368 goto busy; 1369 } 1370 delta = sc->sc_last_frame_num - td->tt_start_slot; 1371 if (delta > DWC_OTG_TT_SLOT_MAX) { 1372 if (td->ep_type != UE_ISOCHRONOUS) { 1373 /* we missed the service interval */ 1374 td->error_any = 1; 1375 } 1376 goto complete; 1377 } 1378 /* complete split */ 1379 td->hcsplt |= HCSPLT_COMPSPLT; 1380 } else if (td->tt_xactpos == HCSPLT_XACTPOS_BEGIN && 1381 dwc_otg_host_rate_check(sc, td)) { 1382 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1383 goto busy; 1384 } 1385 1386 /* allocate a new channel */ 1387 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1388 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1389 goto busy; 1390 } 1391 1392 channel = td->channel; 1393 1394 /* set toggle, if any */ 1395 if (td->set_toggle) { 1396 td->set_toggle = 0; 1397 td->toggle = 1; 1398 } 1399 1400 td->state = DWC_CHAN_ST_WAIT_ANE; 1401 1402 /* receive one packet */ 1403 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1404 (td->max_packet_size << HCTSIZ_XFERSIZE_SHIFT) | 1405 (1 << HCTSIZ_PKTCNT_SHIFT) | 1406 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1407 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1408 1409 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1410 1411 hcchar = td->hcchar; 1412 hcchar |= HCCHAR_EPDIR_IN; 1413 1414 /* receive complete split ASAP */ 1415 if ((sc->sc_last_frame_num & 1) != 0) 1416 hcchar |= HCCHAR_ODDFRM; 1417 else 1418 hcchar &= ~HCCHAR_ODDFRM; 1419 1420 /* must enable channel before data can be received */ 1421 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1422 1423 /* wait until next slot before trying complete split */ 1424 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1425 1426 goto busy; 1427 1428 receive_spkt: 1429 /* free existing channel(s), if any */ 1430 dwc_otg_host_channel_free(sc, td); 1431 1432 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1433 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1434 td->state = DWC_CHAN_ST_START; 1435 goto busy; 1436 } 1437 delta = sc->sc_last_frame_num - td->tt_start_slot; 1438 if (delta > 5) { 1439 /* missed it */ 1440 td->tt_scheduled = 0; 1441 td->state = DWC_CHAN_ST_START; 1442 goto busy; 1443 } 1444 1445 /* allocate a new channel */ 1446 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1447 td->state = DWC_CHAN_ST_START; 1448 goto busy; 1449 } 1450 1451 channel = td->channel; 1452 1453 td->hcsplt &= ~HCSPLT_COMPSPLT; 1454 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1455 1456 /* receive one packet */ 1457 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1458 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1459 1460 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1461 1462 /* send after next SOF event */ 1463 if ((sc->sc_last_frame_num & 1) == 0) 1464 td->hcchar |= HCCHAR_ODDFRM; 1465 else 1466 td->hcchar &= ~HCCHAR_ODDFRM; 1467 1468 hcchar = td->hcchar; 1469 hcchar |= HCCHAR_EPDIR_IN; 1470 1471 /* wait until next slot before trying complete split */ 1472 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1473 1474 /* must enable channel before data can be received */ 1475 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1476 busy: 1477 return (1); /* busy */ 1478 1479 complete: 1480 dwc_otg_host_channel_free(sc, td); 1481 return (0); /* complete */ 1482 } 1483 1484 static uint8_t 1485 dwc_otg_data_rx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1486 { 1487 uint32_t temp; 1488 uint16_t count; 1489 uint8_t got_short; 1490 1491 got_short = 0; 1492 1493 /* check endpoint status */ 1494 if (sc->sc_last_rx_status == 0) 1495 goto not_complete; 1496 1497 if (GRXSTSRD_CHNUM_GET(sc->sc_last_rx_status) != td->ep_no) 1498 goto not_complete; 1499 1500 /* check for SETUP packet */ 1501 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) == 1502 GRXSTSRD_STP_DATA) { 1503 if (td->remainder == 0) { 1504 /* 1505 * We are actually complete and have 1506 * received the next SETUP 1507 */ 1508 DPRINTFN(5, "faking complete\n"); 1509 return (0); /* complete */ 1510 } 1511 /* 1512 * USB Host Aborted the transfer. 1513 */ 1514 td->error_any = 1; 1515 return (0); /* complete */ 1516 } 1517 1518 if ((sc->sc_last_rx_status & GRXSTSRD_PKTSTS_MASK) != 1519 GRXSTSRD_OUT_DATA) { 1520 /* release FIFO */ 1521 dwc_otg_common_rx_ack(sc); 1522 goto not_complete; 1523 } 1524 1525 /* get the packet byte count */ 1526 count = GRXSTSRD_BCNT_GET(sc->sc_last_rx_status); 1527 1528 /* verify the packet byte count */ 1529 if (count != td->max_packet_size) { 1530 if (count < td->max_packet_size) { 1531 /* we have a short packet */ 1532 td->short_pkt = 1; 1533 got_short = 1; 1534 } else { 1535 /* invalid USB packet */ 1536 td->error_any = 1; 1537 1538 /* release FIFO */ 1539 dwc_otg_common_rx_ack(sc); 1540 return (0); /* we are complete */ 1541 } 1542 } 1543 /* verify the packet byte count */ 1544 if (count > td->remainder) { 1545 /* invalid USB packet */ 1546 td->error_any = 1; 1547 1548 /* release FIFO */ 1549 dwc_otg_common_rx_ack(sc); 1550 return (0); /* we are complete */ 1551 } 1552 1553 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 1554 td->remainder -= count; 1555 td->offset += count; 1556 1557 /* release FIFO */ 1558 dwc_otg_common_rx_ack(sc); 1559 1560 temp = sc->sc_out_ctl[td->ep_no]; 1561 1562 /* check for isochronous mode */ 1563 if ((temp & DIEPCTL_EPTYPE_MASK) == 1564 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 1565 /* toggle odd or even frame bit */ 1566 if (temp & DIEPCTL_SETD1PID) { 1567 temp &= ~DIEPCTL_SETD1PID; 1568 temp |= DIEPCTL_SETD0PID; 1569 } else { 1570 temp &= ~DIEPCTL_SETD0PID; 1571 temp |= DIEPCTL_SETD1PID; 1572 } 1573 sc->sc_out_ctl[td->ep_no] = temp; 1574 } 1575 1576 /* check if we are complete */ 1577 if ((td->remainder == 0) || got_short) { 1578 if (td->short_pkt) { 1579 /* we are complete */ 1580 return (0); 1581 } 1582 /* else need to receive a zero length packet */ 1583 } 1584 1585 not_complete: 1586 1587 temp = sc->sc_out_ctl[td->ep_no]; 1588 1589 temp |= DOEPCTL_EPENA | DOEPCTL_CNAK; 1590 1591 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(td->ep_no), temp); 1592 1593 /* enable SETUP and transfer complete interrupt */ 1594 if (td->ep_no == 0) { 1595 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(0), 1596 DXEPTSIZ_SET_NPKT(1) | 1597 DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 1598 } else { 1599 /* allow reception of multiple packets */ 1600 DWC_OTG_WRITE_4(sc, DOTG_DOEPTSIZ(td->ep_no), 1601 DXEPTSIZ_SET_MULTI(1) | 1602 DXEPTSIZ_SET_NPKT(4) | 1603 DXEPTSIZ_SET_NBYTES(4 * 1604 ((td->max_packet_size + 3) & ~3))); 1605 } 1606 return (1); /* not complete */ 1607 } 1608 1609 static uint8_t 1610 dwc_otg_host_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1611 { 1612 uint32_t count; 1613 uint32_t hcint; 1614 uint32_t hcchar; 1615 uint8_t delta; 1616 uint8_t channel; 1617 1618 dwc_otg_host_dump_rx(sc, td); 1619 1620 channel = td->channel; 1621 1622 if (channel < DWC_OTG_MAX_CHANNELS) { 1623 hcint = sc->sc_chan_state[channel].hcint; 1624 1625 DPRINTF("CH=%d ST=%d HCINT=0x%08x HCCHAR=0x%08x HCTSIZ=0x%08x\n", 1626 channel, td->state, hcint, 1627 DWC_OTG_READ_4(sc, DOTG_HCCHAR(channel)), 1628 DWC_OTG_READ_4(sc, DOTG_HCTSIZ(channel))); 1629 1630 if (hcint & (HCINT_RETRY | 1631 HCINT_ACK | HCINT_NYET)) { 1632 /* give success bits priority over failure bits */ 1633 } else if (hcint & HCINT_STALL) { 1634 DPRINTF("CH=%d STALL\n", channel); 1635 td->error_stall = 1; 1636 td->error_any = 1; 1637 goto complete; 1638 } else if (hcint & HCINT_ERRORS) { 1639 DPRINTF("CH=%d ERROR\n", channel); 1640 td->errcnt++; 1641 if (td->hcsplt != 0 || td->errcnt >= 3) { 1642 td->error_any = 1; 1643 goto complete; 1644 } 1645 } 1646 1647 if (hcint & (HCINT_ERRORS | HCINT_RETRY | 1648 HCINT_ACK | HCINT_NYET)) { 1649 1650 if (!(hcint & HCINT_ERRORS)) 1651 td->errcnt = 0; 1652 } 1653 } else { 1654 hcint = 0; 1655 } 1656 1657 switch (td->state) { 1658 case DWC_CHAN_ST_START: 1659 goto send_pkt; 1660 1661 case DWC_CHAN_ST_WAIT_ANE: 1662 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1663 td->did_nak++; 1664 td->tt_scheduled = 0; 1665 goto send_pkt; 1666 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1667 td->offset += td->tx_bytes; 1668 td->remainder -= td->tx_bytes; 1669 td->toggle ^= 1; 1670 td->did_nak = 0; 1671 td->tt_scheduled = 0; 1672 1673 /* check remainder */ 1674 if (td->remainder == 0) { 1675 if (td->short_pkt) 1676 goto complete; 1677 1678 /* 1679 * Else we need to transmit a short 1680 * packet: 1681 */ 1682 } 1683 goto send_pkt; 1684 } 1685 break; 1686 1687 case DWC_CHAN_ST_WAIT_S_ANE: 1688 if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1689 td->did_nak++; 1690 td->tt_scheduled = 0; 1691 goto send_pkt; 1692 } else if (hcint & (HCINT_ACK | HCINT_NYET)) { 1693 td->did_nak = 0; 1694 goto send_cpkt; 1695 } 1696 break; 1697 1698 case DWC_CHAN_ST_WAIT_C_ANE: 1699 if (hcint & HCINT_NYET) { 1700 goto send_cpkt; 1701 } else if (hcint & (HCINT_RETRY | HCINT_ERRORS)) { 1702 td->did_nak++; 1703 td->tt_scheduled = 0; 1704 goto send_pkt; 1705 } else if (hcint & HCINT_ACK) { 1706 td->offset += td->tx_bytes; 1707 td->remainder -= td->tx_bytes; 1708 td->toggle ^= 1; 1709 td->did_nak = 0; 1710 td->tt_scheduled = 0; 1711 1712 /* check remainder */ 1713 if (td->remainder == 0) { 1714 if (td->short_pkt) 1715 goto complete; 1716 1717 /* else we need to transmit a short packet */ 1718 } 1719 goto send_pkt; 1720 } 1721 break; 1722 1723 case DWC_CHAN_ST_WAIT_C_PKT: 1724 goto send_cpkt; 1725 1726 case DWC_CHAN_ST_TX_WAIT_ISOC: 1727 1728 /* Check if isochronous OUT traffic is complete */ 1729 if ((hcint & HCINT_HCH_DONE_MASK) == 0) 1730 break; 1731 1732 td->offset += td->tx_bytes; 1733 td->remainder -= td->tx_bytes; 1734 1735 if (td->hcsplt != 0 || td->remainder == 0) 1736 goto complete; 1737 1738 /* check for next packet */ 1739 if (td->max_packet_count > 1) 1740 td->tt_xactpos++; 1741 1742 /* free existing channel, if any */ 1743 dwc_otg_host_channel_free(sc, td); 1744 1745 td->state = DWC_CHAN_ST_TX_PKT_ISOC; 1746 1747 /* FALLTHROUGH */ 1748 1749 case DWC_CHAN_ST_TX_PKT_ISOC: 1750 if (dwc_otg_host_channel_alloc(sc, td, 1)) 1751 break; 1752 channel = td->channel; 1753 goto send_isoc_pkt; 1754 default: 1755 break; 1756 } 1757 goto busy; 1758 1759 send_pkt: 1760 /* free existing channel(s), if any */ 1761 dwc_otg_host_channel_free(sc, td); 1762 1763 if (td->hcsplt != 0) { 1764 delta = td->tt_start_slot - sc->sc_last_frame_num - 1; 1765 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1766 td->state = DWC_CHAN_ST_START; 1767 goto busy; 1768 } 1769 delta = sc->sc_last_frame_num - td->tt_start_slot; 1770 if (delta > 5) { 1771 /* missed it */ 1772 td->tt_scheduled = 0; 1773 td->state = DWC_CHAN_ST_START; 1774 goto busy; 1775 } 1776 } else if (dwc_otg_host_rate_check(sc, td)) { 1777 td->state = DWC_CHAN_ST_START; 1778 goto busy; 1779 } 1780 1781 /* allocate a new channel */ 1782 if (dwc_otg_host_channel_alloc(sc, td, 1)) { 1783 td->state = DWC_CHAN_ST_START; 1784 goto busy; 1785 } 1786 1787 channel = td->channel; 1788 1789 /* set toggle, if any */ 1790 if (td->set_toggle) { 1791 td->set_toggle = 0; 1792 td->toggle = 1; 1793 } 1794 1795 if (td->ep_type == UE_ISOCHRONOUS) { 1796 send_isoc_pkt: 1797 /* Isochronous OUT transfers don't have any ACKs */ 1798 td->state = DWC_CHAN_ST_TX_WAIT_ISOC; 1799 td->hcsplt &= ~HCSPLT_COMPSPLT; 1800 if (td->hcsplt != 0) { 1801 /* get maximum transfer length */ 1802 count = td->remainder; 1803 if (count > HCSPLT_XACTLEN_BURST) { 1804 DPRINTF("TT overflow\n"); 1805 td->error_any = 1; 1806 goto complete; 1807 } 1808 /* Update transaction position */ 1809 td->hcsplt &= ~HCSPLT_XACTPOS_MASK; 1810 td->hcsplt |= (HCSPLT_XACTPOS_ALL << HCSPLT_XACTPOS_SHIFT); 1811 } else { 1812 /* send one packet at a time */ 1813 count = td->max_packet_size; 1814 if (td->remainder < count) { 1815 /* we have a short packet */ 1816 td->short_pkt = 1; 1817 count = td->remainder; 1818 } 1819 } 1820 } else if (td->hcsplt != 0) { 1821 1822 td->hcsplt &= ~HCSPLT_COMPSPLT; 1823 1824 /* Wait for ACK/NAK/ERR from TT */ 1825 td->state = DWC_CHAN_ST_WAIT_S_ANE; 1826 1827 /* send one packet at a time */ 1828 count = td->max_packet_size; 1829 if (td->remainder < count) { 1830 /* we have a short packet */ 1831 td->short_pkt = 1; 1832 count = td->remainder; 1833 } 1834 } else { 1835 /* Wait for ACK/NAK/STALL from device */ 1836 td->state = DWC_CHAN_ST_WAIT_ANE; 1837 1838 /* send one packet at a time */ 1839 count = td->max_packet_size; 1840 if (td->remainder < count) { 1841 /* we have a short packet */ 1842 td->short_pkt = 1; 1843 count = td->remainder; 1844 } 1845 } 1846 1847 /* check for High-Speed multi-packets */ 1848 if ((td->hcsplt == 0) && (td->max_packet_count > 1)) { 1849 if (td->npkt == 0) { 1850 if (td->remainder >= (3 * td->max_packet_size)) 1851 td->npkt = 3; 1852 else if (td->remainder >= (2 * td->max_packet_size)) 1853 td->npkt = 2; 1854 else 1855 td->npkt = 1; 1856 1857 if (td->npkt > td->max_packet_count) 1858 td->npkt = td->max_packet_count; 1859 1860 td->tt_xactpos = 1; /* overload */ 1861 } 1862 if (td->tt_xactpos == td->npkt) { 1863 if (td->npkt == 1) { 1864 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1865 (count << HCTSIZ_XFERSIZE_SHIFT) | 1866 (1 << HCTSIZ_PKTCNT_SHIFT) | 1867 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1868 } else if (td->npkt == 2) { 1869 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1870 (count << HCTSIZ_XFERSIZE_SHIFT) | 1871 (1 << HCTSIZ_PKTCNT_SHIFT) | 1872 (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT)); 1873 } else { 1874 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1875 (count << HCTSIZ_XFERSIZE_SHIFT) | 1876 (1 << HCTSIZ_PKTCNT_SHIFT) | 1877 (HCTSIZ_PID_DATA2 << HCTSIZ_PID_SHIFT)); 1878 } 1879 td->npkt = 0; 1880 } else { 1881 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1882 (count << HCTSIZ_XFERSIZE_SHIFT) | 1883 (1 << HCTSIZ_PKTCNT_SHIFT) | 1884 (HCTSIZ_PID_MDATA << HCTSIZ_PID_SHIFT)); 1885 } 1886 } else { 1887 /* TODO: HCTSIZ_DOPNG */ 1888 1889 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1890 (count << HCTSIZ_XFERSIZE_SHIFT) | 1891 (1 << HCTSIZ_PKTCNT_SHIFT) | 1892 (td->toggle ? (HCTSIZ_PID_DATA1 << HCTSIZ_PID_SHIFT) : 1893 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT))); 1894 } 1895 1896 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1897 1898 hcchar = td->hcchar; 1899 hcchar &= ~HCCHAR_EPDIR_IN; 1900 1901 /* send after next SOF event */ 1902 if ((sc->sc_last_frame_num & 1) == 0) 1903 hcchar |= HCCHAR_ODDFRM; 1904 else 1905 hcchar &= ~HCCHAR_ODDFRM; 1906 1907 /* must enable before writing data to FIFO */ 1908 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1909 1910 if (count != 0) { 1911 1912 /* clear topmost word before copy */ 1913 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 1914 1915 /* copy out data */ 1916 usbd_copy_out(td->pc, td->offset, 1917 sc->sc_tx_bounce_buffer, count); 1918 1919 /* transfer data into FIFO */ 1920 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 1921 DOTG_DFIFO(channel), 1922 sc->sc_tx_bounce_buffer, (count + 3) / 4); 1923 } 1924 1925 /* store number of bytes transmitted */ 1926 td->tx_bytes = count; 1927 goto busy; 1928 1929 send_cpkt: 1930 /* free existing channel, if any */ 1931 dwc_otg_host_channel_free(sc, td); 1932 1933 delta = td->tt_complete_slot - sc->sc_last_frame_num - 1; 1934 if (td->tt_scheduled == 0 || delta < DWC_OTG_TT_SLOT_MAX) { 1935 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1936 goto busy; 1937 } 1938 delta = sc->sc_last_frame_num - td->tt_start_slot; 1939 if (delta > DWC_OTG_TT_SLOT_MAX) { 1940 /* we missed the service interval */ 1941 if (td->ep_type != UE_ISOCHRONOUS) 1942 td->error_any = 1; 1943 goto complete; 1944 } 1945 1946 /* allocate a new channel */ 1947 if (dwc_otg_host_channel_alloc(sc, td, 0)) { 1948 td->state = DWC_CHAN_ST_WAIT_C_PKT; 1949 goto busy; 1950 } 1951 1952 channel = td->channel; 1953 1954 td->hcsplt |= HCSPLT_COMPSPLT; 1955 td->state = DWC_CHAN_ST_WAIT_C_ANE; 1956 1957 DWC_OTG_WRITE_4(sc, DOTG_HCTSIZ(channel), 1958 (HCTSIZ_PID_DATA0 << HCTSIZ_PID_SHIFT)); 1959 1960 DWC_OTG_WRITE_4(sc, DOTG_HCSPLT(channel), td->hcsplt); 1961 1962 hcchar = td->hcchar; 1963 hcchar &= ~HCCHAR_EPDIR_IN; 1964 1965 /* receive complete split ASAP */ 1966 if ((sc->sc_last_frame_num & 1) != 0) 1967 hcchar |= HCCHAR_ODDFRM; 1968 else 1969 hcchar &= ~HCCHAR_ODDFRM; 1970 1971 /* must enable channel before data can be received */ 1972 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(channel), hcchar); 1973 1974 /* wait until next slot before trying complete split */ 1975 td->tt_complete_slot = sc->sc_last_frame_num + 1; 1976 busy: 1977 return (1); /* busy */ 1978 1979 complete: 1980 dwc_otg_host_channel_free(sc, td); 1981 return (0); /* complete */ 1982 } 1983 1984 static uint8_t 1985 dwc_otg_data_tx(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 1986 { 1987 uint32_t max_buffer; 1988 uint32_t count; 1989 uint32_t fifo_left; 1990 uint32_t mpkt; 1991 uint32_t temp; 1992 uint8_t to; 1993 1994 to = 3; /* don't loop forever! */ 1995 1996 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 1997 1998 repeat: 1999 /* check for for endpoint 0 data */ 2000 2001 temp = sc->sc_last_rx_status; 2002 2003 if ((td->ep_no == 0) && (temp != 0) && 2004 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2005 2006 if ((temp & GRXSTSRD_PKTSTS_MASK) != 2007 GRXSTSRD_STP_DATA) { 2008 2009 /* dump data - wrong direction */ 2010 dwc_otg_common_rx_ack(sc); 2011 } else { 2012 /* 2013 * The current transfer was cancelled 2014 * by the USB Host: 2015 */ 2016 td->error_any = 1; 2017 return (0); /* complete */ 2018 } 2019 } 2020 2021 /* fill in more TX data, if possible */ 2022 if (td->tx_bytes != 0) { 2023 2024 uint16_t cpkt; 2025 2026 /* check if packets have been transferred */ 2027 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2028 2029 /* get current packet number */ 2030 cpkt = DXEPTSIZ_GET_NPKT(temp); 2031 2032 if (cpkt >= td->npkt) { 2033 fifo_left = 0; 2034 } else { 2035 if (max_buffer != 0) { 2036 fifo_left = (td->npkt - cpkt) * 2037 td->max_packet_size; 2038 2039 if (fifo_left > max_buffer) 2040 fifo_left = max_buffer; 2041 } else { 2042 fifo_left = td->max_packet_size; 2043 } 2044 } 2045 2046 count = td->tx_bytes; 2047 if (count > fifo_left) 2048 count = fifo_left; 2049 2050 if (count != 0) { 2051 2052 /* clear topmost word before copy */ 2053 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 2054 2055 /* copy out data */ 2056 usbd_copy_out(td->pc, td->offset, 2057 sc->sc_tx_bounce_buffer, count); 2058 2059 /* transfer data into FIFO */ 2060 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2061 DOTG_DFIFO(td->ep_no), 2062 sc->sc_tx_bounce_buffer, (count + 3) / 4); 2063 2064 td->tx_bytes -= count; 2065 td->remainder -= count; 2066 td->offset += count; 2067 td->npkt = cpkt; 2068 } 2069 if (td->tx_bytes != 0) 2070 goto not_complete; 2071 2072 /* check remainder */ 2073 if (td->remainder == 0) { 2074 if (td->short_pkt) 2075 return (0); /* complete */ 2076 2077 /* else we need to transmit a short packet */ 2078 } 2079 } 2080 2081 if (!to--) 2082 goto not_complete; 2083 2084 /* check if not all packets have been transferred */ 2085 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2086 2087 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2088 2089 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 2090 "DIEPCTL=0x%08x\n", td->ep_no, 2091 DXEPTSIZ_GET_NPKT(temp), 2092 temp, DWC_OTG_READ_4(sc, DOTG_DIEPCTL(td->ep_no))); 2093 2094 goto not_complete; 2095 } 2096 2097 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 2098 2099 /* try to optimise by sending more data */ 2100 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 2101 2102 /* send multiple packets at the same time */ 2103 mpkt = max_buffer / td->max_packet_size; 2104 2105 if (mpkt > 0x3FE) 2106 mpkt = 0x3FE; 2107 2108 count = td->remainder; 2109 if (count > 0x7FFFFF) 2110 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 2111 2112 td->npkt = count / td->max_packet_size; 2113 2114 /* 2115 * NOTE: We could use 0x3FE instead of "mpkt" in the 2116 * check below to get more throughput, but then we 2117 * have a dependency towards non-generic chip features 2118 * to disable the TX-FIFO-EMPTY interrupts on a per 2119 * endpoint basis. Increase the maximum buffer size of 2120 * the IN endpoint to increase the performance. 2121 */ 2122 if (td->npkt > mpkt) { 2123 td->npkt = mpkt; 2124 count = td->max_packet_size * mpkt; 2125 } else if ((count == 0) || (count % td->max_packet_size)) { 2126 /* we are transmitting a short packet */ 2127 td->npkt++; 2128 td->short_pkt = 1; 2129 } 2130 } else { 2131 /* send one packet at a time */ 2132 mpkt = 1; 2133 count = td->max_packet_size; 2134 if (td->remainder < count) { 2135 /* we have a short packet */ 2136 td->short_pkt = 1; 2137 count = td->remainder; 2138 } 2139 td->npkt = 1; 2140 } 2141 DWC_OTG_WRITE_4(sc, DOTG_DIEPTSIZ(td->ep_no), 2142 DXEPTSIZ_SET_MULTI(1) | 2143 DXEPTSIZ_SET_NPKT(td->npkt) | 2144 DXEPTSIZ_SET_NBYTES(count)); 2145 2146 /* make room for buffering */ 2147 td->npkt += mpkt; 2148 2149 temp = sc->sc_in_ctl[td->ep_no]; 2150 2151 /* check for isochronous mode */ 2152 if ((temp & DIEPCTL_EPTYPE_MASK) == 2153 (DIEPCTL_EPTYPE_ISOC << DIEPCTL_EPTYPE_SHIFT)) { 2154 /* toggle odd or even frame bit */ 2155 if (temp & DIEPCTL_SETD1PID) { 2156 temp &= ~DIEPCTL_SETD1PID; 2157 temp |= DIEPCTL_SETD0PID; 2158 } else { 2159 temp &= ~DIEPCTL_SETD0PID; 2160 temp |= DIEPCTL_SETD1PID; 2161 } 2162 sc->sc_in_ctl[td->ep_no] = temp; 2163 } 2164 2165 /* must enable before writing data to FIFO */ 2166 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(td->ep_no), temp | 2167 DIEPCTL_EPENA | DIEPCTL_CNAK); 2168 2169 td->tx_bytes = count; 2170 2171 /* check remainder */ 2172 if (td->tx_bytes == 0 && 2173 td->remainder == 0) { 2174 if (td->short_pkt) 2175 return (0); /* complete */ 2176 2177 /* else we need to transmit a short packet */ 2178 } 2179 goto repeat; 2180 2181 not_complete: 2182 return (1); /* not complete */ 2183 } 2184 2185 static uint8_t 2186 dwc_otg_data_tx_sync(struct dwc_otg_softc *sc, struct dwc_otg_td *td) 2187 { 2188 uint32_t temp; 2189 2190 /* 2191 * If all packets are transferred we are complete: 2192 */ 2193 temp = DWC_OTG_READ_4(sc, DOTG_DIEPTSIZ(td->ep_no)); 2194 2195 /* check that all packets have been transferred */ 2196 if (DXEPTSIZ_GET_NPKT(temp) != 0) { 2197 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 2198 goto not_complete; 2199 } 2200 return (0); 2201 2202 not_complete: 2203 2204 /* we only want to know if there is a SETUP packet or free IN packet */ 2205 2206 temp = sc->sc_last_rx_status; 2207 2208 if ((td->ep_no == 0) && (temp != 0) && 2209 (GRXSTSRD_CHNUM_GET(temp) == 0)) { 2210 2211 if ((temp & GRXSTSRD_PKTSTS_MASK) == 2212 GRXSTSRD_STP_DATA) { 2213 DPRINTFN(5, "faking complete\n"); 2214 /* 2215 * Race condition: We are complete! 2216 */ 2217 return (0); 2218 } else { 2219 /* dump data - wrong direction */ 2220 dwc_otg_common_rx_ack(sc); 2221 } 2222 } 2223 return (1); /* not complete */ 2224 } 2225 2226 static void 2227 dwc_otg_xfer_do_fifo(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2228 { 2229 struct dwc_otg_td *td; 2230 uint8_t toggle; 2231 uint8_t tmr_val; 2232 uint8_t tmr_res; 2233 2234 DPRINTFN(9, "\n"); 2235 2236 td = xfer->td_transfer_cache; 2237 if (td == NULL) 2238 return; 2239 2240 while (1) { 2241 if ((td->func) (sc, td)) { 2242 /* operation in progress */ 2243 break; 2244 } 2245 if (((void *)td) == xfer->td_transfer_last) { 2246 goto done; 2247 } 2248 if (td->error_any) { 2249 goto done; 2250 } else if (td->remainder > 0) { 2251 /* 2252 * We had a short transfer. If there is no alternate 2253 * next, stop processing ! 2254 */ 2255 if (!td->alt_next) 2256 goto done; 2257 } 2258 2259 /* 2260 * Fetch the next transfer descriptor and transfer 2261 * some flags to the next transfer descriptor 2262 */ 2263 tmr_res = td->tmr_res; 2264 tmr_val = td->tmr_val; 2265 toggle = td->toggle; 2266 td = td->obj_next; 2267 xfer->td_transfer_cache = td; 2268 td->toggle = toggle; /* transfer toggle */ 2269 td->tmr_res = tmr_res; 2270 td->tmr_val = tmr_val; 2271 } 2272 return; 2273 2274 done: 2275 xfer->td_transfer_cache = NULL; 2276 sc->sc_xfer_complete = 1; 2277 } 2278 2279 static uint8_t 2280 dwc_otg_xfer_do_complete_locked(struct dwc_otg_softc *sc, struct usb_xfer *xfer) 2281 { 2282 struct dwc_otg_td *td; 2283 2284 DPRINTFN(9, "\n"); 2285 2286 td = xfer->td_transfer_cache; 2287 if (td == NULL) { 2288 /* compute all actual lengths */ 2289 dwc_otg_standard_done(xfer); 2290 return (1); 2291 } 2292 return (0); 2293 } 2294 2295 static void 2296 dwc_otg_timer(void *_sc) 2297 { 2298 struct dwc_otg_softc *sc = _sc; 2299 struct usb_xfer *xfer; 2300 struct dwc_otg_td *td; 2301 2302 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2303 2304 DPRINTF("\n"); 2305 2306 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2307 2308 /* increment timer value */ 2309 sc->sc_tmr_val++; 2310 2311 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2312 td = xfer->td_transfer_cache; 2313 if (td != NULL) { 2314 /* reset NAK counter */ 2315 td->did_nak = 0; 2316 } 2317 } 2318 2319 /* enable SOF interrupt, which will poll jobs */ 2320 dwc_otg_enable_sof_irq(sc); 2321 2322 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2323 2324 if (sc->sc_timer_active) { 2325 /* restart timer */ 2326 usb_callout_reset(&sc->sc_timer, 2327 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2328 &dwc_otg_timer, sc); 2329 } 2330 } 2331 2332 static void 2333 dwc_otg_timer_start(struct dwc_otg_softc *sc) 2334 { 2335 if (sc->sc_timer_active != 0) 2336 return; 2337 2338 sc->sc_timer_active = 1; 2339 2340 /* restart timer */ 2341 usb_callout_reset(&sc->sc_timer, 2342 hz / (1000 / DWC_OTG_HOST_TIMER_RATE), 2343 &dwc_otg_timer, sc); 2344 } 2345 2346 static void 2347 dwc_otg_timer_stop(struct dwc_otg_softc *sc) 2348 { 2349 if (sc->sc_timer_active == 0) 2350 return; 2351 2352 sc->sc_timer_active = 0; 2353 2354 /* stop timer */ 2355 usb_callout_stop(&sc->sc_timer); 2356 } 2357 2358 static void 2359 dwc_otg_host_channel_disable(struct dwc_otg_softc *sc, uint8_t x) 2360 { 2361 uint32_t hcchar; 2362 2363 hcchar = DWC_OTG_READ_4(sc, DOTG_HCCHAR(x)); 2364 2365 /* disable host channel, if any */ 2366 if (hcchar & (HCCHAR_CHENA | HCCHAR_CHDIS)) { 2367 /* disable channel */ 2368 DWC_OTG_WRITE_4(sc, DOTG_HCCHAR(x), 2369 HCCHAR_CHENA | HCCHAR_CHDIS); 2370 /* wait for chip to get its brains in order */ 2371 sc->sc_chan_state[x].wait_sof = 2; 2372 } 2373 2374 /* release TX FIFO usage, if any */ 2375 sc->sc_tx_cur_p_level -= sc->sc_chan_state[x].tx_p_size; 2376 sc->sc_tx_cur_np_level -= sc->sc_chan_state[x].tx_np_size; 2377 2378 /* don't release TX FIFO usage twice */ 2379 sc->sc_chan_state[x].tx_p_size = 0; 2380 sc->sc_chan_state[x].tx_np_size = 0; 2381 } 2382 2383 static uint16_t 2384 dwc_otg_compute_isoc_rx_tt_slot(struct dwc_otg_tt_info *pinfo) 2385 { 2386 if (pinfo->slot_index < DWC_OTG_TT_SLOT_MAX) 2387 pinfo->slot_index++; 2388 return (pinfo->slot_index); 2389 } 2390 2391 static uint8_t 2392 dwc_otg_update_host_transfer_schedule_locked(struct dwc_otg_softc *sc) 2393 { 2394 TAILQ_HEAD(, usb_xfer) head; 2395 struct usb_xfer *xfer; 2396 struct usb_xfer *xfer_next; 2397 struct dwc_otg_td *td; 2398 uint16_t temp; 2399 uint16_t slot; 2400 uint8_t x; 2401 2402 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM) & DWC_OTG_FRAME_MASK; 2403 2404 if (sc->sc_last_frame_num == temp) 2405 return (0); 2406 2407 sc->sc_last_frame_num = temp; 2408 2409 TAILQ_INIT(&head); 2410 2411 for (x = 0; x != sc->sc_host_ch_max; x++) { 2412 if (sc->sc_chan_state[x].wait_sof == 0) 2413 continue; 2414 2415 sc->sc_needsof = 1; 2416 if (--(sc->sc_chan_state[x].wait_sof) == 0) 2417 dwc_otg_host_channel_disable(sc, x); 2418 } 2419 2420 if ((temp & 7) == 0) { 2421 2422 /* reset the schedule */ 2423 memset(sc->sc_tt_info, 0, sizeof(sc->sc_tt_info)); 2424 2425 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2426 td = xfer->td_transfer_cache; 2427 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2428 continue; 2429 2430 /* check for IN direction */ 2431 if ((td->hcchar & HCCHAR_EPDIR_IN) != 0) 2432 continue; 2433 2434 /* execute more frames */ 2435 td->tmr_val = 0; 2436 2437 sc->sc_needsof = 1; 2438 2439 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2440 continue; 2441 2442 /* compute slot */ 2443 slot = dwc_otg_compute_isoc_rx_tt_slot( 2444 sc->sc_tt_info + td->tt_index); 2445 if (slot > 3) { 2446 /* 2447 * Not enough time to get complete 2448 * split executed. 2449 */ 2450 continue; 2451 } 2452 /* Delayed start */ 2453 td->tt_start_slot = temp + slot; 2454 td->tt_scheduled = 1; 2455 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2456 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2457 } 2458 2459 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2460 td = xfer->td_transfer_cache; 2461 if (td == NULL || td->ep_type != UE_ISOCHRONOUS) 2462 continue; 2463 2464 /* check for OUT direction */ 2465 if ((td->hcchar & HCCHAR_EPDIR_IN) == 0) 2466 continue; 2467 2468 /* execute more frames */ 2469 td->tmr_val = 0; 2470 2471 sc->sc_needsof = 1; 2472 2473 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2474 continue; 2475 2476 /* Start ASAP */ 2477 td->tt_start_slot = temp; 2478 td->tt_scheduled = 1; 2479 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2480 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2481 } 2482 2483 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2484 td = xfer->td_transfer_cache; 2485 if (td == NULL || td->ep_type != UE_INTERRUPT) 2486 continue; 2487 2488 if (td->tt_scheduled != 0) { 2489 sc->sc_needsof = 1; 2490 continue; 2491 } 2492 2493 if (dwc_otg_host_rate_check_interrupt(sc, td)) 2494 continue; 2495 2496 if (td->hcsplt == 0) { 2497 sc->sc_needsof = 1; 2498 td->tt_scheduled = 1; 2499 continue; 2500 } 2501 2502 /* start ASAP */ 2503 td->tt_start_slot = temp; 2504 sc->sc_needsof = 1; 2505 td->tt_scheduled = 1; 2506 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2507 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2508 } 2509 2510 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2511 td = xfer->td_transfer_cache; 2512 if (td == NULL || 2513 td->ep_type != UE_CONTROL || 2514 td->did_nak >= DWC_OTG_NAK_MAX) { 2515 continue; 2516 } 2517 2518 sc->sc_needsof = 1; 2519 2520 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2521 continue; 2522 2523 /* start ASAP */ 2524 td->tt_start_slot = temp; 2525 td->tt_scheduled = 1; 2526 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2527 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2528 } 2529 } 2530 if ((temp & 7) < 6) { 2531 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2532 td = xfer->td_transfer_cache; 2533 if (td == NULL || 2534 td->ep_type != UE_BULK || 2535 td->did_nak >= DWC_OTG_NAK_MAX) { 2536 continue; 2537 } 2538 2539 sc->sc_needsof = 1; 2540 2541 if (td->hcsplt == 0 || td->tt_scheduled != 0) 2542 continue; 2543 2544 /* start ASAP */ 2545 td->tt_start_slot = temp; 2546 td->tt_scheduled = 1; 2547 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2548 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2549 } 2550 } 2551 2552 /* Put TT transfers in execution order at the end */ 2553 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2554 2555 /* move all TT transfers in front, keeping the current order */ 2556 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2557 td = xfer->td_transfer_cache; 2558 if (td == NULL || td->hcsplt == 0) 2559 continue; 2560 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2561 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2562 } 2563 TAILQ_CONCAT(&head, &sc->sc_bus.intr_q.head, wait_entry); 2564 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2565 2566 /* put non-TT BULK transfers last */ 2567 TAILQ_FOREACH_SAFE(xfer, &sc->sc_bus.intr_q.head, wait_entry, xfer_next) { 2568 td = xfer->td_transfer_cache; 2569 if (td == NULL || td->hcsplt != 0 || td->ep_type != UE_BULK) 2570 continue; 2571 TAILQ_REMOVE(&sc->sc_bus.intr_q.head, xfer, wait_entry); 2572 TAILQ_INSERT_TAIL(&head, xfer, wait_entry); 2573 } 2574 TAILQ_CONCAT(&sc->sc_bus.intr_q.head, &head, wait_entry); 2575 2576 if ((temp & 7) == 0) { 2577 2578 DPRINTFN(12, "SOF interrupt #%d, needsof=%d\n", 2579 (int)temp, (int)sc->sc_needsof); 2580 2581 /* update SOF IRQ mask */ 2582 if (sc->sc_irq_mask & GINTMSK_SOFMSK) { 2583 if (sc->sc_needsof == 0) { 2584 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2585 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2586 } 2587 } else { 2588 if (sc->sc_needsof != 0) { 2589 sc->sc_irq_mask |= GINTMSK_SOFMSK; 2590 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2591 } 2592 } 2593 2594 /* clear need SOF flag */ 2595 sc->sc_needsof = 0; 2596 } 2597 return (1); 2598 } 2599 2600 static void 2601 dwc_otg_interrupt_poll_locked(struct dwc_otg_softc *sc) 2602 { 2603 struct usb_xfer *xfer; 2604 uint32_t temp; 2605 uint8_t got_rx_status; 2606 uint8_t x; 2607 2608 repeat: 2609 /* get all channel interrupts */ 2610 for (x = 0; x != sc->sc_host_ch_max; x++) { 2611 temp = DWC_OTG_READ_4(sc, DOTG_HCINT(x)); 2612 if (temp != 0) { 2613 DWC_OTG_WRITE_4(sc, DOTG_HCINT(x), temp); 2614 temp &= ~HCINT_SOFTWARE_ONLY; 2615 sc->sc_chan_state[x].hcint |= temp; 2616 } 2617 } 2618 2619 if (sc->sc_last_rx_status == 0) { 2620 2621 temp = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2622 if (temp & GINTSTS_RXFLVL) { 2623 /* pop current status */ 2624 sc->sc_last_rx_status = 2625 DWC_OTG_READ_4(sc, DOTG_GRXSTSPD); 2626 } 2627 2628 if (sc->sc_last_rx_status != 0) { 2629 2630 uint8_t ep_no; 2631 2632 temp = sc->sc_last_rx_status & 2633 GRXSTSRD_PKTSTS_MASK; 2634 2635 /* non-data messages we simply skip */ 2636 if (temp != GRXSTSRD_STP_DATA && 2637 temp != GRXSTSRD_OUT_DATA) { 2638 dwc_otg_common_rx_ack(sc); 2639 goto repeat; 2640 } 2641 2642 temp = GRXSTSRD_BCNT_GET( 2643 sc->sc_last_rx_status); 2644 ep_no = GRXSTSRD_CHNUM_GET( 2645 sc->sc_last_rx_status); 2646 2647 /* receive data, if any */ 2648 if (temp != 0) { 2649 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 2650 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 2651 DOTG_DFIFO(ep_no), 2652 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 2653 } 2654 2655 /* check if we should dump the data */ 2656 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2657 dwc_otg_common_rx_ack(sc); 2658 goto repeat; 2659 } 2660 2661 got_rx_status = 1; 2662 2663 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 2664 sc->sc_last_rx_status, ep_no, 2665 (sc->sc_last_rx_status >> 15) & 3, 2666 GRXSTSRD_BCNT_GET(sc->sc_last_rx_status), 2667 (sc->sc_last_rx_status >> 17) & 15); 2668 } else { 2669 got_rx_status = 0; 2670 } 2671 } else { 2672 uint8_t ep_no; 2673 2674 ep_no = GRXSTSRD_CHNUM_GET( 2675 sc->sc_last_rx_status); 2676 2677 /* check if we should dump the data */ 2678 if (!(sc->sc_active_rx_ep & (1U << ep_no))) { 2679 dwc_otg_common_rx_ack(sc); 2680 goto repeat; 2681 } 2682 2683 got_rx_status = 1; 2684 } 2685 2686 /* execute FIFOs */ 2687 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) 2688 dwc_otg_xfer_do_fifo(sc, xfer); 2689 2690 if (got_rx_status) { 2691 /* check if data was consumed */ 2692 if (sc->sc_last_rx_status == 0) 2693 goto repeat; 2694 2695 /* disable RX FIFO level interrupt */ 2696 sc->sc_irq_mask &= ~GINTMSK_RXFLVLMSK; 2697 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2698 } 2699 2700 if (sc->sc_flags.status_device_mode == 0 && sc->sc_xfer_complete == 0) { 2701 /* update host transfer schedule, so that new transfers can be issued */ 2702 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2703 goto repeat; 2704 } 2705 } 2706 2707 static void 2708 dwc_otg_interrupt_complete_locked(struct dwc_otg_softc *sc) 2709 { 2710 struct usb_xfer *xfer; 2711 repeat: 2712 /* scan for completion events */ 2713 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 2714 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 2715 goto repeat; 2716 } 2717 } 2718 2719 static void 2720 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 2721 { 2722 DPRINTFN(5, "vbus = %u\n", is_on); 2723 2724 /* 2725 * If the USB host mode is forced, then assume VBUS is always 2726 * present else rely on the input to this function: 2727 */ 2728 if ((is_on != 0) || (sc->sc_mode == DWC_MODE_HOST)) { 2729 2730 if (!sc->sc_flags.status_vbus) { 2731 sc->sc_flags.status_vbus = 1; 2732 2733 /* complete root HUB interrupt endpoint */ 2734 2735 dwc_otg_root_intr(sc); 2736 } 2737 } else { 2738 if (sc->sc_flags.status_vbus) { 2739 sc->sc_flags.status_vbus = 0; 2740 sc->sc_flags.status_bus_reset = 0; 2741 sc->sc_flags.status_suspend = 0; 2742 sc->sc_flags.change_suspend = 0; 2743 sc->sc_flags.change_connect = 1; 2744 2745 /* complete root HUB interrupt endpoint */ 2746 2747 dwc_otg_root_intr(sc); 2748 } 2749 } 2750 } 2751 2752 int 2753 dwc_otg_filter_interrupt(void *arg) 2754 { 2755 struct dwc_otg_softc *sc = arg; 2756 int retval = FILTER_HANDLED; 2757 uint32_t status; 2758 2759 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2760 2761 /* read and clear interrupt status */ 2762 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2763 2764 /* clear interrupts we are handling here */ 2765 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & ~DWC_OTG_MSK_GINT_THREAD_IRQ); 2766 2767 /* check for USB state change interrupts */ 2768 if ((status & DWC_OTG_MSK_GINT_THREAD_IRQ) != 0) 2769 retval = FILTER_SCHEDULE_THREAD; 2770 2771 /* clear all IN endpoint interrupts */ 2772 if (status & GINTSTS_IEPINT) { 2773 uint32_t temp; 2774 uint8_t x; 2775 2776 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 2777 temp = DWC_OTG_READ_4(sc, DOTG_DIEPINT(x)); 2778 if (temp & DIEPMSK_XFERCOMPLMSK) { 2779 DWC_OTG_WRITE_4(sc, DOTG_DIEPINT(x), 2780 DIEPMSK_XFERCOMPLMSK); 2781 } 2782 } 2783 } 2784 2785 /* poll FIFOs, if any */ 2786 dwc_otg_interrupt_poll_locked(sc); 2787 2788 if (sc->sc_xfer_complete != 0) 2789 retval = FILTER_SCHEDULE_THREAD; 2790 2791 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2792 2793 return (retval); 2794 } 2795 2796 void 2797 dwc_otg_interrupt(void *arg) 2798 { 2799 struct dwc_otg_softc *sc = arg; 2800 uint32_t status; 2801 2802 USB_BUS_LOCK(&sc->sc_bus); 2803 USB_BUS_SPIN_LOCK(&sc->sc_bus); 2804 2805 /* read and clear interrupt status */ 2806 status = DWC_OTG_READ_4(sc, DOTG_GINTSTS); 2807 2808 /* clear interrupts we are handling here */ 2809 DWC_OTG_WRITE_4(sc, DOTG_GINTSTS, status & DWC_OTG_MSK_GINT_THREAD_IRQ); 2810 2811 DPRINTFN(14, "GINTSTS=0x%08x HAINT=0x%08x HFNUM=0x%08x\n", 2812 status, DWC_OTG_READ_4(sc, DOTG_HAINT), 2813 DWC_OTG_READ_4(sc, DOTG_HFNUM)); 2814 2815 if (status & GINTSTS_USBRST) { 2816 2817 /* set correct state */ 2818 sc->sc_flags.status_device_mode = 1; 2819 sc->sc_flags.status_bus_reset = 0; 2820 sc->sc_flags.status_suspend = 0; 2821 sc->sc_flags.change_suspend = 0; 2822 sc->sc_flags.change_connect = 1; 2823 2824 /* Disable SOF interrupt */ 2825 sc->sc_irq_mask &= ~GINTMSK_SOFMSK; 2826 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2827 2828 /* complete root HUB interrupt endpoint */ 2829 dwc_otg_root_intr(sc); 2830 } 2831 2832 /* check for any bus state change interrupts */ 2833 if (status & GINTSTS_ENUMDONE) { 2834 2835 uint32_t temp; 2836 2837 DPRINTFN(5, "end of reset\n"); 2838 2839 /* set correct state */ 2840 sc->sc_flags.status_device_mode = 1; 2841 sc->sc_flags.status_bus_reset = 1; 2842 sc->sc_flags.status_suspend = 0; 2843 sc->sc_flags.change_suspend = 0; 2844 sc->sc_flags.change_connect = 1; 2845 sc->sc_flags.status_low_speed = 0; 2846 sc->sc_flags.port_enabled = 1; 2847 2848 /* reset FIFOs */ 2849 (void) dwc_otg_init_fifo(sc, DWC_MODE_DEVICE); 2850 2851 /* reset function address */ 2852 dwc_otg_set_address(sc, 0); 2853 2854 /* figure out enumeration speed */ 2855 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 2856 if (DSTS_ENUMSPD_GET(temp) == DSTS_ENUMSPD_HI) 2857 sc->sc_flags.status_high_speed = 1; 2858 else 2859 sc->sc_flags.status_high_speed = 0; 2860 2861 /* 2862 * Disable resume and SOF interrupt, and enable 2863 * suspend and RX frame interrupt: 2864 */ 2865 sc->sc_irq_mask &= ~(GINTMSK_WKUPINTMSK | GINTMSK_SOFMSK); 2866 sc->sc_irq_mask |= GINTMSK_USBSUSPMSK; 2867 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 2868 2869 /* complete root HUB interrupt endpoint */ 2870 dwc_otg_root_intr(sc); 2871 } 2872 2873 if (status & GINTSTS_PRTINT) { 2874 uint32_t hprt; 2875 2876 hprt = DWC_OTG_READ_4(sc, DOTG_HPRT); 2877 2878 /* clear change bits */ 2879 DWC_OTG_WRITE_4(sc, DOTG_HPRT, (hprt & ( 2880 HPRT_PRTPWR | HPRT_PRTENCHNG | 2881 HPRT_PRTCONNDET | HPRT_PRTOVRCURRCHNG)) | 2882 sc->sc_hprt_val); 2883 2884 DPRINTFN(12, "GINTSTS=0x%08x, HPRT=0x%08x\n", status, hprt); 2885 2886 sc->sc_flags.status_device_mode = 0; 2887 2888 if (hprt & HPRT_PRTCONNSTS) 2889 sc->sc_flags.status_bus_reset = 1; 2890 else 2891 sc->sc_flags.status_bus_reset = 0; 2892 2893 if (hprt & HPRT_PRTENCHNG) 2894 sc->sc_flags.change_enabled = 1; 2895 2896 if (hprt & HPRT_PRTENA) 2897 sc->sc_flags.port_enabled = 1; 2898 else 2899 sc->sc_flags.port_enabled = 0; 2900 2901 if (hprt & HPRT_PRTOVRCURRCHNG) 2902 sc->sc_flags.change_over_current = 1; 2903 2904 if (hprt & HPRT_PRTOVRCURRACT) 2905 sc->sc_flags.port_over_current = 1; 2906 else 2907 sc->sc_flags.port_over_current = 0; 2908 2909 if (hprt & HPRT_PRTPWR) 2910 sc->sc_flags.port_powered = 1; 2911 else 2912 sc->sc_flags.port_powered = 0; 2913 2914 if (((hprt & HPRT_PRTSPD_MASK) 2915 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_LOW) 2916 sc->sc_flags.status_low_speed = 1; 2917 else 2918 sc->sc_flags.status_low_speed = 0; 2919 2920 if (((hprt & HPRT_PRTSPD_MASK) 2921 >> HPRT_PRTSPD_SHIFT) == HPRT_PRTSPD_HIGH) 2922 sc->sc_flags.status_high_speed = 1; 2923 else 2924 sc->sc_flags.status_high_speed = 0; 2925 2926 if (hprt & HPRT_PRTCONNDET) 2927 sc->sc_flags.change_connect = 1; 2928 2929 if (hprt & HPRT_PRTSUSP) 2930 dwc_otg_suspend_irq(sc); 2931 else 2932 dwc_otg_resume_irq(sc); 2933 2934 /* complete root HUB interrupt endpoint */ 2935 dwc_otg_root_intr(sc); 2936 2937 /* update host frame interval */ 2938 dwc_otg_update_host_frame_interval(sc); 2939 } 2940 2941 /* 2942 * If resume and suspend is set at the same time we interpret 2943 * that like RESUME. Resume is set when there is at least 3 2944 * milliseconds of inactivity on the USB BUS. 2945 */ 2946 if (status & GINTSTS_WKUPINT) { 2947 2948 DPRINTFN(5, "resume interrupt\n"); 2949 2950 dwc_otg_resume_irq(sc); 2951 2952 } else if (status & GINTSTS_USBSUSP) { 2953 2954 DPRINTFN(5, "suspend interrupt\n"); 2955 2956 dwc_otg_suspend_irq(sc); 2957 } 2958 /* check VBUS */ 2959 if (status & (GINTSTS_USBSUSP | 2960 GINTSTS_USBRST | 2961 GINTMSK_OTGINTMSK | 2962 GINTSTS_SESSREQINT)) { 2963 uint32_t temp; 2964 2965 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 2966 2967 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 2968 2969 dwc_otg_vbus_interrupt(sc, 2970 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 2971 } 2972 2973 if (sc->sc_xfer_complete != 0) { 2974 sc->sc_xfer_complete = 0; 2975 2976 /* complete FIFOs, if any */ 2977 dwc_otg_interrupt_complete_locked(sc); 2978 2979 if (sc->sc_flags.status_device_mode == 0) { 2980 /* update host transfer schedule, so that new transfers can be issued */ 2981 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 2982 dwc_otg_interrupt_poll_locked(sc); 2983 } 2984 } 2985 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 2986 USB_BUS_UNLOCK(&sc->sc_bus); 2987 } 2988 2989 static void 2990 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 2991 { 2992 struct dwc_otg_td *td; 2993 2994 /* get current Transfer Descriptor */ 2995 td = temp->td_next; 2996 temp->td = td; 2997 2998 /* prepare for next TD */ 2999 temp->td_next = td->obj_next; 3000 3001 /* fill out the Transfer Descriptor */ 3002 td->func = temp->func; 3003 td->pc = temp->pc; 3004 td->offset = temp->offset; 3005 td->remainder = temp->len; 3006 td->tx_bytes = 0; 3007 td->error_any = 0; 3008 td->error_stall = 0; 3009 td->npkt = 0; 3010 td->did_stall = temp->did_stall; 3011 td->short_pkt = temp->short_pkt; 3012 td->alt_next = temp->setup_alt_next; 3013 td->set_toggle = 0; 3014 td->got_short = 0; 3015 td->did_nak = 0; 3016 td->channel = DWC_OTG_MAX_CHANNELS; 3017 td->state = 0; 3018 td->errcnt = 0; 3019 td->tt_scheduled = 0; 3020 td->tt_xactpos = HCSPLT_XACTPOS_BEGIN; 3021 } 3022 3023 static void 3024 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 3025 { 3026 struct dwc_otg_std_temp temp; 3027 struct dwc_otg_td *td; 3028 uint32_t x; 3029 uint8_t need_sync; 3030 uint8_t is_host; 3031 3032 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 3033 xfer->address, UE_GET_ADDR(xfer->endpointno), 3034 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 3035 3036 temp.max_frame_size = xfer->max_frame_size; 3037 3038 td = xfer->td_start[0]; 3039 xfer->td_transfer_first = td; 3040 xfer->td_transfer_cache = td; 3041 3042 /* setup temp */ 3043 3044 temp.pc = NULL; 3045 temp.td = NULL; 3046 temp.td_next = xfer->td_start[0]; 3047 temp.offset = 0; 3048 temp.setup_alt_next = xfer->flags_int.short_frames_ok || 3049 xfer->flags_int.isochronous_xfr; 3050 temp.did_stall = !xfer->flags_int.control_stall; 3051 3052 is_host = (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST); 3053 3054 /* check if we should prepend a setup message */ 3055 3056 if (xfer->flags_int.control_xfr) { 3057 if (xfer->flags_int.control_hdr) { 3058 3059 if (is_host) 3060 temp.func = &dwc_otg_host_setup_tx; 3061 else 3062 temp.func = &dwc_otg_setup_rx; 3063 3064 temp.len = xfer->frlengths[0]; 3065 temp.pc = xfer->frbuffers + 0; 3066 temp.short_pkt = temp.len ? 1 : 0; 3067 3068 /* check for last frame */ 3069 if (xfer->nframes == 1) { 3070 /* no STATUS stage yet, SETUP is last */ 3071 if (xfer->flags_int.control_act) 3072 temp.setup_alt_next = 0; 3073 } 3074 3075 dwc_otg_setup_standard_chain_sub(&temp); 3076 } 3077 x = 1; 3078 } else { 3079 x = 0; 3080 } 3081 3082 if (x != xfer->nframes) { 3083 if (xfer->endpointno & UE_DIR_IN) { 3084 if (is_host) { 3085 temp.func = &dwc_otg_host_data_rx; 3086 need_sync = 0; 3087 } else { 3088 temp.func = &dwc_otg_data_tx; 3089 need_sync = 1; 3090 } 3091 } else { 3092 if (is_host) { 3093 temp.func = &dwc_otg_host_data_tx; 3094 need_sync = 0; 3095 } else { 3096 temp.func = &dwc_otg_data_rx; 3097 need_sync = 0; 3098 } 3099 } 3100 3101 /* setup "pc" pointer */ 3102 temp.pc = xfer->frbuffers + x; 3103 } else { 3104 need_sync = 0; 3105 } 3106 while (x != xfer->nframes) { 3107 3108 /* DATA0 / DATA1 message */ 3109 3110 temp.len = xfer->frlengths[x]; 3111 3112 x++; 3113 3114 if (x == xfer->nframes) { 3115 if (xfer->flags_int.control_xfr) { 3116 if (xfer->flags_int.control_act) { 3117 temp.setup_alt_next = 0; 3118 } 3119 } else { 3120 temp.setup_alt_next = 0; 3121 } 3122 } 3123 if (temp.len == 0) { 3124 3125 /* make sure that we send an USB packet */ 3126 3127 temp.short_pkt = 0; 3128 3129 } else { 3130 3131 /* regular data transfer */ 3132 3133 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 3134 } 3135 3136 dwc_otg_setup_standard_chain_sub(&temp); 3137 3138 if (xfer->flags_int.isochronous_xfr) { 3139 temp.offset += temp.len; 3140 } else { 3141 /* get next Page Cache pointer */ 3142 temp.pc = xfer->frbuffers + x; 3143 } 3144 } 3145 3146 if (xfer->flags_int.control_xfr) { 3147 3148 /* always setup a valid "pc" pointer for status and sync */ 3149 temp.pc = xfer->frbuffers + 0; 3150 temp.len = 0; 3151 temp.short_pkt = 0; 3152 temp.setup_alt_next = 0; 3153 3154 /* check if we need to sync */ 3155 if (need_sync) { 3156 /* we need a SYNC point after TX */ 3157 temp.func = &dwc_otg_data_tx_sync; 3158 dwc_otg_setup_standard_chain_sub(&temp); 3159 } 3160 3161 /* check if we should append a status stage */ 3162 if (!xfer->flags_int.control_act) { 3163 3164 /* 3165 * Send a DATA1 message and invert the current 3166 * endpoint direction. 3167 */ 3168 if (xfer->endpointno & UE_DIR_IN) { 3169 if (is_host) { 3170 temp.func = &dwc_otg_host_data_tx; 3171 need_sync = 0; 3172 } else { 3173 temp.func = &dwc_otg_data_rx; 3174 need_sync = 0; 3175 } 3176 } else { 3177 if (is_host) { 3178 temp.func = &dwc_otg_host_data_rx; 3179 need_sync = 0; 3180 } else { 3181 temp.func = &dwc_otg_data_tx; 3182 need_sync = 1; 3183 } 3184 } 3185 3186 dwc_otg_setup_standard_chain_sub(&temp); 3187 3188 /* data toggle should be DATA1 */ 3189 td = temp.td; 3190 td->set_toggle = 1; 3191 3192 if (need_sync) { 3193 /* we need a SYNC point after TX */ 3194 temp.func = &dwc_otg_data_tx_sync; 3195 dwc_otg_setup_standard_chain_sub(&temp); 3196 } 3197 } 3198 } else { 3199 /* check if we need to sync */ 3200 if (need_sync) { 3201 3202 temp.pc = xfer->frbuffers + 0; 3203 temp.len = 0; 3204 temp.short_pkt = 0; 3205 temp.setup_alt_next = 0; 3206 3207 /* we need a SYNC point after TX */ 3208 temp.func = &dwc_otg_data_tx_sync; 3209 dwc_otg_setup_standard_chain_sub(&temp); 3210 } 3211 } 3212 3213 /* must have at least one frame! */ 3214 td = temp.td; 3215 xfer->td_transfer_last = td; 3216 3217 if (is_host) { 3218 3219 struct dwc_otg_softc *sc; 3220 uint32_t hcchar; 3221 uint32_t hcsplt; 3222 3223 sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3224 3225 /* get first again */ 3226 td = xfer->td_transfer_first; 3227 td->toggle = (xfer->endpoint->toggle_next ? 1 : 0); 3228 3229 hcchar = 3230 (xfer->address << HCCHAR_DEVADDR_SHIFT) | 3231 ((xfer->endpointno & UE_ADDR) << HCCHAR_EPNUM_SHIFT) | 3232 (xfer->max_packet_size << HCCHAR_MPS_SHIFT) | 3233 HCCHAR_CHENA; 3234 3235 /* 3236 * We are not always able to meet the timing 3237 * requirements of the USB interrupt endpoint's 3238 * complete split token, when doing transfers going 3239 * via a transaction translator. Use the CONTROL 3240 * transfer type instead of the INTERRUPT transfer 3241 * type in general, as a means to workaround 3242 * that. This trick should work for both FULL and LOW 3243 * speed USB traffic going through a TT. For non-TT 3244 * traffic it works aswell. The reason for using 3245 * CONTROL type instead of BULK is that some TTs might 3246 * reject LOW speed BULK traffic. 3247 */ 3248 if (td->ep_type == UE_INTERRUPT) 3249 hcchar |= (UE_CONTROL << HCCHAR_EPTYPE_SHIFT); 3250 else 3251 hcchar |= (td->ep_type << HCCHAR_EPTYPE_SHIFT); 3252 3253 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_LOW) 3254 hcchar |= HCCHAR_LSPDDEV; 3255 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) 3256 hcchar |= HCCHAR_EPDIR_IN; 3257 3258 switch (xfer->xroot->udev->speed) { 3259 case USB_SPEED_FULL: 3260 case USB_SPEED_LOW: 3261 /* check if root HUB port is running High Speed */ 3262 if (xfer->xroot->udev->parent_hs_hub != NULL) { 3263 hcsplt = HCSPLT_SPLTENA | 3264 (xfer->xroot->udev->hs_port_no << 3265 HCSPLT_PRTADDR_SHIFT) | 3266 (xfer->xroot->udev->hs_hub_addr << 3267 HCSPLT_HUBADDR_SHIFT); 3268 } else { 3269 hcsplt = 0; 3270 } 3271 if (td->ep_type == UE_INTERRUPT) { 3272 uint32_t ival; 3273 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3274 if (ival == 0) 3275 ival = 1; 3276 else if (ival > 127) 3277 ival = 127; 3278 td->tmr_val = sc->sc_tmr_val + ival; 3279 td->tmr_res = ival; 3280 } else if (td->ep_type == UE_ISOCHRONOUS) { 3281 td->tmr_val = 0; 3282 td->tmr_res = 1; 3283 } else { 3284 td->tmr_val = 0; 3285 td->tmr_res = 0; 3286 } 3287 break; 3288 case USB_SPEED_HIGH: 3289 hcsplt = 0; 3290 if (td->ep_type == UE_INTERRUPT) { 3291 uint32_t ival; 3292 #if 0 3293 hcchar |= ((xfer->max_packet_count & 3) 3294 << HCCHAR_MC_SHIFT); 3295 #endif 3296 ival = xfer->interval / DWC_OTG_HOST_TIMER_RATE; 3297 if (ival == 0) 3298 ival = 1; 3299 else if (ival > 127) 3300 ival = 127; 3301 td->tmr_val = sc->sc_tmr_val + ival; 3302 td->tmr_res = ival; 3303 } else if (td->ep_type == UE_ISOCHRONOUS) { 3304 hcchar |= ((xfer->max_packet_count & 3) 3305 << HCCHAR_MC_SHIFT); 3306 td->tmr_val = 0; 3307 td->tmr_res = 1 << usbd_xfer_get_fps_shift(xfer); 3308 } else { 3309 td->tmr_val = 0; 3310 td->tmr_res = 0; 3311 } 3312 break; 3313 default: 3314 hcsplt = 0; 3315 td->tmr_val = 0; 3316 td->tmr_res = 0; 3317 break; 3318 } 3319 3320 /* store configuration in all TD's */ 3321 while (1) { 3322 td->hcchar = hcchar; 3323 td->hcsplt = hcsplt; 3324 3325 if (((void *)td) == xfer->td_transfer_last) 3326 break; 3327 3328 td = td->obj_next; 3329 } 3330 } 3331 } 3332 3333 static void 3334 dwc_otg_timeout(void *arg) 3335 { 3336 struct usb_xfer *xfer = arg; 3337 3338 DPRINTF("xfer=%p\n", xfer); 3339 3340 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 3341 3342 /* transfer is transferred */ 3343 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 3344 } 3345 3346 static void 3347 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 3348 { 3349 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3350 struct usb_xfer_root *xroot; 3351 struct dwc_otg_td *td; 3352 3353 DPRINTFN(9, "\n"); 3354 3355 /* 3356 * Poll one time in device mode, which will turn on the 3357 * endpoint interrupts. Else wait for SOF interrupt in host 3358 * mode. 3359 */ 3360 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3361 3362 if (sc->sc_flags.status_device_mode != 0) { 3363 dwc_otg_xfer_do_fifo(sc, xfer); 3364 if (dwc_otg_xfer_do_complete_locked(sc, xfer)) 3365 goto done; 3366 } 3367 3368 /* put transfer on interrupt queue */ 3369 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3370 3371 /* start timeout, if any */ 3372 if (xfer->timeout != 0) { 3373 usbd_transfer_timeout_ms(xfer, 3374 &dwc_otg_timeout, xfer->timeout); 3375 } 3376 3377 if (sc->sc_flags.status_device_mode != 0) 3378 goto done; 3379 3380 /* enable SOF interrupt, if any */ 3381 dwc_otg_enable_sof_irq(sc); 3382 3383 td = xfer->td_transfer_cache; 3384 if (td->ep_type != UE_BULK) 3385 goto done; 3386 3387 xroot = xfer->xroot; 3388 3389 /* 3390 * Optimise the ping-pong effect by waking up other BULK 3391 * transfers belonging to the same device group: 3392 */ 3393 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3394 td = xfer->td_transfer_cache; 3395 if (td == NULL || td->ep_type != UE_BULK || xfer->xroot != xroot) 3396 continue; 3397 /* reset NAK counter */ 3398 td->did_nak = 0; 3399 } 3400 done: 3401 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3402 } 3403 3404 static void 3405 dwc_otg_root_intr(struct dwc_otg_softc *sc) 3406 { 3407 DPRINTFN(9, "\n"); 3408 3409 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3410 3411 /* set port bit */ 3412 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 3413 3414 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3415 sizeof(sc->sc_hub_idata)); 3416 } 3417 3418 static usb_error_t 3419 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 3420 { 3421 struct dwc_otg_td *td; 3422 uint32_t len; 3423 usb_error_t error; 3424 3425 DPRINTFN(9, "\n"); 3426 3427 td = xfer->td_transfer_cache; 3428 3429 do { 3430 len = td->remainder; 3431 3432 /* store last data toggle */ 3433 xfer->endpoint->toggle_next = td->toggle; 3434 3435 if (xfer->aframes != xfer->nframes) { 3436 /* 3437 * Verify the length and subtract 3438 * the remainder from "frlengths[]": 3439 */ 3440 if (len > xfer->frlengths[xfer->aframes]) { 3441 td->error_any = 1; 3442 } else { 3443 xfer->frlengths[xfer->aframes] -= len; 3444 } 3445 } 3446 /* Check for transfer error */ 3447 if (td->error_any) { 3448 /* the transfer is finished */ 3449 error = (td->error_stall ? 3450 USB_ERR_STALLED : USB_ERR_IOERROR); 3451 td = NULL; 3452 break; 3453 } 3454 /* Check for short transfer */ 3455 if (len > 0) { 3456 if (xfer->flags_int.short_frames_ok || 3457 xfer->flags_int.isochronous_xfr) { 3458 /* follow alt next */ 3459 if (td->alt_next) { 3460 td = td->obj_next; 3461 } else { 3462 td = NULL; 3463 } 3464 } else { 3465 /* the transfer is finished */ 3466 td = NULL; 3467 } 3468 error = 0; 3469 break; 3470 } 3471 td = td->obj_next; 3472 3473 /* this USB frame is complete */ 3474 error = 0; 3475 break; 3476 3477 } while (0); 3478 3479 /* update transfer cache */ 3480 3481 xfer->td_transfer_cache = td; 3482 3483 return (error); 3484 } 3485 3486 static void 3487 dwc_otg_standard_done(struct usb_xfer *xfer) 3488 { 3489 usb_error_t err = 0; 3490 3491 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 3492 xfer, xfer->endpoint); 3493 3494 /* reset scanner */ 3495 3496 xfer->td_transfer_cache = xfer->td_transfer_first; 3497 3498 if (xfer->flags_int.control_xfr) { 3499 3500 if (xfer->flags_int.control_hdr) { 3501 3502 err = dwc_otg_standard_done_sub(xfer); 3503 } 3504 xfer->aframes = 1; 3505 3506 if (xfer->td_transfer_cache == NULL) { 3507 goto done; 3508 } 3509 } 3510 while (xfer->aframes != xfer->nframes) { 3511 3512 err = dwc_otg_standard_done_sub(xfer); 3513 xfer->aframes++; 3514 3515 if (xfer->td_transfer_cache == NULL) { 3516 goto done; 3517 } 3518 } 3519 3520 if (xfer->flags_int.control_xfr && 3521 !xfer->flags_int.control_act) { 3522 3523 err = dwc_otg_standard_done_sub(xfer); 3524 } 3525 done: 3526 dwc_otg_device_done(xfer, err); 3527 } 3528 3529 /*------------------------------------------------------------------------* 3530 * dwc_otg_device_done 3531 * 3532 * NOTE: this function can be called more than one time on the 3533 * same USB transfer! 3534 *------------------------------------------------------------------------*/ 3535 static void 3536 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 3537 { 3538 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 3539 3540 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 3541 xfer, xfer->endpoint, error); 3542 3543 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3544 3545 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 3546 /* Interrupts are cleared by the interrupt handler */ 3547 } else { 3548 struct dwc_otg_td *td; 3549 3550 td = xfer->td_transfer_cache; 3551 if (td != NULL) 3552 dwc_otg_host_channel_free(sc, td); 3553 } 3554 /* dequeue transfer and start next transfer */ 3555 usbd_transfer_done(xfer, error); 3556 3557 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3558 } 3559 3560 static void 3561 dwc_otg_xfer_stall(struct usb_xfer *xfer) 3562 { 3563 dwc_otg_device_done(xfer, USB_ERR_STALLED); 3564 } 3565 3566 static void 3567 dwc_otg_set_stall(struct usb_device *udev, 3568 struct usb_endpoint *ep, uint8_t *did_stall) 3569 { 3570 struct dwc_otg_softc *sc; 3571 uint32_t temp; 3572 uint32_t reg; 3573 uint8_t ep_no; 3574 3575 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3576 3577 /* check mode */ 3578 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3579 /* not supported */ 3580 return; 3581 } 3582 3583 sc = DWC_OTG_BUS2SC(udev->bus); 3584 3585 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3586 3587 /* get endpoint address */ 3588 ep_no = ep->edesc->bEndpointAddress; 3589 3590 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 3591 3592 if (ep_no & UE_DIR_IN) { 3593 reg = DOTG_DIEPCTL(ep_no & UE_ADDR); 3594 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 3595 } else { 3596 reg = DOTG_DOEPCTL(ep_no & UE_ADDR); 3597 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 3598 } 3599 3600 /* disable and stall endpoint */ 3601 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3602 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_STALL); 3603 3604 /* clear active OUT ep */ 3605 if (!(ep_no & UE_DIR_IN)) { 3606 3607 sc->sc_active_rx_ep &= ~(1U << (ep_no & UE_ADDR)); 3608 3609 if (sc->sc_last_rx_status != 0 && 3610 (ep_no & UE_ADDR) == GRXSTSRD_CHNUM_GET( 3611 sc->sc_last_rx_status)) { 3612 /* dump data */ 3613 dwc_otg_common_rx_ack(sc); 3614 /* poll interrupt */ 3615 dwc_otg_interrupt_poll_locked(sc); 3616 dwc_otg_interrupt_complete_locked(sc); 3617 } 3618 } 3619 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3620 } 3621 3622 static void 3623 dwc_otg_clear_stall_sub_locked(struct dwc_otg_softc *sc, uint32_t mps, 3624 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 3625 { 3626 uint32_t reg; 3627 uint32_t temp; 3628 3629 if (ep_type == UE_CONTROL) { 3630 /* clearing stall is not needed */ 3631 return; 3632 } 3633 3634 if (ep_dir) { 3635 reg = DOTG_DIEPCTL(ep_no); 3636 } else { 3637 reg = DOTG_DOEPCTL(ep_no); 3638 sc->sc_active_rx_ep |= (1U << ep_no); 3639 } 3640 3641 /* round up and mask away the multiplier count */ 3642 mps = (mps + 3) & 0x7FC; 3643 3644 if (ep_type == UE_BULK) { 3645 temp = DIEPCTL_EPTYPE_SET( 3646 DIEPCTL_EPTYPE_BULK) | 3647 DIEPCTL_USBACTEP; 3648 } else if (ep_type == UE_INTERRUPT) { 3649 temp = DIEPCTL_EPTYPE_SET( 3650 DIEPCTL_EPTYPE_INTERRUPT) | 3651 DIEPCTL_USBACTEP; 3652 } else { 3653 temp = DIEPCTL_EPTYPE_SET( 3654 DIEPCTL_EPTYPE_ISOC) | 3655 DIEPCTL_USBACTEP; 3656 } 3657 3658 temp |= DIEPCTL_MPS_SET(mps); 3659 temp |= DIEPCTL_TXFNUM_SET(ep_no); 3660 3661 if (ep_dir) 3662 sc->sc_in_ctl[ep_no] = temp; 3663 else 3664 sc->sc_out_ctl[ep_no] = temp; 3665 3666 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_EPDIS); 3667 DWC_OTG_WRITE_4(sc, reg, temp | DOEPCTL_SETD0PID); 3668 DWC_OTG_WRITE_4(sc, reg, temp | DIEPCTL_SNAK); 3669 3670 /* we only reset the transmit FIFO */ 3671 if (ep_dir) { 3672 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3673 GRSTCTL_TXFIFO(ep_no) | 3674 GRSTCTL_TXFFLSH); 3675 3676 DWC_OTG_WRITE_4(sc, 3677 DOTG_DIEPTSIZ(ep_no), 0); 3678 } 3679 3680 /* poll interrupt */ 3681 dwc_otg_interrupt_poll_locked(sc); 3682 dwc_otg_interrupt_complete_locked(sc); 3683 } 3684 3685 static void 3686 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3687 { 3688 struct dwc_otg_softc *sc; 3689 struct usb_endpoint_descriptor *ed; 3690 3691 DPRINTFN(5, "endpoint=%p\n", ep); 3692 3693 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 3694 3695 /* check mode */ 3696 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3697 /* not supported */ 3698 return; 3699 } 3700 /* get softc */ 3701 sc = DWC_OTG_BUS2SC(udev->bus); 3702 3703 USB_BUS_SPIN_LOCK(&sc->sc_bus); 3704 3705 /* get endpoint descriptor */ 3706 ed = ep->edesc; 3707 3708 /* reset endpoint */ 3709 dwc_otg_clear_stall_sub_locked(sc, 3710 UGETW(ed->wMaxPacketSize), 3711 (ed->bEndpointAddress & UE_ADDR), 3712 (ed->bmAttributes & UE_XFERTYPE), 3713 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 3714 3715 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 3716 } 3717 3718 static void 3719 dwc_otg_device_state_change(struct usb_device *udev) 3720 { 3721 struct dwc_otg_softc *sc; 3722 uint8_t x; 3723 3724 /* check mode */ 3725 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 3726 /* not supported */ 3727 return; 3728 } 3729 3730 /* get softc */ 3731 sc = DWC_OTG_BUS2SC(udev->bus); 3732 3733 /* deactivate all other endpoint but the control endpoint */ 3734 if (udev->state == USB_STATE_CONFIGURED || 3735 udev->state == USB_STATE_ADDRESSED) { 3736 3737 USB_BUS_LOCK(&sc->sc_bus); 3738 3739 for (x = 1; x != sc->sc_dev_ep_max; x++) { 3740 3741 if (x < sc->sc_dev_in_ep_max) { 3742 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 3743 DIEPCTL_EPDIS); 3744 DWC_OTG_WRITE_4(sc, DOTG_DIEPCTL(x), 0); 3745 } 3746 3747 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 3748 DOEPCTL_EPDIS); 3749 DWC_OTG_WRITE_4(sc, DOTG_DOEPCTL(x), 0); 3750 } 3751 USB_BUS_UNLOCK(&sc->sc_bus); 3752 } 3753 } 3754 3755 int 3756 dwc_otg_init(struct dwc_otg_softc *sc) 3757 { 3758 uint32_t temp; 3759 3760 DPRINTF("start\n"); 3761 3762 /* set up the bus structure */ 3763 sc->sc_bus.usbrev = USB_REV_2_0; 3764 sc->sc_bus.methods = &dwc_otg_bus_methods; 3765 3766 usb_callout_init_mtx(&sc->sc_timer, 3767 &sc->sc_bus.bus_mtx, 0); 3768 3769 USB_BUS_LOCK(&sc->sc_bus); 3770 3771 /* turn on clocks */ 3772 dwc_otg_clocks_on(sc); 3773 3774 temp = DWC_OTG_READ_4(sc, DOTG_GSNPSID); 3775 DPRINTF("Version = 0x%08x\n", temp); 3776 3777 /* disconnect */ 3778 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3779 DCTL_SFTDISCON); 3780 3781 /* wait for host to detect disconnect */ 3782 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 3783 3784 DWC_OTG_WRITE_4(sc, DOTG_GRSTCTL, 3785 GRSTCTL_CSFTRST); 3786 3787 /* wait a little bit for block to reset */ 3788 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 3789 3790 switch (sc->sc_mode) { 3791 case DWC_MODE_DEVICE: 3792 temp = GUSBCFG_FORCEDEVMODE; 3793 break; 3794 case DWC_MODE_HOST: 3795 temp = GUSBCFG_FORCEHOSTMODE; 3796 break; 3797 default: 3798 temp = 0; 3799 break; 3800 } 3801 3802 /* select HSIC, ULPI or internal PHY mode */ 3803 switch (dwc_otg_phy_type) { 3804 case DWC_OTG_PHY_HSIC: 3805 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3806 GUSBCFG_PHYIF | 3807 GUSBCFG_TRD_TIM_SET(5) | temp); 3808 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 3809 0x000000EC); 3810 3811 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3812 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3813 temp & ~GLPMCFG_HSIC_CONN); 3814 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3815 temp | GLPMCFG_HSIC_CONN); 3816 break; 3817 case DWC_OTG_PHY_ULPI: 3818 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3819 GUSBCFG_ULPI_UTMI_SEL | 3820 GUSBCFG_TRD_TIM_SET(5) | temp); 3821 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3822 3823 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3824 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3825 temp & ~GLPMCFG_HSIC_CONN); 3826 break; 3827 case DWC_OTG_PHY_INTERNAL: 3828 DWC_OTG_WRITE_4(sc, DOTG_GUSBCFG, 3829 GUSBCFG_PHYSEL | 3830 GUSBCFG_TRD_TIM_SET(5) | temp); 3831 DWC_OTG_WRITE_4(sc, DOTG_GOTGCTL, 0); 3832 3833 temp = DWC_OTG_READ_4(sc, DOTG_GLPMCFG); 3834 DWC_OTG_WRITE_4(sc, DOTG_GLPMCFG, 3835 temp & ~GLPMCFG_HSIC_CONN); 3836 3837 temp = DWC_OTG_READ_4(sc, DOTG_GGPIO); 3838 temp &= ~(DOTG_GGPIO_NOVBUSSENS | DOTG_GGPIO_I2CPADEN); 3839 temp |= (DOTG_GGPIO_VBUSASEN | DOTG_GGPIO_VBUSBSEN | 3840 DOTG_GGPIO_PWRDWN); 3841 DWC_OTG_WRITE_4(sc, DOTG_GGPIO, temp); 3842 break; 3843 default: 3844 break; 3845 } 3846 3847 /* clear global nak */ 3848 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3849 DCTL_CGOUTNAK | 3850 DCTL_CGNPINNAK); 3851 3852 /* disable USB port */ 3853 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0xFFFFFFFF); 3854 3855 /* wait 10ms */ 3856 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3857 3858 /* enable USB port */ 3859 DWC_OTG_WRITE_4(sc, DOTG_PCGCCTL, 0); 3860 3861 /* wait 10ms */ 3862 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100); 3863 3864 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG3); 3865 3866 sc->sc_fifo_size = 4 * GHWCFG3_DFIFODEPTH_GET(temp); 3867 3868 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3869 3870 sc->sc_dev_ep_max = GHWCFG2_NUMDEVEPS_GET(temp); 3871 3872 if (sc->sc_dev_ep_max > DWC_OTG_MAX_ENDPOINTS) 3873 sc->sc_dev_ep_max = DWC_OTG_MAX_ENDPOINTS; 3874 3875 sc->sc_host_ch_max = GHWCFG2_NUMHSTCHNL_GET(temp); 3876 3877 if (sc->sc_host_ch_max > DWC_OTG_MAX_CHANNELS) 3878 sc->sc_host_ch_max = DWC_OTG_MAX_CHANNELS; 3879 3880 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG4); 3881 3882 sc->sc_dev_in_ep_max = GHWCFG4_NUM_IN_EP_GET(temp); 3883 3884 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d Host CHs = %d\n", 3885 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max, 3886 sc->sc_host_ch_max); 3887 3888 /* setup FIFO */ 3889 if (dwc_otg_init_fifo(sc, sc->sc_mode)) { 3890 USB_BUS_UNLOCK(&sc->sc_bus); 3891 return (EINVAL); 3892 } 3893 3894 /* enable interrupts */ 3895 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 3896 DWC_OTG_WRITE_4(sc, DOTG_GINTMSK, sc->sc_irq_mask); 3897 3898 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_DEVICE) { 3899 3900 /* enable all endpoint interrupts */ 3901 temp = DWC_OTG_READ_4(sc, DOTG_GHWCFG2); 3902 if (temp & GHWCFG2_MPI) { 3903 uint8_t x; 3904 3905 DPRINTF("Disable Multi Process Interrupts\n"); 3906 3907 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 3908 DWC_OTG_WRITE_4(sc, DOTG_DIEPEACHINTMSK(x), 0); 3909 DWC_OTG_WRITE_4(sc, DOTG_DOEPEACHINTMSK(x), 0); 3910 } 3911 DWC_OTG_WRITE_4(sc, DOTG_DEACHINTMSK, 0); 3912 } 3913 DWC_OTG_WRITE_4(sc, DOTG_DIEPMSK, 3914 DIEPMSK_XFERCOMPLMSK); 3915 DWC_OTG_WRITE_4(sc, DOTG_DOEPMSK, 0); 3916 DWC_OTG_WRITE_4(sc, DOTG_DAINTMSK, 0xFFFF); 3917 } 3918 3919 if (sc->sc_mode == DWC_MODE_OTG || sc->sc_mode == DWC_MODE_HOST) { 3920 /* setup clocks */ 3921 temp = DWC_OTG_READ_4(sc, DOTG_HCFG); 3922 temp &= ~(HCFG_FSLSSUPP | HCFG_FSLSPCLKSEL_MASK); 3923 temp |= (1 << HCFG_FSLSPCLKSEL_SHIFT); 3924 DWC_OTG_WRITE_4(sc, DOTG_HCFG, temp); 3925 } 3926 3927 /* only enable global IRQ */ 3928 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 3929 GAHBCFG_GLBLINTRMSK); 3930 3931 /* turn off clocks */ 3932 dwc_otg_clocks_off(sc); 3933 3934 /* read initial VBUS state */ 3935 3936 temp = DWC_OTG_READ_4(sc, DOTG_GOTGCTL); 3937 3938 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 3939 3940 dwc_otg_vbus_interrupt(sc, 3941 (temp & (GOTGCTL_ASESVLD | GOTGCTL_BSESVLD)) ? 1 : 0); 3942 3943 USB_BUS_UNLOCK(&sc->sc_bus); 3944 3945 /* catch any lost interrupts */ 3946 3947 dwc_otg_do_poll(&sc->sc_bus); 3948 3949 return (0); /* success */ 3950 } 3951 3952 void 3953 dwc_otg_uninit(struct dwc_otg_softc *sc) 3954 { 3955 USB_BUS_LOCK(&sc->sc_bus); 3956 3957 /* stop host timer */ 3958 dwc_otg_timer_stop(sc); 3959 3960 /* set disconnect */ 3961 DWC_OTG_WRITE_4(sc, DOTG_DCTL, 3962 DCTL_SFTDISCON); 3963 3964 /* turn off global IRQ */ 3965 DWC_OTG_WRITE_4(sc, DOTG_GAHBCFG, 0); 3966 3967 sc->sc_flags.port_enabled = 0; 3968 sc->sc_flags.port_powered = 0; 3969 sc->sc_flags.status_vbus = 0; 3970 sc->sc_flags.status_bus_reset = 0; 3971 sc->sc_flags.status_suspend = 0; 3972 sc->sc_flags.change_suspend = 0; 3973 sc->sc_flags.change_connect = 1; 3974 3975 dwc_otg_pull_down(sc); 3976 dwc_otg_clocks_off(sc); 3977 3978 USB_BUS_UNLOCK(&sc->sc_bus); 3979 3980 usb_callout_drain(&sc->sc_timer); 3981 } 3982 3983 static void 3984 dwc_otg_suspend(struct dwc_otg_softc *sc) 3985 { 3986 return; 3987 } 3988 3989 static void 3990 dwc_otg_resume(struct dwc_otg_softc *sc) 3991 { 3992 return; 3993 } 3994 3995 static void 3996 dwc_otg_do_poll(struct usb_bus *bus) 3997 { 3998 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 3999 4000 USB_BUS_LOCK(&sc->sc_bus); 4001 USB_BUS_SPIN_LOCK(&sc->sc_bus); 4002 dwc_otg_interrupt_poll_locked(sc); 4003 dwc_otg_interrupt_complete_locked(sc); 4004 if (sc->sc_flags.status_device_mode == 0) { 4005 /* update host transfer schedule, so that new transfers can be issued */ 4006 if (dwc_otg_update_host_transfer_schedule_locked(sc)) 4007 dwc_otg_interrupt_poll_locked(sc); 4008 } 4009 USB_BUS_SPIN_UNLOCK(&sc->sc_bus); 4010 USB_BUS_UNLOCK(&sc->sc_bus); 4011 } 4012 4013 /*------------------------------------------------------------------------* 4014 * DWC OTG bulk support 4015 * DWC OTG control support 4016 * DWC OTG interrupt support 4017 *------------------------------------------------------------------------*/ 4018 static void 4019 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 4020 { 4021 } 4022 4023 static void 4024 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 4025 { 4026 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4027 } 4028 4029 static void 4030 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 4031 { 4032 } 4033 4034 static void 4035 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 4036 { 4037 /* setup TDs */ 4038 dwc_otg_setup_standard_chain(xfer); 4039 dwc_otg_start_standard_chain(xfer); 4040 } 4041 4042 static const struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 4043 { 4044 .open = dwc_otg_device_non_isoc_open, 4045 .close = dwc_otg_device_non_isoc_close, 4046 .enter = dwc_otg_device_non_isoc_enter, 4047 .start = dwc_otg_device_non_isoc_start, 4048 }; 4049 4050 /*------------------------------------------------------------------------* 4051 * DWC OTG full speed isochronous support 4052 *------------------------------------------------------------------------*/ 4053 static void 4054 dwc_otg_device_isoc_open(struct usb_xfer *xfer) 4055 { 4056 } 4057 4058 static void 4059 dwc_otg_device_isoc_close(struct usb_xfer *xfer) 4060 { 4061 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 4062 } 4063 4064 static void 4065 dwc_otg_device_isoc_enter(struct usb_xfer *xfer) 4066 { 4067 } 4068 4069 static void 4070 dwc_otg_device_isoc_start(struct usb_xfer *xfer) 4071 { 4072 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 4073 uint32_t temp; 4074 uint32_t msframes; 4075 uint32_t framenum; 4076 uint8_t shift = usbd_xfer_get_fps_shift(xfer); 4077 4078 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 4079 xfer, xfer->endpoint->isoc_next, xfer->nframes); 4080 4081 if (xfer->xroot->udev->flags.usb_mode == USB_MODE_HOST) { 4082 temp = DWC_OTG_READ_4(sc, DOTG_HFNUM); 4083 4084 /* get the current frame index */ 4085 framenum = (temp & HFNUM_FRNUM_MASK); 4086 } else { 4087 temp = DWC_OTG_READ_4(sc, DOTG_DSTS); 4088 4089 /* get the current frame index */ 4090 framenum = DSTS_SOFFN_GET(temp); 4091 } 4092 4093 if (xfer->xroot->udev->parent_hs_hub != NULL) 4094 framenum /= 8; 4095 4096 framenum &= DWC_OTG_FRAME_MASK; 4097 4098 /* 4099 * Compute number of milliseconds worth of data traffic for 4100 * this USB transfer: 4101 */ 4102 if (xfer->xroot->udev->speed == USB_SPEED_HIGH) 4103 msframes = ((xfer->nframes << shift) + 7) / 8; 4104 else 4105 msframes = xfer->nframes; 4106 4107 /* 4108 * check if the frame index is within the window where the frames 4109 * will be inserted 4110 */ 4111 temp = (framenum - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 4112 4113 if ((xfer->endpoint->is_synced == 0) || (temp < msframes)) { 4114 /* 4115 * If there is data underflow or the pipe queue is 4116 * empty we schedule the transfer a few frames ahead 4117 * of the current frame position. Else two isochronous 4118 * transfers might overlap. 4119 */ 4120 xfer->endpoint->isoc_next = (framenum + 3) & DWC_OTG_FRAME_MASK; 4121 xfer->endpoint->is_synced = 1; 4122 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 4123 } 4124 /* 4125 * compute how many milliseconds the insertion is ahead of the 4126 * current frame position: 4127 */ 4128 temp = (xfer->endpoint->isoc_next - framenum) & DWC_OTG_FRAME_MASK; 4129 4130 /* 4131 * pre-compute when the isochronous transfer will be finished: 4132 */ 4133 xfer->isoc_time_complete = 4134 usb_isoc_time_expand(&sc->sc_bus, framenum) + temp + msframes; 4135 4136 /* setup TDs */ 4137 dwc_otg_setup_standard_chain(xfer); 4138 4139 /* compute frame number for next insertion */ 4140 xfer->endpoint->isoc_next += msframes; 4141 4142 /* start TD chain */ 4143 dwc_otg_start_standard_chain(xfer); 4144 } 4145 4146 static const struct usb_pipe_methods dwc_otg_device_isoc_methods = 4147 { 4148 .open = dwc_otg_device_isoc_open, 4149 .close = dwc_otg_device_isoc_close, 4150 .enter = dwc_otg_device_isoc_enter, 4151 .start = dwc_otg_device_isoc_start, 4152 }; 4153 4154 /*------------------------------------------------------------------------* 4155 * DWC OTG root control support 4156 *------------------------------------------------------------------------* 4157 * Simulate a hardware HUB by handling all the necessary requests. 4158 *------------------------------------------------------------------------*/ 4159 4160 static const struct usb_device_descriptor dwc_otg_devd = { 4161 .bLength = sizeof(struct usb_device_descriptor), 4162 .bDescriptorType = UDESC_DEVICE, 4163 .bcdUSB = {0x00, 0x02}, 4164 .bDeviceClass = UDCLASS_HUB, 4165 .bDeviceSubClass = UDSUBCLASS_HUB, 4166 .bDeviceProtocol = UDPROTO_HSHUBSTT, 4167 .bMaxPacketSize = 64, 4168 .bcdDevice = {0x00, 0x01}, 4169 .iManufacturer = 1, 4170 .iProduct = 2, 4171 .bNumConfigurations = 1, 4172 }; 4173 4174 static const struct dwc_otg_config_desc dwc_otg_confd = { 4175 .confd = { 4176 .bLength = sizeof(struct usb_config_descriptor), 4177 .bDescriptorType = UDESC_CONFIG, 4178 .wTotalLength[0] = sizeof(dwc_otg_confd), 4179 .bNumInterface = 1, 4180 .bConfigurationValue = 1, 4181 .iConfiguration = 0, 4182 .bmAttributes = UC_SELF_POWERED, 4183 .bMaxPower = 0, 4184 }, 4185 .ifcd = { 4186 .bLength = sizeof(struct usb_interface_descriptor), 4187 .bDescriptorType = UDESC_INTERFACE, 4188 .bNumEndpoints = 1, 4189 .bInterfaceClass = UICLASS_HUB, 4190 .bInterfaceSubClass = UISUBCLASS_HUB, 4191 .bInterfaceProtocol = 0, 4192 }, 4193 .endpd = { 4194 .bLength = sizeof(struct usb_endpoint_descriptor), 4195 .bDescriptorType = UDESC_ENDPOINT, 4196 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 4197 .bmAttributes = UE_INTERRUPT, 4198 .wMaxPacketSize[0] = 8, 4199 .bInterval = 255, 4200 }, 4201 }; 4202 4203 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 4204 4205 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 4206 .bDescLength = sizeof(dwc_otg_hubd), 4207 .bDescriptorType = UDESC_HUB, 4208 .bNbrPorts = 1, 4209 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 4210 .bPwrOn2PwrGood = 50, 4211 .bHubContrCurrent = 0, 4212 .DeviceRemovable = {0}, /* port is removable */ 4213 }; 4214 4215 #define STRING_VENDOR \ 4216 "D\0W\0C\0O\0T\0G" 4217 4218 #define STRING_PRODUCT \ 4219 "O\0T\0G\0 \0R\0o\0o\0t\0 \0H\0U\0B" 4220 4221 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 4222 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 4223 4224 static usb_error_t 4225 dwc_otg_roothub_exec(struct usb_device *udev, 4226 struct usb_device_request *req, const void **pptr, uint16_t *plength) 4227 { 4228 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4229 const void *ptr; 4230 uint16_t len; 4231 uint16_t value; 4232 uint16_t index; 4233 usb_error_t err; 4234 4235 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 4236 4237 /* buffer reset */ 4238 ptr = (const void *)&sc->sc_hub_temp; 4239 len = 0; 4240 err = 0; 4241 4242 value = UGETW(req->wValue); 4243 index = UGETW(req->wIndex); 4244 4245 /* demultiplex the control request */ 4246 4247 switch (req->bmRequestType) { 4248 case UT_READ_DEVICE: 4249 switch (req->bRequest) { 4250 case UR_GET_DESCRIPTOR: 4251 goto tr_handle_get_descriptor; 4252 case UR_GET_CONFIG: 4253 goto tr_handle_get_config; 4254 case UR_GET_STATUS: 4255 goto tr_handle_get_status; 4256 default: 4257 goto tr_stalled; 4258 } 4259 break; 4260 4261 case UT_WRITE_DEVICE: 4262 switch (req->bRequest) { 4263 case UR_SET_ADDRESS: 4264 goto tr_handle_set_address; 4265 case UR_SET_CONFIG: 4266 goto tr_handle_set_config; 4267 case UR_CLEAR_FEATURE: 4268 goto tr_valid; /* nop */ 4269 case UR_SET_DESCRIPTOR: 4270 goto tr_valid; /* nop */ 4271 case UR_SET_FEATURE: 4272 default: 4273 goto tr_stalled; 4274 } 4275 break; 4276 4277 case UT_WRITE_ENDPOINT: 4278 switch (req->bRequest) { 4279 case UR_CLEAR_FEATURE: 4280 switch (UGETW(req->wValue)) { 4281 case UF_ENDPOINT_HALT: 4282 goto tr_handle_clear_halt; 4283 case UF_DEVICE_REMOTE_WAKEUP: 4284 goto tr_handle_clear_wakeup; 4285 default: 4286 goto tr_stalled; 4287 } 4288 break; 4289 case UR_SET_FEATURE: 4290 switch (UGETW(req->wValue)) { 4291 case UF_ENDPOINT_HALT: 4292 goto tr_handle_set_halt; 4293 case UF_DEVICE_REMOTE_WAKEUP: 4294 goto tr_handle_set_wakeup; 4295 default: 4296 goto tr_stalled; 4297 } 4298 break; 4299 case UR_SYNCH_FRAME: 4300 goto tr_valid; /* nop */ 4301 default: 4302 goto tr_stalled; 4303 } 4304 break; 4305 4306 case UT_READ_ENDPOINT: 4307 switch (req->bRequest) { 4308 case UR_GET_STATUS: 4309 goto tr_handle_get_ep_status; 4310 default: 4311 goto tr_stalled; 4312 } 4313 break; 4314 4315 case UT_WRITE_INTERFACE: 4316 switch (req->bRequest) { 4317 case UR_SET_INTERFACE: 4318 goto tr_handle_set_interface; 4319 case UR_CLEAR_FEATURE: 4320 goto tr_valid; /* nop */ 4321 case UR_SET_FEATURE: 4322 default: 4323 goto tr_stalled; 4324 } 4325 break; 4326 4327 case UT_READ_INTERFACE: 4328 switch (req->bRequest) { 4329 case UR_GET_INTERFACE: 4330 goto tr_handle_get_interface; 4331 case UR_GET_STATUS: 4332 goto tr_handle_get_iface_status; 4333 default: 4334 goto tr_stalled; 4335 } 4336 break; 4337 4338 case UT_WRITE_CLASS_INTERFACE: 4339 case UT_WRITE_VENDOR_INTERFACE: 4340 /* XXX forward */ 4341 break; 4342 4343 case UT_READ_CLASS_INTERFACE: 4344 case UT_READ_VENDOR_INTERFACE: 4345 /* XXX forward */ 4346 break; 4347 4348 case UT_WRITE_CLASS_DEVICE: 4349 switch (req->bRequest) { 4350 case UR_CLEAR_FEATURE: 4351 goto tr_valid; 4352 case UR_SET_DESCRIPTOR: 4353 case UR_SET_FEATURE: 4354 break; 4355 default: 4356 goto tr_stalled; 4357 } 4358 break; 4359 4360 case UT_WRITE_CLASS_OTHER: 4361 switch (req->bRequest) { 4362 case UR_CLEAR_FEATURE: 4363 goto tr_handle_clear_port_feature; 4364 case UR_SET_FEATURE: 4365 goto tr_handle_set_port_feature; 4366 case UR_CLEAR_TT_BUFFER: 4367 case UR_RESET_TT: 4368 case UR_STOP_TT: 4369 goto tr_valid; 4370 4371 default: 4372 goto tr_stalled; 4373 } 4374 break; 4375 4376 case UT_READ_CLASS_OTHER: 4377 switch (req->bRequest) { 4378 case UR_GET_TT_STATE: 4379 goto tr_handle_get_tt_state; 4380 case UR_GET_STATUS: 4381 goto tr_handle_get_port_status; 4382 default: 4383 goto tr_stalled; 4384 } 4385 break; 4386 4387 case UT_READ_CLASS_DEVICE: 4388 switch (req->bRequest) { 4389 case UR_GET_DESCRIPTOR: 4390 goto tr_handle_get_class_descriptor; 4391 case UR_GET_STATUS: 4392 goto tr_handle_get_class_status; 4393 4394 default: 4395 goto tr_stalled; 4396 } 4397 break; 4398 default: 4399 goto tr_stalled; 4400 } 4401 goto tr_valid; 4402 4403 tr_handle_get_descriptor: 4404 switch (value >> 8) { 4405 case UDESC_DEVICE: 4406 if (value & 0xff) { 4407 goto tr_stalled; 4408 } 4409 len = sizeof(dwc_otg_devd); 4410 ptr = (const void *)&dwc_otg_devd; 4411 goto tr_valid; 4412 case UDESC_CONFIG: 4413 if (value & 0xff) { 4414 goto tr_stalled; 4415 } 4416 len = sizeof(dwc_otg_confd); 4417 ptr = (const void *)&dwc_otg_confd; 4418 goto tr_valid; 4419 case UDESC_STRING: 4420 switch (value & 0xff) { 4421 case 0: /* Language table */ 4422 len = sizeof(usb_string_lang_en); 4423 ptr = (const void *)&usb_string_lang_en; 4424 goto tr_valid; 4425 4426 case 1: /* Vendor */ 4427 len = sizeof(dwc_otg_vendor); 4428 ptr = (const void *)&dwc_otg_vendor; 4429 goto tr_valid; 4430 4431 case 2: /* Product */ 4432 len = sizeof(dwc_otg_product); 4433 ptr = (const void *)&dwc_otg_product; 4434 goto tr_valid; 4435 default: 4436 break; 4437 } 4438 break; 4439 default: 4440 goto tr_stalled; 4441 } 4442 goto tr_stalled; 4443 4444 tr_handle_get_config: 4445 len = 1; 4446 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 4447 goto tr_valid; 4448 4449 tr_handle_get_status: 4450 len = 2; 4451 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 4452 goto tr_valid; 4453 4454 tr_handle_set_address: 4455 if (value & 0xFF00) { 4456 goto tr_stalled; 4457 } 4458 sc->sc_rt_addr = value; 4459 goto tr_valid; 4460 4461 tr_handle_set_config: 4462 if (value >= 2) { 4463 goto tr_stalled; 4464 } 4465 sc->sc_conf = value; 4466 goto tr_valid; 4467 4468 tr_handle_get_interface: 4469 len = 1; 4470 sc->sc_hub_temp.wValue[0] = 0; 4471 goto tr_valid; 4472 4473 tr_handle_get_tt_state: 4474 tr_handle_get_class_status: 4475 tr_handle_get_iface_status: 4476 tr_handle_get_ep_status: 4477 len = 2; 4478 USETW(sc->sc_hub_temp.wValue, 0); 4479 goto tr_valid; 4480 4481 tr_handle_set_halt: 4482 tr_handle_set_interface: 4483 tr_handle_set_wakeup: 4484 tr_handle_clear_wakeup: 4485 tr_handle_clear_halt: 4486 goto tr_valid; 4487 4488 tr_handle_clear_port_feature: 4489 if (index != 1) 4490 goto tr_stalled; 4491 4492 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 4493 4494 switch (value) { 4495 case UHF_PORT_SUSPEND: 4496 dwc_otg_wakeup_peer(sc); 4497 break; 4498 4499 case UHF_PORT_ENABLE: 4500 if (sc->sc_flags.status_device_mode == 0) { 4501 DWC_OTG_WRITE_4(sc, DOTG_HPRT, 4502 sc->sc_hprt_val | HPRT_PRTENA); 4503 } 4504 sc->sc_flags.port_enabled = 0; 4505 break; 4506 4507 case UHF_C_PORT_RESET: 4508 sc->sc_flags.change_reset = 0; 4509 break; 4510 4511 case UHF_C_PORT_ENABLE: 4512 sc->sc_flags.change_enabled = 0; 4513 break; 4514 4515 case UHF_C_PORT_OVER_CURRENT: 4516 sc->sc_flags.change_over_current = 0; 4517 break; 4518 4519 case UHF_PORT_TEST: 4520 case UHF_PORT_INDICATOR: 4521 /* nops */ 4522 break; 4523 4524 case UHF_PORT_POWER: 4525 sc->sc_flags.port_powered = 0; 4526 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4527 sc->sc_hprt_val = 0; 4528 DWC_OTG_WRITE_4(sc, DOTG_HPRT, HPRT_PRTENA); 4529 } 4530 dwc_otg_pull_down(sc); 4531 dwc_otg_clocks_off(sc); 4532 break; 4533 4534 case UHF_C_PORT_CONNECTION: 4535 /* clear connect change flag */ 4536 sc->sc_flags.change_connect = 0; 4537 break; 4538 4539 case UHF_C_PORT_SUSPEND: 4540 sc->sc_flags.change_suspend = 0; 4541 break; 4542 4543 default: 4544 err = USB_ERR_IOERROR; 4545 goto done; 4546 } 4547 goto tr_valid; 4548 4549 tr_handle_set_port_feature: 4550 if (index != 1) { 4551 goto tr_stalled; 4552 } 4553 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 4554 4555 switch (value) { 4556 case UHF_PORT_ENABLE: 4557 break; 4558 4559 case UHF_PORT_SUSPEND: 4560 if (sc->sc_flags.status_device_mode == 0) { 4561 /* set suspend BIT */ 4562 sc->sc_hprt_val |= HPRT_PRTSUSP; 4563 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4564 4565 /* generate HUB suspend event */ 4566 dwc_otg_suspend_irq(sc); 4567 } 4568 break; 4569 4570 case UHF_PORT_RESET: 4571 if (sc->sc_flags.status_device_mode == 0) { 4572 4573 DPRINTF("PORT RESET\n"); 4574 4575 /* enable PORT reset */ 4576 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val | HPRT_PRTRST); 4577 4578 /* Wait 62.5ms for reset to complete */ 4579 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4580 4581 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4582 4583 /* Wait 62.5ms for reset to complete */ 4584 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 16); 4585 4586 /* reset FIFOs */ 4587 (void) dwc_otg_init_fifo(sc, DWC_MODE_HOST); 4588 4589 sc->sc_flags.change_reset = 1; 4590 } else { 4591 err = USB_ERR_IOERROR; 4592 } 4593 break; 4594 4595 case UHF_PORT_TEST: 4596 case UHF_PORT_INDICATOR: 4597 /* nops */ 4598 break; 4599 case UHF_PORT_POWER: 4600 sc->sc_flags.port_powered = 1; 4601 if (sc->sc_mode == DWC_MODE_HOST || sc->sc_mode == DWC_MODE_OTG) { 4602 sc->sc_hprt_val |= HPRT_PRTPWR; 4603 DWC_OTG_WRITE_4(sc, DOTG_HPRT, sc->sc_hprt_val); 4604 } 4605 if (sc->sc_mode == DWC_MODE_DEVICE || sc->sc_mode == DWC_MODE_OTG) { 4606 /* pull up D+, if any */ 4607 dwc_otg_pull_up(sc); 4608 } 4609 break; 4610 default: 4611 err = USB_ERR_IOERROR; 4612 goto done; 4613 } 4614 goto tr_valid; 4615 4616 tr_handle_get_port_status: 4617 4618 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 4619 4620 if (index != 1) 4621 goto tr_stalled; 4622 4623 if (sc->sc_flags.status_vbus) 4624 dwc_otg_clocks_on(sc); 4625 else 4626 dwc_otg_clocks_off(sc); 4627 4628 /* Select Device Side Mode */ 4629 4630 if (sc->sc_flags.status_device_mode) { 4631 value = UPS_PORT_MODE_DEVICE; 4632 dwc_otg_timer_stop(sc); 4633 } else { 4634 value = 0; 4635 dwc_otg_timer_start(sc); 4636 } 4637 4638 if (sc->sc_flags.status_high_speed) 4639 value |= UPS_HIGH_SPEED; 4640 else if (sc->sc_flags.status_low_speed) 4641 value |= UPS_LOW_SPEED; 4642 4643 if (sc->sc_flags.port_powered) 4644 value |= UPS_PORT_POWER; 4645 4646 if (sc->sc_flags.port_enabled) 4647 value |= UPS_PORT_ENABLED; 4648 4649 if (sc->sc_flags.port_over_current) 4650 value |= UPS_OVERCURRENT_INDICATOR; 4651 4652 if (sc->sc_flags.status_vbus && 4653 sc->sc_flags.status_bus_reset) 4654 value |= UPS_CURRENT_CONNECT_STATUS; 4655 4656 if (sc->sc_flags.status_suspend) 4657 value |= UPS_SUSPEND; 4658 4659 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 4660 4661 value = 0; 4662 4663 if (sc->sc_flags.change_connect) 4664 value |= UPS_C_CONNECT_STATUS; 4665 if (sc->sc_flags.change_suspend) 4666 value |= UPS_C_SUSPEND; 4667 if (sc->sc_flags.change_reset) 4668 value |= UPS_C_PORT_RESET; 4669 if (sc->sc_flags.change_over_current) 4670 value |= UPS_C_OVERCURRENT_INDICATOR; 4671 4672 USETW(sc->sc_hub_temp.ps.wPortChange, value); 4673 len = sizeof(sc->sc_hub_temp.ps); 4674 goto tr_valid; 4675 4676 tr_handle_get_class_descriptor: 4677 if (value & 0xFF) { 4678 goto tr_stalled; 4679 } 4680 ptr = (const void *)&dwc_otg_hubd; 4681 len = sizeof(dwc_otg_hubd); 4682 goto tr_valid; 4683 4684 tr_stalled: 4685 err = USB_ERR_STALLED; 4686 tr_valid: 4687 done: 4688 *plength = len; 4689 *pptr = ptr; 4690 return (err); 4691 } 4692 4693 static void 4694 dwc_otg_xfer_setup(struct usb_setup_params *parm) 4695 { 4696 struct usb_xfer *xfer; 4697 void *last_obj; 4698 uint32_t ntd; 4699 uint32_t n; 4700 uint8_t ep_no; 4701 uint8_t ep_type; 4702 4703 xfer = parm->curr_xfer; 4704 4705 /* 4706 * NOTE: This driver does not use any of the parameters that 4707 * are computed from the following values. Just set some 4708 * reasonable dummies: 4709 */ 4710 parm->hc_max_packet_size = 0x500; 4711 parm->hc_max_packet_count = 3; 4712 parm->hc_max_frame_size = 3 * 0x500; 4713 4714 usbd_transfer_setup_sub(parm); 4715 4716 /* 4717 * compute maximum number of TDs 4718 */ 4719 ep_type = (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE); 4720 4721 if (ep_type == UE_CONTROL) { 4722 4723 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 4724 + 1 /* SYNC 2 */ + 1 /* SYNC 3 */; 4725 } else { 4726 4727 ntd = xfer->nframes + 1 /* SYNC */ ; 4728 } 4729 4730 /* 4731 * check if "usbd_transfer_setup_sub" set an error 4732 */ 4733 if (parm->err) 4734 return; 4735 4736 /* 4737 * allocate transfer descriptors 4738 */ 4739 last_obj = NULL; 4740 4741 ep_no = xfer->endpointno & UE_ADDR; 4742 4743 /* 4744 * Check for a valid endpoint profile in USB device mode: 4745 */ 4746 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 4747 const struct usb_hw_ep_profile *pf; 4748 4749 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 4750 4751 if (pf == NULL) { 4752 /* should not happen */ 4753 parm->err = USB_ERR_INVAL; 4754 return; 4755 } 4756 } 4757 4758 /* align data */ 4759 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 4760 4761 for (n = 0; n != ntd; n++) { 4762 4763 struct dwc_otg_td *td; 4764 4765 if (parm->buf) { 4766 4767 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 4768 4769 /* compute shared bandwidth resource index for TT */ 4770 if (parm->udev->parent_hs_hub != NULL && parm->udev->speed != USB_SPEED_HIGH) { 4771 if (parm->udev->parent_hs_hub->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) 4772 td->tt_index = parm->udev->device_index; 4773 else 4774 td->tt_index = parm->udev->parent_hs_hub->device_index; 4775 } else { 4776 td->tt_index = parm->udev->device_index; 4777 } 4778 4779 /* init TD */ 4780 td->max_packet_size = xfer->max_packet_size; 4781 td->max_packet_count = xfer->max_packet_count; 4782 td->ep_no = ep_no; 4783 td->ep_type = ep_type; 4784 td->obj_next = last_obj; 4785 4786 last_obj = td; 4787 } 4788 parm->size[0] += sizeof(*td); 4789 } 4790 4791 xfer->td_start[0] = last_obj; 4792 } 4793 4794 static void 4795 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 4796 { 4797 return; 4798 } 4799 4800 static void 4801 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 4802 struct usb_endpoint *ep) 4803 { 4804 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 4805 4806 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 4807 ep, udev->address, 4808 edesc->bEndpointAddress, udev->flags.usb_mode, 4809 sc->sc_rt_addr, udev->device_index); 4810 4811 if (udev->device_index != sc->sc_rt_addr) { 4812 4813 if (udev->flags.usb_mode == USB_MODE_DEVICE) { 4814 if (udev->speed != USB_SPEED_FULL && 4815 udev->speed != USB_SPEED_HIGH) { 4816 /* not supported */ 4817 return; 4818 } 4819 } else { 4820 if (udev->speed == USB_SPEED_HIGH) { 4821 if ((UGETW(edesc->wMaxPacketSize) >> 11) & 3) { 4822 /* high bandwidth endpoint - not tested */ 4823 DPRINTF("High Bandwidth Endpoint - not tested\n"); 4824 return; 4825 } 4826 } 4827 } 4828 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 4829 ep->methods = &dwc_otg_device_isoc_methods; 4830 else 4831 ep->methods = &dwc_otg_device_non_isoc_methods; 4832 } 4833 } 4834 4835 static void 4836 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 4837 { 4838 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 4839 4840 switch (state) { 4841 case USB_HW_POWER_SUSPEND: 4842 dwc_otg_suspend(sc); 4843 break; 4844 case USB_HW_POWER_SHUTDOWN: 4845 dwc_otg_uninit(sc); 4846 break; 4847 case USB_HW_POWER_RESUME: 4848 dwc_otg_resume(sc); 4849 break; 4850 default: 4851 break; 4852 } 4853 } 4854 4855 static void 4856 dwc_otg_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4857 { 4858 /* DMA delay - wait until any use of memory is finished */ 4859 *pus = (2125); /* microseconds */ 4860 } 4861 4862 static void 4863 dwc_otg_device_resume(struct usb_device *udev) 4864 { 4865 DPRINTF("\n"); 4866 4867 /* poll all transfers again to restart resumed ones */ 4868 dwc_otg_do_poll(udev->bus); 4869 } 4870 4871 static void 4872 dwc_otg_device_suspend(struct usb_device *udev) 4873 { 4874 DPRINTF("\n"); 4875 } 4876 4877 static const struct usb_bus_methods dwc_otg_bus_methods = 4878 { 4879 .endpoint_init = &dwc_otg_ep_init, 4880 .xfer_setup = &dwc_otg_xfer_setup, 4881 .xfer_unsetup = &dwc_otg_xfer_unsetup, 4882 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 4883 .xfer_stall = &dwc_otg_xfer_stall, 4884 .set_stall = &dwc_otg_set_stall, 4885 .clear_stall = &dwc_otg_clear_stall, 4886 .roothub_exec = &dwc_otg_roothub_exec, 4887 .xfer_poll = &dwc_otg_do_poll, 4888 .device_state_change = &dwc_otg_device_state_change, 4889 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 4890 .get_dma_delay = &dwc_otg_get_dma_delay, 4891 .device_resume = &dwc_otg_device_resume, 4892 .device_suspend = &dwc_otg_device_suspend, 4893 }; 4894