1 /*- 2 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * This file contains the driver for the DesignWare series USB 2.0 OTG 28 * Controller. This driver currently only supports the device mode of 29 * the USB hardware. 30 */ 31 32 /* 33 * LIMITATION: Drivers must be bound to all OUT endpoints in the 34 * active configuration for this driver to work properly. Blocking any 35 * OUT endpoint will block all OUT endpoints including the control 36 * endpoint. Usually this is not a problem. 37 */ 38 39 /* 40 * NOTE: Writing to non-existing registers appears to cause an 41 * internal reset. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/stdint.h> 48 #include <sys/stddef.h> 49 #include <sys/param.h> 50 #include <sys/queue.h> 51 #include <sys/types.h> 52 #include <sys/systm.h> 53 #include <sys/kernel.h> 54 #include <sys/bus.h> 55 #include <sys/module.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <sys/condvar.h> 59 #include <sys/sysctl.h> 60 #include <sys/sx.h> 61 #include <sys/unistd.h> 62 #include <sys/callout.h> 63 #include <sys/malloc.h> 64 #include <sys/priv.h> 65 66 #include <dev/usb/usb.h> 67 #include <dev/usb/usbdi.h> 68 69 #define USB_DEBUG_VAR dwc_otg_debug 70 71 #include <dev/usb/usb_core.h> 72 #include <dev/usb/usb_debug.h> 73 #include <dev/usb/usb_busdma.h> 74 #include <dev/usb/usb_process.h> 75 #include <dev/usb/usb_transfer.h> 76 #include <dev/usb/usb_device.h> 77 #include <dev/usb/usb_hub.h> 78 #include <dev/usb/usb_util.h> 79 80 #include <dev/usb/usb_controller.h> 81 #include <dev/usb/usb_bus.h> 82 83 #include <dev/usb/controller/dwc_otg.h> 84 85 #define DWC_OTG_BUS2SC(bus) \ 86 ((struct dwc_otg_softc *)(((uint8_t *)(bus)) - \ 87 ((uint8_t *)&(((struct dwc_otg_softc *)0)->sc_bus)))) 88 89 #define DWC_OTG_PC2SC(pc) \ 90 DWC_OTG_BUS2SC(USB_DMATAG_TO_XROOT((pc)->tag_parent)->bus) 91 92 #define DWC_OTG_MSK_GINT_ENABLED \ 93 (DWC_OTG_MSK_GINT_ENUM_DONE | \ 94 DWC_OTG_MSK_GINT_USB_RESET | \ 95 DWC_OTG_MSK_GINT_USB_SUSPEND | \ 96 DWC_OTG_MSK_GINT_INEP | \ 97 DWC_OTG_MSK_GINT_RXFLVL | \ 98 DWC_OTG_MSK_GINT_SESSREQINT) 99 100 #define DWC_OTG_USE_HSIC 0 101 102 #ifdef USB_DEBUG 103 static int dwc_otg_debug = 0; 104 105 static SYSCTL_NODE(_hw_usb, OID_AUTO, dwc_otg, CTLFLAG_RW, 0, "USB DWC OTG"); 106 SYSCTL_INT(_hw_usb_dwc_otg, OID_AUTO, debug, CTLFLAG_RW, 107 &dwc_otg_debug, 0, "DWC OTG debug level"); 108 #endif 109 110 #define DWC_OTG_INTR_ENDPT 1 111 112 /* prototypes */ 113 114 struct usb_bus_methods dwc_otg_bus_methods; 115 struct usb_pipe_methods dwc_otg_device_non_isoc_methods; 116 struct usb_pipe_methods dwc_otg_device_isoc_fs_methods; 117 118 static dwc_otg_cmd_t dwc_otg_setup_rx; 119 static dwc_otg_cmd_t dwc_otg_data_rx; 120 static dwc_otg_cmd_t dwc_otg_data_tx; 121 static dwc_otg_cmd_t dwc_otg_data_tx_sync; 122 static void dwc_otg_device_done(struct usb_xfer *, usb_error_t); 123 static void dwc_otg_do_poll(struct usb_bus *); 124 static void dwc_otg_standard_done(struct usb_xfer *); 125 static void dwc_otg_root_intr(struct dwc_otg_softc *sc); 126 127 /* 128 * Here is a configuration that the chip supports. 129 */ 130 static const struct usb_hw_ep_profile dwc_otg_ep_profile[1] = { 131 132 [0] = { 133 .max_in_frame_size = 64,/* fixed */ 134 .max_out_frame_size = 64, /* fixed */ 135 .is_simplex = 1, 136 .support_control = 1, 137 } 138 }; 139 140 static void 141 dwc_otg_get_hw_ep_profile(struct usb_device *udev, 142 const struct usb_hw_ep_profile **ppf, uint8_t ep_addr) 143 { 144 struct dwc_otg_softc *sc; 145 146 sc = DWC_OTG_BUS2SC(udev->bus); 147 148 if (ep_addr < sc->sc_dev_ep_max) 149 *ppf = &sc->sc_hw_ep_profile[ep_addr].usb; 150 else 151 *ppf = NULL; 152 } 153 154 static int 155 dwc_otg_init_fifo(struct dwc_otg_softc *sc) 156 { 157 struct dwc_otg_profile *pf; 158 uint32_t fifo_size; 159 uint32_t fifo_regs; 160 uint32_t tx_start; 161 uint8_t x; 162 163 fifo_size = sc->sc_fifo_size; 164 165 fifo_regs = 4 * (sc->sc_dev_ep_max + sc->sc_dev_in_ep_max); 166 167 if (fifo_size >= fifo_regs) 168 fifo_size -= fifo_regs; 169 else 170 fifo_size = 0; 171 172 /* split equally for IN and OUT */ 173 fifo_size /= 2; 174 175 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRXFSIZ, fifo_size / 4); 176 177 /* align to 4-bytes */ 178 fifo_size &= ~3; 179 180 tx_start = fifo_size; 181 182 if (fifo_size < 0x40) { 183 DPRINTFN(-1, "Not enough data space for EP0 FIFO.\n"); 184 USB_BUS_UNLOCK(&sc->sc_bus); 185 return (EINVAL); 186 } 187 188 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GNPTXFSIZ, (0x10 << 16) | (tx_start / 4)); 189 fifo_size -= 0x40; 190 tx_start += 0x40; 191 192 /* setup control endpoint profile */ 193 sc->sc_hw_ep_profile[0].usb = dwc_otg_ep_profile[0]; 194 195 for (x = 1; x != sc->sc_dev_ep_max; x++) { 196 197 pf = sc->sc_hw_ep_profile + x; 198 199 pf->usb.max_out_frame_size = 1024 * 3; 200 pf->usb.is_simplex = 0; /* assume duplex */ 201 pf->usb.support_bulk = 1; 202 pf->usb.support_interrupt = 1; 203 pf->usb.support_isochronous = 1; 204 pf->usb.support_out = 1; 205 206 if (x < sc->sc_dev_in_ep_max) { 207 uint32_t limit; 208 209 limit = (x == 1) ? DWC_OTG_MAX_TXN : 210 (DWC_OTG_MAX_TXN / 2); 211 212 if (fifo_size >= limit) { 213 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x), 214 ((limit / 4) << 16) | 215 (tx_start / 4)); 216 tx_start += limit; 217 fifo_size -= limit; 218 pf->usb.max_in_frame_size = 0x200; 219 pf->usb.support_in = 1; 220 pf->max_buffer = limit; 221 222 } else if (fifo_size >= 0x80) { 223 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x), 224 ((0x80 / 4) << 16) | (tx_start / 4)); 225 tx_start += 0x80; 226 fifo_size -= 0x80; 227 pf->usb.max_in_frame_size = 0x40; 228 pf->usb.support_in = 1; 229 230 } else { 231 pf->usb.is_simplex = 1; 232 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTXF(x), 233 (0x0 << 16) | (tx_start / 4)); 234 } 235 } else { 236 pf->usb.is_simplex = 1; 237 } 238 239 DPRINTF("FIFO%d = IN:%d / OUT:%d\n", x, 240 pf->usb.max_in_frame_size, 241 pf->usb.max_out_frame_size); 242 } 243 244 /* reset RX FIFO */ 245 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 246 DWC_OTG_MSK_GRSTCTL_RXFFLUSH); 247 248 /* reset all TX FIFOs */ 249 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 250 DWC_OTG_MSK_GRSTCTL_TXFIFO(0x10) | 251 DWC_OTG_MSK_GRSTCTL_TXFFLUSH); 252 253 return (0); 254 } 255 256 static void 257 dwc_otg_clocks_on(struct dwc_otg_softc *sc) 258 { 259 if (sc->sc_flags.clocks_off && 260 sc->sc_flags.port_powered) { 261 262 DPRINTFN(5, "\n"); 263 264 /* TODO - platform specific */ 265 266 sc->sc_flags.clocks_off = 0; 267 } 268 } 269 270 static void 271 dwc_otg_clocks_off(struct dwc_otg_softc *sc) 272 { 273 if (!sc->sc_flags.clocks_off) { 274 275 DPRINTFN(5, "\n"); 276 277 /* TODO - platform specific */ 278 279 sc->sc_flags.clocks_off = 1; 280 } 281 } 282 283 static void 284 dwc_otg_pull_up(struct dwc_otg_softc *sc) 285 { 286 uint32_t temp; 287 288 /* pullup D+, if possible */ 289 290 if (!sc->sc_flags.d_pulled_up && 291 sc->sc_flags.port_powered) { 292 sc->sc_flags.d_pulled_up = 1; 293 294 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL); 295 temp &= ~DWC_OTG_MSK_DCTL_SOFT_DISC; 296 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp); 297 } 298 } 299 300 static void 301 dwc_otg_pull_down(struct dwc_otg_softc *sc) 302 { 303 uint32_t temp; 304 305 /* pulldown D+, if possible */ 306 307 if (sc->sc_flags.d_pulled_up) { 308 sc->sc_flags.d_pulled_up = 0; 309 310 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL); 311 temp |= DWC_OTG_MSK_DCTL_SOFT_DISC; 312 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp); 313 } 314 } 315 316 static void 317 dwc_otg_resume_irq(struct dwc_otg_softc *sc) 318 { 319 if (sc->sc_flags.status_suspend) { 320 /* update status bits */ 321 sc->sc_flags.status_suspend = 0; 322 sc->sc_flags.change_suspend = 1; 323 324 /* 325 * Disable resume interrupt and enable suspend 326 * interrupt: 327 */ 328 sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_WKUPINT; 329 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_USB_SUSPEND; 330 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 331 332 /* complete root HUB interrupt endpoint */ 333 dwc_otg_root_intr(sc); 334 } 335 } 336 337 static void 338 dwc_otg_wakeup_peer(struct dwc_otg_softc *sc) 339 { 340 uint32_t temp; 341 342 if (!sc->sc_flags.status_suspend) 343 return; 344 345 DPRINTFN(5, "Remote wakeup\n"); 346 347 /* enable remote wakeup signalling */ 348 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCTL); 349 temp |= DWC_OTG_MSK_DCTL_REMOTE_WAKEUP; 350 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp); 351 352 /* Wait 8ms for remote wakeup to complete. */ 353 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 125); 354 355 temp &= ~DWC_OTG_MSK_DCTL_REMOTE_WAKEUP; 356 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, temp); 357 358 /* need to fake resume IRQ */ 359 dwc_otg_resume_irq(sc); 360 } 361 362 static void 363 dwc_otg_set_address(struct dwc_otg_softc *sc, uint8_t addr) 364 { 365 uint32_t temp; 366 367 DPRINTFN(5, "addr=%d\n", addr); 368 369 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DCFG); 370 temp &= ~DWC_OTG_MSK_DCFG_SET_DEV_ADDR(0x7F); 371 temp |= DWC_OTG_MSK_DCFG_SET_DEV_ADDR(addr); 372 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCFG, temp); 373 } 374 375 static void 376 dwc_otg_common_rx_ack(struct dwc_otg_softc *sc) 377 { 378 DPRINTFN(5, "RX status clear\n"); 379 380 /* enable RX FIFO level interrupt */ 381 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_RXFLVL; 382 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 383 384 /* clear cached status */ 385 sc->sc_last_rx_status = 0; 386 } 387 388 static uint8_t 389 dwc_otg_setup_rx(struct dwc_otg_td *td) 390 { 391 struct dwc_otg_softc *sc; 392 struct usb_device_request req __aligned(4); 393 uint32_t temp; 394 uint16_t count; 395 396 /* get pointer to softc */ 397 sc = DWC_OTG_PC2SC(td->pc); 398 399 /* check endpoint status */ 400 401 if (sc->sc_last_rx_status == 0) 402 goto not_complete; 403 404 if (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(sc->sc_last_rx_status) != 0) 405 goto not_complete; 406 407 if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PID) != 408 DWC_OTG_MSK_GRXSTS_PID_DATA0) { 409 /* release FIFO */ 410 dwc_otg_common_rx_ack(sc); 411 goto not_complete; 412 } 413 414 if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) != 415 DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) { 416 /* release FIFO */ 417 dwc_otg_common_rx_ack(sc); 418 goto not_complete; 419 } 420 421 DPRINTFN(5, "GRXSTSR=0x%08x\n", sc->sc_last_rx_status); 422 423 /* clear did stall */ 424 td->did_stall = 0; 425 426 /* get the packet byte count */ 427 count = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status); 428 429 /* verify data length */ 430 if (count != td->remainder) { 431 DPRINTFN(0, "Invalid SETUP packet " 432 "length, %d bytes\n", count); 433 /* release FIFO */ 434 dwc_otg_common_rx_ack(sc); 435 goto not_complete; 436 } 437 if (count != sizeof(req)) { 438 DPRINTFN(0, "Unsupported SETUP packet " 439 "length, %d bytes\n", count); 440 /* release FIFO */ 441 dwc_otg_common_rx_ack(sc); 442 goto not_complete; 443 } 444 445 /* copy in control request */ 446 memcpy(&req, sc->sc_rx_bounce_buffer, sizeof(req)); 447 448 /* copy data into real buffer */ 449 usbd_copy_in(td->pc, 0, &req, sizeof(req)); 450 451 td->offset = sizeof(req); 452 td->remainder = 0; 453 454 /* sneak peek the set address */ 455 if ((req.bmRequestType == UT_WRITE_DEVICE) && 456 (req.bRequest == UR_SET_ADDRESS)) { 457 /* must write address before ZLP */ 458 dwc_otg_set_address(sc, req.wValue[0] & 0x7F); 459 } 460 461 /* don't send any data by default */ 462 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTSIZ(0), 463 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(0) | 464 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(0)); 465 466 temp = sc->sc_in_ctl[0]; 467 468 /* enable IN endpoint */ 469 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0), 470 temp | DWC_OTG_MSK_DIEPCTL_ENABLE); 471 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0), 472 temp | DWC_OTG_MSK_DIEPCTL_SET_NAK); 473 474 /* reset IN endpoint buffer */ 475 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 476 DWC_OTG_MSK_GRSTCTL_TXFIFO(0) | 477 DWC_OTG_MSK_GRSTCTL_TXFFLUSH); 478 479 /* acknowledge RX status */ 480 dwc_otg_common_rx_ack(sc); 481 return (0); /* complete */ 482 483 not_complete: 484 /* abort any ongoing transfer, before enabling again */ 485 486 temp = sc->sc_out_ctl[0]; 487 488 temp |= DWC_OTG_MSK_DOEPCTL_ENABLE | 489 DWC_OTG_MSK_DOEPCTL_SET_NAK; 490 491 /* enable OUT endpoint */ 492 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(0), temp); 493 494 if (!td->did_stall) { 495 td->did_stall = 1; 496 497 DPRINTFN(5, "stalling IN and OUT direction\n"); 498 499 /* set stall after enabling endpoint */ 500 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(0), 501 temp | DWC_OTG_MSK_DOEPCTL_STALL); 502 503 temp = sc->sc_in_ctl[0]; 504 505 /* set stall assuming endpoint is enabled */ 506 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(0), 507 temp | DWC_OTG_MSK_DIEPCTL_STALL); 508 } 509 510 /* setup number of buffers to receive */ 511 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(0), 512 DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(3) | 513 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(1) | 514 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(sizeof(req))); 515 516 return (1); /* not complete */ 517 } 518 519 static uint8_t 520 dwc_otg_data_rx(struct dwc_otg_td *td) 521 { 522 struct dwc_otg_softc *sc; 523 uint32_t temp; 524 uint16_t count; 525 uint8_t got_short; 526 527 got_short = 0; 528 529 /* get pointer to softc */ 530 sc = DWC_OTG_PC2SC(td->pc); 531 532 /* check endpoint status */ 533 if (sc->sc_last_rx_status == 0) 534 goto not_complete; 535 536 if (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(sc->sc_last_rx_status) != td->ep_no) 537 goto not_complete; 538 539 /* check for SETUP packet */ 540 if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) == 541 DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) { 542 if (td->remainder == 0) { 543 /* 544 * We are actually complete and have 545 * received the next SETUP 546 */ 547 DPRINTFN(5, "faking complete\n"); 548 return (0); /* complete */ 549 } 550 /* 551 * USB Host Aborted the transfer. 552 */ 553 td->error = 1; 554 return (0); /* complete */ 555 } 556 557 if ((sc->sc_last_rx_status & DWC_OTG_MSK_GRXSTS_PACKET_STS) != 558 DWC_OTG_MSK_GRXSTS_DEV_OUT_DATA) { 559 /* release FIFO */ 560 dwc_otg_common_rx_ack(sc); 561 goto not_complete; 562 } 563 564 /* get the packet byte count */ 565 count = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status); 566 567 /* verify the packet byte count */ 568 if (count != td->max_packet_size) { 569 if (count < td->max_packet_size) { 570 /* we have a short packet */ 571 td->short_pkt = 1; 572 got_short = 1; 573 } else { 574 /* invalid USB packet */ 575 td->error = 1; 576 577 /* release FIFO */ 578 dwc_otg_common_rx_ack(sc); 579 return (0); /* we are complete */ 580 } 581 } 582 /* verify the packet byte count */ 583 if (count > td->remainder) { 584 /* invalid USB packet */ 585 td->error = 1; 586 587 /* release FIFO */ 588 dwc_otg_common_rx_ack(sc); 589 return (0); /* we are complete */ 590 } 591 592 usbd_copy_in(td->pc, td->offset, sc->sc_rx_bounce_buffer, count); 593 td->remainder -= count; 594 td->offset += count; 595 596 /* release FIFO */ 597 dwc_otg_common_rx_ack(sc); 598 599 /* check if we are complete */ 600 if ((td->remainder == 0) || got_short) { 601 if (td->short_pkt) { 602 /* we are complete */ 603 return (0); 604 } 605 /* else need to receive a zero length packet */ 606 } 607 608 not_complete: 609 610 temp = sc->sc_out_ctl[td->ep_no]; 611 612 temp |= DWC_OTG_MSK_DOEPCTL_ENABLE | 613 DWC_OTG_MSK_DOEPCTL_CLR_NAK; 614 615 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(td->ep_no), temp); 616 617 /* enable SETUP and transfer complete interrupt */ 618 if (td->ep_no == 0) { 619 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(0), 620 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(1) | 621 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(td->max_packet_size)); 622 } else { 623 /* allow reception of multiple packets */ 624 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPTSIZ(td->ep_no), 625 DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(1) | 626 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(4) | 627 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(4 * 628 ((td->max_packet_size + 3) & ~3))); 629 } 630 return (1); /* not complete */ 631 } 632 633 static uint8_t 634 dwc_otg_data_tx(struct dwc_otg_td *td) 635 { 636 struct dwc_otg_softc *sc; 637 uint32_t max_buffer; 638 uint32_t count; 639 uint32_t fifo_left; 640 uint32_t mpkt; 641 uint32_t temp; 642 uint8_t to; 643 644 to = 3; /* don't loop forever! */ 645 646 /* get pointer to softc */ 647 sc = DWC_OTG_PC2SC(td->pc); 648 649 max_buffer = sc->sc_hw_ep_profile[td->ep_no].max_buffer; 650 651 repeat: 652 /* check for for endpoint 0 data */ 653 654 temp = sc->sc_last_rx_status; 655 656 if ((td->ep_no == 0) && (temp != 0) && 657 (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(temp) == 0)) { 658 659 if ((temp & DWC_OTG_MSK_GRXSTS_PACKET_STS) != 660 DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) { 661 662 /* dump data - wrong direction */ 663 dwc_otg_common_rx_ack(sc); 664 } else { 665 /* 666 * The current transfer was cancelled 667 * by the USB Host: 668 */ 669 td->error = 1; 670 return (0); /* complete */ 671 } 672 } 673 674 /* fill in more TX data, if possible */ 675 if (td->tx_bytes != 0) { 676 677 uint16_t cpkt; 678 679 /* check if packets have been transferred */ 680 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no)); 681 682 /* get current packet number */ 683 cpkt = DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp); 684 685 if (cpkt >= td->npkt) { 686 fifo_left = 0; 687 } else { 688 if (max_buffer != 0) { 689 fifo_left = (td->npkt - cpkt) * 690 td->max_packet_size; 691 692 if (fifo_left > max_buffer) 693 fifo_left = max_buffer; 694 } else { 695 fifo_left = td->max_packet_size; 696 } 697 } 698 699 count = td->tx_bytes; 700 if (count > fifo_left) 701 count = fifo_left; 702 703 if (count != 0) { 704 705 /* clear topmost word before copy */ 706 sc->sc_tx_bounce_buffer[(count - 1) / 4] = 0; 707 708 /* copy out data */ 709 usbd_copy_out(td->pc, td->offset, 710 sc->sc_tx_bounce_buffer, count); 711 712 /* transfer data into FIFO */ 713 bus_space_write_region_4(sc->sc_io_tag, sc->sc_io_hdl, 714 DWC_OTG_REG_DFIFO(td->ep_no), 715 sc->sc_tx_bounce_buffer, (count + 3) / 4); 716 717 td->tx_bytes -= count; 718 td->remainder -= count; 719 td->offset += count; 720 td->npkt = cpkt; 721 } 722 if (td->tx_bytes != 0) 723 goto not_complete; 724 725 /* check remainder */ 726 if (td->remainder == 0) { 727 if (td->short_pkt) 728 return (0); /* complete */ 729 730 /* else we need to transmit a short packet */ 731 } 732 } 733 734 if (!to--) 735 goto not_complete; 736 737 /* check if not all packets have been transferred */ 738 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no)); 739 740 if (DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp) != 0) { 741 742 DPRINTFN(5, "busy ep=%d npkt=%d DIEPTSIZ=0x%08x " 743 "DIEPCTL=0x%08x\n", td->ep_no, 744 DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp), 745 temp, DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPCTL(td->ep_no))); 746 747 goto not_complete; 748 } 749 750 DPRINTFN(5, "rem=%u ep=%d\n", td->remainder, td->ep_no); 751 752 /* try to optimise by sending more data */ 753 if ((max_buffer != 0) && ((td->max_packet_size & 3) == 0)) { 754 755 /* send multiple packets at the same time */ 756 mpkt = max_buffer / td->max_packet_size; 757 758 if (mpkt > 0x3FE) 759 mpkt = 0x3FE; 760 761 count = td->remainder; 762 if (count > 0x7FFFFF) 763 count = 0x7FFFFF - (0x7FFFFF % td->max_packet_size); 764 765 td->npkt = count / td->max_packet_size; 766 767 /* 768 * NOTE: We could use 0x3FE instead of "mpkt" in the 769 * check below to get more throughput, but then we 770 * have a dependency towards non-generic chip features 771 * to disable the TX-FIFO-EMPTY interrupts on a per 772 * endpoint basis. Increase the maximum buffer size of 773 * the IN endpoint to increase the performance. 774 */ 775 if (td->npkt > mpkt) { 776 td->npkt = mpkt; 777 count = td->max_packet_size * mpkt; 778 } else if ((count == 0) || (count % td->max_packet_size)) { 779 /* we are transmitting a short packet */ 780 td->npkt++; 781 td->short_pkt = 1; 782 } 783 } else { 784 /* send one packet at a time */ 785 mpkt = 1; 786 count = td->max_packet_size; 787 if (td->remainder < count) { 788 /* we have a short packet */ 789 td->short_pkt = 1; 790 count = td->remainder; 791 } 792 td->npkt = 1; 793 } 794 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no), 795 DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(1) | 796 DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(td->npkt) | 797 DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(count)); 798 799 /* make room for buffering */ 800 td->npkt += mpkt; 801 802 temp = sc->sc_in_ctl[td->ep_no]; 803 804 /* must enable before writing data to FIFO */ 805 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(td->ep_no), temp | 806 DWC_OTG_MSK_DIEPCTL_ENABLE | 807 DWC_OTG_MSK_DIEPCTL_CLR_NAK); 808 809 td->tx_bytes = count; 810 811 /* check remainder */ 812 if (td->tx_bytes == 0 && 813 td->remainder == 0) { 814 if (td->short_pkt) 815 return (0); /* complete */ 816 817 /* else we need to transmit a short packet */ 818 } 819 goto repeat; 820 821 not_complete: 822 return (1); /* not complete */ 823 } 824 825 static uint8_t 826 dwc_otg_data_tx_sync(struct dwc_otg_td *td) 827 { 828 struct dwc_otg_softc *sc; 829 uint32_t temp; 830 831 /* get pointer to softc */ 832 sc = DWC_OTG_PC2SC(td->pc); 833 834 /* 835 * If all packets are transferred we are complete: 836 */ 837 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no)); 838 839 /* check that all packets have been transferred */ 840 if (DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp) != 0) { 841 DPRINTFN(5, "busy ep=%d\n", td->ep_no); 842 goto not_complete; 843 } 844 return (0); 845 846 not_complete: 847 848 /* we only want to know if there is a SETUP packet or free IN packet */ 849 850 temp = sc->sc_last_rx_status; 851 852 if ((td->ep_no == 0) && (temp != 0) && 853 (DWC_OTG_MSK_GRXSTS_GET_CHANNEL(temp) == 0)) { 854 855 if ((temp & DWC_OTG_MSK_GRXSTS_PACKET_STS) == 856 DWC_OTG_MSK_GRXSTS_DEV_STP_DATA) { 857 DPRINTFN(5, "faking complete\n"); 858 /* 859 * Race condition: We are complete! 860 */ 861 return (0); 862 } else { 863 /* dump data - wrong direction */ 864 dwc_otg_common_rx_ack(sc); 865 } 866 } 867 return (1); /* not complete */ 868 } 869 870 static uint8_t 871 dwc_otg_xfer_do_fifo(struct usb_xfer *xfer) 872 { 873 struct dwc_otg_td *td; 874 875 DPRINTFN(9, "\n"); 876 877 td = xfer->td_transfer_cache; 878 while (1) { 879 if ((td->func) (td)) { 880 /* operation in progress */ 881 break; 882 } 883 if (((void *)td) == xfer->td_transfer_last) { 884 goto done; 885 } 886 if (td->error) { 887 goto done; 888 } else if (td->remainder > 0) { 889 /* 890 * We had a short transfer. If there is no alternate 891 * next, stop processing ! 892 */ 893 if (!td->alt_next) 894 goto done; 895 } 896 897 /* 898 * Fetch the next transfer descriptor and transfer 899 * some flags to the next transfer descriptor 900 */ 901 td = td->obj_next; 902 xfer->td_transfer_cache = td; 903 } 904 return (1); /* not complete */ 905 906 done: 907 /* compute all actual lengths */ 908 909 dwc_otg_standard_done(xfer); 910 return (0); /* complete */ 911 } 912 913 static void 914 dwc_otg_interrupt_poll(struct dwc_otg_softc *sc) 915 { 916 struct usb_xfer *xfer; 917 uint32_t temp; 918 uint8_t got_rx_status; 919 920 repeat: 921 if (sc->sc_last_rx_status == 0) { 922 923 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GINTSTS); 924 if (temp & DWC_OTG_MSK_GINT_RXFLVL) { 925 /* pop current status */ 926 sc->sc_last_rx_status = 927 DWC_OTG_READ_4(sc, DWC_OTG_REG_GRXSTSP); 928 } 929 930 if (sc->sc_last_rx_status != 0) { 931 932 uint8_t ep_no; 933 934 temp = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT( 935 sc->sc_last_rx_status); 936 ep_no = DWC_OTG_MSK_GRXSTS_GET_CHANNEL( 937 sc->sc_last_rx_status); 938 939 /* receive data, if any */ 940 if (temp != 0) { 941 DPRINTF("Reading %d bytes from ep %d\n", temp, ep_no); 942 bus_space_read_region_4(sc->sc_io_tag, sc->sc_io_hdl, 943 DWC_OTG_REG_DFIFO(ep_no), 944 sc->sc_rx_bounce_buffer, (temp + 3) / 4); 945 } 946 947 temp = sc->sc_last_rx_status & 948 DWC_OTG_MSK_GRXSTS_PACKET_STS; 949 950 /* non-data messages we simply skip */ 951 if (temp != DWC_OTG_MSK_GRXSTS_DEV_STP_DATA && 952 temp != DWC_OTG_MSK_GRXSTS_DEV_OUT_DATA) { 953 dwc_otg_common_rx_ack(sc); 954 goto repeat; 955 } 956 957 /* check if we should dump the data */ 958 if (!(sc->sc_active_out_ep & (1U << ep_no))) { 959 dwc_otg_common_rx_ack(sc); 960 goto repeat; 961 } 962 963 got_rx_status = 1; 964 965 DPRINTFN(5, "RX status = 0x%08x: ch=%d pid=%d bytes=%d sts=%d\n", 966 sc->sc_last_rx_status, ep_no, 967 (sc->sc_last_rx_status >> 15) & 3, 968 DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(sc->sc_last_rx_status), 969 (sc->sc_last_rx_status >> 17) & 15); 970 } else { 971 got_rx_status = 0; 972 } 973 } else { 974 uint8_t ep_no; 975 976 ep_no = DWC_OTG_MSK_GRXSTS_GET_CHANNEL( 977 sc->sc_last_rx_status); 978 979 /* check if we should dump the data */ 980 if (!(sc->sc_active_out_ep & (1U << ep_no))) { 981 dwc_otg_common_rx_ack(sc); 982 goto repeat; 983 } 984 985 got_rx_status = 1; 986 } 987 988 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 989 if (!dwc_otg_xfer_do_fifo(xfer)) { 990 /* queue has been modified */ 991 goto repeat; 992 } 993 } 994 995 if (got_rx_status) { 996 if (sc->sc_last_rx_status == 0) 997 goto repeat; 998 999 /* disable RX FIFO level interrupt */ 1000 sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_RXFLVL; 1001 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 1002 } 1003 } 1004 1005 static void 1006 dwc_otg_vbus_interrupt(struct dwc_otg_softc *sc, uint8_t is_on) 1007 { 1008 DPRINTFN(5, "vbus = %u\n", is_on); 1009 1010 if (is_on) { 1011 if (!sc->sc_flags.status_vbus) { 1012 sc->sc_flags.status_vbus = 1; 1013 1014 /* complete root HUB interrupt endpoint */ 1015 1016 dwc_otg_root_intr(sc); 1017 } 1018 } else { 1019 if (sc->sc_flags.status_vbus) { 1020 sc->sc_flags.status_vbus = 0; 1021 sc->sc_flags.status_bus_reset = 0; 1022 sc->sc_flags.status_suspend = 0; 1023 sc->sc_flags.change_suspend = 0; 1024 sc->sc_flags.change_connect = 1; 1025 1026 /* complete root HUB interrupt endpoint */ 1027 1028 dwc_otg_root_intr(sc); 1029 } 1030 } 1031 } 1032 1033 void 1034 dwc_otg_interrupt(struct dwc_otg_softc *sc) 1035 { 1036 uint32_t status; 1037 1038 USB_BUS_LOCK(&sc->sc_bus); 1039 1040 /* read and clear interrupt status */ 1041 status = DWC_OTG_READ_4(sc, DWC_OTG_REG_GINTSTS); 1042 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTSTS, status); 1043 1044 DPRINTFN(14, "GINTSTS=0x%08x\n", status); 1045 1046 if (status & DWC_OTG_MSK_GINT_USB_RESET) { 1047 1048 /* set correct state */ 1049 sc->sc_flags.status_bus_reset = 0; 1050 sc->sc_flags.status_suspend = 0; 1051 sc->sc_flags.change_suspend = 0; 1052 sc->sc_flags.change_connect = 1; 1053 1054 /* complete root HUB interrupt endpoint */ 1055 dwc_otg_root_intr(sc); 1056 } 1057 1058 /* check for any bus state change interrupts */ 1059 if (status & DWC_OTG_MSK_GINT_ENUM_DONE) { 1060 1061 uint32_t temp; 1062 1063 DPRINTFN(5, "end of reset\n"); 1064 1065 /* set correct state */ 1066 sc->sc_flags.status_bus_reset = 1; 1067 sc->sc_flags.status_suspend = 0; 1068 sc->sc_flags.change_suspend = 0; 1069 sc->sc_flags.change_connect = 1; 1070 1071 /* reset FIFOs */ 1072 dwc_otg_init_fifo(sc); 1073 1074 /* reset function address */ 1075 dwc_otg_set_address(sc, 0); 1076 1077 /* reset active endpoints */ 1078 sc->sc_active_out_ep = 1; 1079 1080 /* figure out enumeration speed */ 1081 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DSTS); 1082 if (DWC_OTG_MSK_DSTS_GET_ENUM_SPEED(temp) == 1083 DWC_OTG_MSK_DSTS_ENUM_SPEED_HI) 1084 sc->sc_flags.status_high_speed = 1; 1085 else 1086 sc->sc_flags.status_high_speed = 0; 1087 1088 /* disable resume interrupt and enable suspend interrupt */ 1089 1090 sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_WKUPINT; 1091 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_USB_SUSPEND; 1092 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 1093 1094 /* complete root HUB interrupt endpoint */ 1095 dwc_otg_root_intr(sc); 1096 } 1097 /* 1098 * If resume and suspend is set at the same time we interpret 1099 * that like RESUME. Resume is set when there is at least 3 1100 * milliseconds of inactivity on the USB BUS. 1101 */ 1102 if (status & DWC_OTG_MSK_GINT_WKUPINT) { 1103 1104 DPRINTFN(5, "resume interrupt\n"); 1105 1106 dwc_otg_resume_irq(sc); 1107 1108 } else if (status & DWC_OTG_MSK_GINT_USB_SUSPEND) { 1109 1110 DPRINTFN(5, "suspend interrupt\n"); 1111 1112 if (!sc->sc_flags.status_suspend) { 1113 /* update status bits */ 1114 sc->sc_flags.status_suspend = 1; 1115 sc->sc_flags.change_suspend = 1; 1116 1117 /* 1118 * Disable suspend interrupt and enable resume 1119 * interrupt: 1120 */ 1121 sc->sc_irq_mask &= ~DWC_OTG_MSK_GINT_USB_SUSPEND; 1122 sc->sc_irq_mask |= DWC_OTG_MSK_GINT_WKUPINT; 1123 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 1124 1125 /* complete root HUB interrupt endpoint */ 1126 dwc_otg_root_intr(sc); 1127 } 1128 } 1129 /* check VBUS */ 1130 if (status & (DWC_OTG_MSK_GINT_USB_SUSPEND | 1131 DWC_OTG_MSK_GINT_USB_RESET | 1132 DWC_OTG_MSK_GINT_SESSREQINT)) { 1133 uint32_t temp; 1134 1135 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GOTGCTL); 1136 1137 DPRINTFN(5, "GOTGCTL=0x%08x\n", temp); 1138 1139 dwc_otg_vbus_interrupt(sc, 1140 (temp & DWC_OTG_MSK_GOTGCTL_BSESS_VALID) ? 1 : 0); 1141 } 1142 1143 /* clear all IN endpoint interrupts */ 1144 if (status & DWC_OTG_MSK_GINT_INEP) { 1145 uint32_t temp; 1146 uint8_t x; 1147 1148 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 1149 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPINT(x)); 1150 if (temp & DWC_OTG_MSK_DIEP_XFER_COMPLETE) { 1151 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPINT(x), 1152 DWC_OTG_MSK_DIEP_XFER_COMPLETE); 1153 } 1154 } 1155 } 1156 1157 #if 0 1158 /* check if we should poll the FIFOs */ 1159 if (status & (DWC_OTG_MSK_GINT_RXFLVL | DWC_OTG_MSK_GINT_INEP)) 1160 #endif 1161 /* poll FIFO(s) */ 1162 dwc_otg_interrupt_poll(sc); 1163 1164 USB_BUS_UNLOCK(&sc->sc_bus); 1165 } 1166 1167 static void 1168 dwc_otg_setup_standard_chain_sub(struct dwc_otg_std_temp *temp) 1169 { 1170 struct dwc_otg_td *td; 1171 1172 /* get current Transfer Descriptor */ 1173 td = temp->td_next; 1174 temp->td = td; 1175 1176 /* prepare for next TD */ 1177 temp->td_next = td->obj_next; 1178 1179 /* fill out the Transfer Descriptor */ 1180 td->func = temp->func; 1181 td->pc = temp->pc; 1182 td->offset = temp->offset; 1183 td->remainder = temp->len; 1184 td->tx_bytes = 0; 1185 td->error = 0; 1186 td->npkt = 1; 1187 td->did_stall = temp->did_stall; 1188 td->short_pkt = temp->short_pkt; 1189 td->alt_next = temp->setup_alt_next; 1190 } 1191 1192 static void 1193 dwc_otg_setup_standard_chain(struct usb_xfer *xfer) 1194 { 1195 struct dwc_otg_std_temp temp; 1196 struct dwc_otg_td *td; 1197 uint32_t x; 1198 uint8_t need_sync; 1199 1200 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n", 1201 xfer->address, UE_GET_ADDR(xfer->endpointno), 1202 xfer->sumlen, usbd_get_speed(xfer->xroot->udev)); 1203 1204 temp.max_frame_size = xfer->max_frame_size; 1205 1206 td = xfer->td_start[0]; 1207 xfer->td_transfer_first = td; 1208 xfer->td_transfer_cache = td; 1209 1210 /* setup temp */ 1211 1212 temp.pc = NULL; 1213 temp.td = NULL; 1214 temp.td_next = xfer->td_start[0]; 1215 temp.offset = 0; 1216 temp.setup_alt_next = xfer->flags_int.short_frames_ok; 1217 temp.did_stall = !xfer->flags_int.control_stall; 1218 1219 /* check if we should prepend a setup message */ 1220 1221 if (xfer->flags_int.control_xfr) { 1222 if (xfer->flags_int.control_hdr) { 1223 1224 temp.func = &dwc_otg_setup_rx; 1225 temp.len = xfer->frlengths[0]; 1226 temp.pc = xfer->frbuffers + 0; 1227 temp.short_pkt = temp.len ? 1 : 0; 1228 1229 /* check for last frame */ 1230 if (xfer->nframes == 1) { 1231 /* no STATUS stage yet, SETUP is last */ 1232 if (xfer->flags_int.control_act) 1233 temp.setup_alt_next = 0; 1234 } 1235 1236 dwc_otg_setup_standard_chain_sub(&temp); 1237 } 1238 x = 1; 1239 } else { 1240 x = 0; 1241 } 1242 1243 if (x != xfer->nframes) { 1244 if (xfer->endpointno & UE_DIR_IN) { 1245 temp.func = &dwc_otg_data_tx; 1246 need_sync = 1; 1247 } else { 1248 temp.func = &dwc_otg_data_rx; 1249 need_sync = 0; 1250 } 1251 1252 /* setup "pc" pointer */ 1253 temp.pc = xfer->frbuffers + x; 1254 } else { 1255 need_sync = 0; 1256 } 1257 while (x != xfer->nframes) { 1258 1259 /* DATA0 / DATA1 message */ 1260 1261 temp.len = xfer->frlengths[x]; 1262 1263 x++; 1264 1265 if (x == xfer->nframes) { 1266 if (xfer->flags_int.control_xfr) { 1267 if (xfer->flags_int.control_act) { 1268 temp.setup_alt_next = 0; 1269 } 1270 } else { 1271 temp.setup_alt_next = 0; 1272 } 1273 } 1274 if (temp.len == 0) { 1275 1276 /* make sure that we send an USB packet */ 1277 1278 temp.short_pkt = 0; 1279 1280 } else { 1281 1282 /* regular data transfer */ 1283 1284 temp.short_pkt = (xfer->flags.force_short_xfer ? 0 : 1); 1285 } 1286 1287 dwc_otg_setup_standard_chain_sub(&temp); 1288 1289 if (xfer->flags_int.isochronous_xfr) { 1290 temp.offset += temp.len; 1291 } else { 1292 /* get next Page Cache pointer */ 1293 temp.pc = xfer->frbuffers + x; 1294 } 1295 } 1296 1297 if (xfer->flags_int.control_xfr) { 1298 1299 /* always setup a valid "pc" pointer for status and sync */ 1300 temp.pc = xfer->frbuffers + 0; 1301 temp.len = 0; 1302 temp.short_pkt = 0; 1303 temp.setup_alt_next = 0; 1304 1305 /* check if we need to sync */ 1306 if (need_sync) { 1307 /* we need a SYNC point after TX */ 1308 temp.func = &dwc_otg_data_tx_sync; 1309 dwc_otg_setup_standard_chain_sub(&temp); 1310 } 1311 1312 /* check if we should append a status stage */ 1313 if (!xfer->flags_int.control_act) { 1314 1315 /* 1316 * Send a DATA1 message and invert the current 1317 * endpoint direction. 1318 */ 1319 if (xfer->endpointno & UE_DIR_IN) { 1320 temp.func = &dwc_otg_data_rx; 1321 need_sync = 0; 1322 } else { 1323 temp.func = &dwc_otg_data_tx; 1324 need_sync = 1; 1325 } 1326 1327 dwc_otg_setup_standard_chain_sub(&temp); 1328 if (need_sync) { 1329 /* we need a SYNC point after TX */ 1330 temp.func = &dwc_otg_data_tx_sync; 1331 dwc_otg_setup_standard_chain_sub(&temp); 1332 } 1333 } 1334 } else { 1335 /* check if we need to sync */ 1336 if (need_sync) { 1337 1338 temp.pc = xfer->frbuffers + 0; 1339 temp.len = 0; 1340 temp.short_pkt = 0; 1341 temp.setup_alt_next = 0; 1342 1343 /* we need a SYNC point after TX */ 1344 temp.func = &dwc_otg_data_tx_sync; 1345 dwc_otg_setup_standard_chain_sub(&temp); 1346 } 1347 } 1348 1349 /* must have at least one frame! */ 1350 td = temp.td; 1351 xfer->td_transfer_last = td; 1352 } 1353 1354 static void 1355 dwc_otg_timeout(void *arg) 1356 { 1357 struct usb_xfer *xfer = arg; 1358 1359 DPRINTF("xfer=%p\n", xfer); 1360 1361 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1362 1363 /* transfer is transferred */ 1364 dwc_otg_device_done(xfer, USB_ERR_TIMEOUT); 1365 } 1366 1367 static void 1368 dwc_otg_start_standard_chain(struct usb_xfer *xfer) 1369 { 1370 DPRINTFN(9, "\n"); 1371 1372 /* poll one time - will turn on interrupts */ 1373 if (dwc_otg_xfer_do_fifo(xfer)) { 1374 1375 /* put transfer on interrupt queue */ 1376 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 1377 1378 /* start timeout, if any */ 1379 if (xfer->timeout != 0) { 1380 usbd_transfer_timeout_ms(xfer, 1381 &dwc_otg_timeout, xfer->timeout); 1382 } 1383 } 1384 } 1385 1386 static void 1387 dwc_otg_root_intr(struct dwc_otg_softc *sc) 1388 { 1389 DPRINTFN(9, "\n"); 1390 1391 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 1392 1393 /* set port bit */ 1394 sc->sc_hub_idata[0] = 0x02; /* we only have one port */ 1395 1396 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 1397 sizeof(sc->sc_hub_idata)); 1398 } 1399 1400 static usb_error_t 1401 dwc_otg_standard_done_sub(struct usb_xfer *xfer) 1402 { 1403 struct dwc_otg_td *td; 1404 uint32_t len; 1405 uint8_t error; 1406 1407 DPRINTFN(9, "\n"); 1408 1409 td = xfer->td_transfer_cache; 1410 1411 do { 1412 len = td->remainder; 1413 1414 if (xfer->aframes != xfer->nframes) { 1415 /* 1416 * Verify the length and subtract 1417 * the remainder from "frlengths[]": 1418 */ 1419 if (len > xfer->frlengths[xfer->aframes]) { 1420 td->error = 1; 1421 } else { 1422 xfer->frlengths[xfer->aframes] -= len; 1423 } 1424 } 1425 /* Check for transfer error */ 1426 if (td->error) { 1427 /* the transfer is finished */ 1428 error = 1; 1429 td = NULL; 1430 break; 1431 } 1432 /* Check for short transfer */ 1433 if (len > 0) { 1434 if (xfer->flags_int.short_frames_ok) { 1435 /* follow alt next */ 1436 if (td->alt_next) { 1437 td = td->obj_next; 1438 } else { 1439 td = NULL; 1440 } 1441 } else { 1442 /* the transfer is finished */ 1443 td = NULL; 1444 } 1445 error = 0; 1446 break; 1447 } 1448 td = td->obj_next; 1449 1450 /* this USB frame is complete */ 1451 error = 0; 1452 break; 1453 1454 } while (0); 1455 1456 /* update transfer cache */ 1457 1458 xfer->td_transfer_cache = td; 1459 1460 return (error ? 1461 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION); 1462 } 1463 1464 static void 1465 dwc_otg_standard_done(struct usb_xfer *xfer) 1466 { 1467 usb_error_t err = 0; 1468 1469 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 1470 xfer, xfer->endpoint); 1471 1472 /* reset scanner */ 1473 1474 xfer->td_transfer_cache = xfer->td_transfer_first; 1475 1476 if (xfer->flags_int.control_xfr) { 1477 1478 if (xfer->flags_int.control_hdr) { 1479 1480 err = dwc_otg_standard_done_sub(xfer); 1481 } 1482 xfer->aframes = 1; 1483 1484 if (xfer->td_transfer_cache == NULL) { 1485 goto done; 1486 } 1487 } 1488 while (xfer->aframes != xfer->nframes) { 1489 1490 err = dwc_otg_standard_done_sub(xfer); 1491 xfer->aframes++; 1492 1493 if (xfer->td_transfer_cache == NULL) { 1494 goto done; 1495 } 1496 } 1497 1498 if (xfer->flags_int.control_xfr && 1499 !xfer->flags_int.control_act) { 1500 1501 err = dwc_otg_standard_done_sub(xfer); 1502 } 1503 done: 1504 dwc_otg_device_done(xfer, err); 1505 } 1506 1507 /*------------------------------------------------------------------------* 1508 * dwc_otg_device_done 1509 * 1510 * NOTE: this function can be called more than one time on the 1511 * same USB transfer! 1512 *------------------------------------------------------------------------*/ 1513 static void 1514 dwc_otg_device_done(struct usb_xfer *xfer, usb_error_t error) 1515 { 1516 DPRINTFN(9, "xfer=%p, endpoint=%p, error=%d\n", 1517 xfer, xfer->endpoint, error); 1518 1519 if (xfer->flags_int.usb_mode == USB_MODE_DEVICE) { 1520 DPRINTFN(15, "disabled interrupts!\n"); 1521 } 1522 /* dequeue transfer and start next transfer */ 1523 usbd_transfer_done(xfer, error); 1524 } 1525 1526 static void 1527 dwc_otg_xfer_stall(struct usb_xfer *xfer) 1528 { 1529 dwc_otg_device_done(xfer, USB_ERR_STALLED); 1530 } 1531 1532 static void 1533 dwc_otg_set_stall(struct usb_device *udev, 1534 struct usb_endpoint *ep, uint8_t *did_stall) 1535 { 1536 struct dwc_otg_softc *sc; 1537 uint32_t temp; 1538 uint32_t reg; 1539 uint8_t ep_no; 1540 1541 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1542 1543 sc = DWC_OTG_BUS2SC(udev->bus); 1544 1545 /* get endpoint address */ 1546 ep_no = ep->edesc->bEndpointAddress; 1547 1548 DPRINTFN(5, "endpoint=0x%x\n", ep_no); 1549 1550 if (ep_no & UE_DIR_IN) { 1551 reg = DWC_OTG_REG_DIEPCTL(ep_no & UE_ADDR); 1552 temp = sc->sc_in_ctl[ep_no & UE_ADDR]; 1553 } else { 1554 reg = DWC_OTG_REG_DOEPCTL(ep_no & UE_ADDR); 1555 temp = sc->sc_out_ctl[ep_no & UE_ADDR]; 1556 } 1557 1558 /* disable and stall endpoint */ 1559 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_DISABLE); 1560 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_STALL); 1561 1562 /* clear active OUT ep */ 1563 if (!(ep_no & UE_DIR_IN)) { 1564 1565 sc->sc_active_out_ep &= ~(1U << (ep_no & UE_ADDR)); 1566 1567 if (sc->sc_last_rx_status != 0 && 1568 (ep_no & UE_ADDR) == DWC_OTG_MSK_GRXSTS_GET_CHANNEL( 1569 sc->sc_last_rx_status)) { 1570 /* dump data */ 1571 dwc_otg_common_rx_ack(sc); 1572 /* poll interrupt */ 1573 dwc_otg_interrupt_poll(sc); 1574 } 1575 } 1576 } 1577 1578 static void 1579 dwc_otg_clear_stall_sub(struct dwc_otg_softc *sc, uint32_t mps, 1580 uint8_t ep_no, uint8_t ep_type, uint8_t ep_dir) 1581 { 1582 uint32_t reg; 1583 uint32_t temp; 1584 1585 if (ep_type == UE_CONTROL) { 1586 /* clearing stall is not needed */ 1587 return; 1588 } 1589 1590 if (ep_dir) { 1591 reg = DWC_OTG_REG_DIEPCTL(ep_no); 1592 } else { 1593 reg = DWC_OTG_REG_DOEPCTL(ep_no); 1594 sc->sc_active_out_ep |= (1U << ep_no); 1595 } 1596 1597 /* round up and mask away the multiplier count */ 1598 mps = (mps + 3) & 0x7FC; 1599 1600 if (ep_type == UE_BULK) { 1601 temp = DWC_OTG_MSK_EP_SET_TYPE( 1602 DWC_OTG_MSK_EP_TYPE_BULK) | 1603 DWC_OTG_MSK_DIEPCTL_USB_AEP; 1604 } else if (ep_type == UE_INTERRUPT) { 1605 temp = DWC_OTG_MSK_EP_SET_TYPE( 1606 DWC_OTG_MSK_EP_TYPE_INTERRUPT) | 1607 DWC_OTG_MSK_DIEPCTL_USB_AEP; 1608 } else { 1609 temp = DWC_OTG_MSK_EP_SET_TYPE( 1610 DWC_OTG_MSK_EP_TYPE_ISOC) | 1611 DWC_OTG_MSK_DIEPCTL_USB_AEP; 1612 } 1613 1614 temp |= DWC_OTG_MSK_DIEPCTL_MPS(mps); 1615 temp |= DWC_OTG_MSK_DIEPCTL_FNUM(ep_no); 1616 1617 if (ep_dir) 1618 sc->sc_in_ctl[ep_no] = temp; 1619 else 1620 sc->sc_out_ctl[ep_no] = temp; 1621 1622 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_DISABLE); 1623 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DOEPCTL_SET_DATA0); 1624 DWC_OTG_WRITE_4(sc, reg, temp | DWC_OTG_MSK_DIEPCTL_SET_NAK); 1625 1626 /* we only reset the transmit FIFO */ 1627 if (ep_dir) { 1628 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 1629 DWC_OTG_MSK_GRSTCTL_TXFIFO(ep_no) | 1630 DWC_OTG_MSK_GRSTCTL_TXFFLUSH); 1631 1632 DWC_OTG_WRITE_4(sc, 1633 DWC_OTG_REG_DIEPTSIZ(ep_no), 0); 1634 } 1635 1636 /* poll interrupt */ 1637 dwc_otg_interrupt_poll(sc); 1638 } 1639 1640 static void 1641 dwc_otg_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 1642 { 1643 struct dwc_otg_softc *sc; 1644 struct usb_endpoint_descriptor *ed; 1645 1646 DPRINTFN(5, "endpoint=%p\n", ep); 1647 1648 USB_BUS_LOCK_ASSERT(udev->bus, MA_OWNED); 1649 1650 /* check mode */ 1651 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 1652 /* not supported */ 1653 return; 1654 } 1655 /* get softc */ 1656 sc = DWC_OTG_BUS2SC(udev->bus); 1657 1658 /* get endpoint descriptor */ 1659 ed = ep->edesc; 1660 1661 /* reset endpoint */ 1662 dwc_otg_clear_stall_sub(sc, 1663 UGETW(ed->wMaxPacketSize), 1664 (ed->bEndpointAddress & UE_ADDR), 1665 (ed->bmAttributes & UE_XFERTYPE), 1666 (ed->bEndpointAddress & (UE_DIR_IN | UE_DIR_OUT))); 1667 } 1668 1669 static void 1670 dwc_otg_device_state_change(struct usb_device *udev) 1671 { 1672 struct dwc_otg_softc *sc; 1673 uint8_t x; 1674 1675 /* get softc */ 1676 sc = DWC_OTG_BUS2SC(udev->bus); 1677 1678 /* deactivate all other endpoint but the control endpoint */ 1679 if (udev->state == USB_STATE_CONFIGURED || 1680 udev->state == USB_STATE_ADDRESSED) { 1681 1682 USB_BUS_LOCK(&sc->sc_bus); 1683 1684 for (x = 1; x != sc->sc_dev_ep_max; x++) { 1685 1686 if (x < sc->sc_dev_in_ep_max) { 1687 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(x), 1688 DWC_OTG_MSK_DIEPCTL_DISABLE); 1689 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPCTL(x), 0); 1690 } 1691 1692 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(x), 1693 DWC_OTG_MSK_DOEPCTL_DISABLE); 1694 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPCTL(x), 0); 1695 } 1696 USB_BUS_UNLOCK(&sc->sc_bus); 1697 } 1698 } 1699 1700 int 1701 dwc_otg_init(struct dwc_otg_softc *sc) 1702 { 1703 uint32_t temp; 1704 1705 DPRINTF("start\n"); 1706 1707 /* set up the bus structure */ 1708 sc->sc_bus.usbrev = USB_REV_2_0; 1709 sc->sc_bus.methods = &dwc_otg_bus_methods; 1710 1711 /* reset active endpoints */ 1712 sc->sc_active_out_ep = 1; 1713 1714 USB_BUS_LOCK(&sc->sc_bus); 1715 1716 /* turn on clocks */ 1717 dwc_otg_clocks_on(sc); 1718 1719 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GSNPSID); 1720 DPRINTF("Version = 0x%08x\n", temp); 1721 1722 /* disconnect */ 1723 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, 1724 DWC_OTG_MSK_DCTL_SOFT_DISC); 1725 1726 /* wait for host to detect disconnect */ 1727 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 32); 1728 1729 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GRSTCTL, 1730 DWC_OTG_MSK_GRSTCTL_CSFTRST); 1731 1732 /* wait a little bit for block to reset */ 1733 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 128); 1734 1735 /* select HSIC or non-HSIC mode */ 1736 if (DWC_OTG_USE_HSIC) { 1737 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GUSBCFG, 1738 DWC_OTG_MSK_GUSBCFG_PHY_INTF | 1739 DWC_OTG_MSK_GUSBCFG_TRD_TIM(5)); 1740 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GOTGCTL, 1741 0x000000EC); 1742 1743 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GLPMCFG); 1744 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG, 1745 temp & ~DWC_OTG_MSK_GLPMCFG_HSIC_CONN); 1746 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG, 1747 temp | DWC_OTG_MSK_GLPMCFG_HSIC_CONN); 1748 } else { 1749 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GUSBCFG, 1750 DWC_OTG_MSK_GUSBCFG_ULPI_UMTI_SEL | 1751 DWC_OTG_MSK_GUSBCFG_TRD_TIM(5)); 1752 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GOTGCTL, 0); 1753 1754 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GLPMCFG); 1755 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GLPMCFG, 1756 temp & ~DWC_OTG_MSK_GLPMCFG_HSIC_CONN); 1757 } 1758 1759 /* clear global nak */ 1760 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, 1761 DWC_OTG_MSK_DCTL_CGOUT_NAK | 1762 DWC_OTG_MSK_DCTL_CGNPIN_NAK); 1763 1764 /* enable USB port */ 1765 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_PCGCCTL, 0); 1766 1767 /* pull up D+ */ 1768 dwc_otg_pull_up(sc); 1769 1770 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG3); 1771 1772 sc->sc_fifo_size = 4 * DWC_OTG_MSK_GHWCFG3_GET_DFIFO(temp); 1773 1774 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG2); 1775 1776 sc->sc_dev_ep_max = DWC_OTG_MSK_GHWCFG2_NUM_DEV_EP(temp); 1777 1778 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG4); 1779 1780 sc->sc_dev_in_ep_max = DWC_OTG_MSK_GHWCFG4_NUM_IN_EPS(temp); 1781 1782 DPRINTF("Total FIFO size = %d bytes, Device EPs = %d/%d\n", 1783 sc->sc_fifo_size, sc->sc_dev_ep_max, sc->sc_dev_in_ep_max); 1784 1785 /* setup FIFO */ 1786 if (dwc_otg_init_fifo(sc)) 1787 return (EINVAL); 1788 1789 /* enable interrupts */ 1790 sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; 1791 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); 1792 1793 /* enable all endpoint interrupts */ 1794 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG2); 1795 if (temp & DWC_OTG_MSK_GHWCFG2_MPI) { 1796 uint8_t x; 1797 1798 DPRINTF("Multi Process Interrupts\n"); 1799 1800 for (x = 0; x != sc->sc_dev_in_ep_max; x++) { 1801 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPEACHMSK(x), 1802 DWC_OTG_MSK_DIEP_XFER_COMPLETE); 1803 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPEACHMSK(x), 0); 1804 } 1805 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DEACHINTMSK, 0xFFFF); 1806 } else { 1807 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPMSK, 1808 DWC_OTG_MSK_DIEP_XFER_COMPLETE); 1809 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPMSK, 0); 1810 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DAINTMSK, 0xFFFF); 1811 } 1812 1813 /* enable global IRQ */ 1814 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GAHBCFG, 1815 DWC_OTG_MSK_GAHBCFG_GLOBAL_IRQ); 1816 1817 /* turn off clocks */ 1818 dwc_otg_clocks_off(sc); 1819 1820 /* read initial VBUS state */ 1821 1822 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GOTGCTL); 1823 1824 DPRINTFN(5, "GOTCTL=0x%08x\n", temp); 1825 1826 dwc_otg_vbus_interrupt(sc, 1827 (temp & DWC_OTG_MSK_GOTGCTL_BSESS_VALID) ? 1 : 0); 1828 1829 USB_BUS_UNLOCK(&sc->sc_bus); 1830 1831 /* catch any lost interrupts */ 1832 1833 dwc_otg_do_poll(&sc->sc_bus); 1834 1835 return (0); /* success */ 1836 } 1837 1838 void 1839 dwc_otg_uninit(struct dwc_otg_softc *sc) 1840 { 1841 USB_BUS_LOCK(&sc->sc_bus); 1842 1843 /* set disconnect */ 1844 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DCTL, 1845 DWC_OTG_MSK_DCTL_SOFT_DISC); 1846 1847 /* turn off global IRQ */ 1848 DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GAHBCFG, 0); 1849 1850 sc->sc_flags.port_powered = 0; 1851 sc->sc_flags.status_vbus = 0; 1852 sc->sc_flags.status_bus_reset = 0; 1853 sc->sc_flags.status_suspend = 0; 1854 sc->sc_flags.change_suspend = 0; 1855 sc->sc_flags.change_connect = 1; 1856 1857 dwc_otg_pull_down(sc); 1858 dwc_otg_clocks_off(sc); 1859 1860 USB_BUS_UNLOCK(&sc->sc_bus); 1861 } 1862 1863 static void 1864 dwc_otg_suspend(struct dwc_otg_softc *sc) 1865 { 1866 return; 1867 } 1868 1869 static void 1870 dwc_otg_resume(struct dwc_otg_softc *sc) 1871 { 1872 return; 1873 } 1874 1875 static void 1876 dwc_otg_do_poll(struct usb_bus *bus) 1877 { 1878 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 1879 1880 USB_BUS_LOCK(&sc->sc_bus); 1881 dwc_otg_interrupt_poll(sc); 1882 USB_BUS_UNLOCK(&sc->sc_bus); 1883 } 1884 1885 /*------------------------------------------------------------------------* 1886 * at91dci bulk support 1887 * at91dci control support 1888 * at91dci interrupt support 1889 *------------------------------------------------------------------------*/ 1890 static void 1891 dwc_otg_device_non_isoc_open(struct usb_xfer *xfer) 1892 { 1893 return; 1894 } 1895 1896 static void 1897 dwc_otg_device_non_isoc_close(struct usb_xfer *xfer) 1898 { 1899 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 1900 } 1901 1902 static void 1903 dwc_otg_device_non_isoc_enter(struct usb_xfer *xfer) 1904 { 1905 return; 1906 } 1907 1908 static void 1909 dwc_otg_device_non_isoc_start(struct usb_xfer *xfer) 1910 { 1911 /* setup TDs */ 1912 dwc_otg_setup_standard_chain(xfer); 1913 dwc_otg_start_standard_chain(xfer); 1914 } 1915 1916 struct usb_pipe_methods dwc_otg_device_non_isoc_methods = 1917 { 1918 .open = dwc_otg_device_non_isoc_open, 1919 .close = dwc_otg_device_non_isoc_close, 1920 .enter = dwc_otg_device_non_isoc_enter, 1921 .start = dwc_otg_device_non_isoc_start, 1922 }; 1923 1924 /*------------------------------------------------------------------------* 1925 * at91dci full speed isochronous support 1926 *------------------------------------------------------------------------*/ 1927 static void 1928 dwc_otg_device_isoc_fs_open(struct usb_xfer *xfer) 1929 { 1930 return; 1931 } 1932 1933 static void 1934 dwc_otg_device_isoc_fs_close(struct usb_xfer *xfer) 1935 { 1936 dwc_otg_device_done(xfer, USB_ERR_CANCELLED); 1937 } 1938 1939 static void 1940 dwc_otg_device_isoc_fs_enter(struct usb_xfer *xfer) 1941 { 1942 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(xfer->xroot->bus); 1943 uint32_t temp; 1944 uint32_t nframes; 1945 1946 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n", 1947 xfer, xfer->endpoint->isoc_next, xfer->nframes); 1948 1949 temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DSTS); 1950 1951 /* get the current frame index */ 1952 1953 nframes = DWC_OTG_MSK_DSTS_GET_FNUM(temp); 1954 1955 if (sc->sc_flags.status_high_speed) 1956 nframes /= 8; 1957 1958 nframes &= DWC_OTG_FRAME_MASK; 1959 1960 /* 1961 * check if the frame index is within the window where the frames 1962 * will be inserted 1963 */ 1964 temp = (nframes - xfer->endpoint->isoc_next) & DWC_OTG_FRAME_MASK; 1965 1966 if ((xfer->endpoint->is_synced == 0) || 1967 (temp < xfer->nframes)) { 1968 /* 1969 * If there is data underflow or the pipe queue is 1970 * empty we schedule the transfer a few frames ahead 1971 * of the current frame position. Else two isochronous 1972 * transfers might overlap. 1973 */ 1974 xfer->endpoint->isoc_next = (nframes + 3) & DWC_OTG_FRAME_MASK; 1975 xfer->endpoint->is_synced = 1; 1976 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1977 } 1978 /* 1979 * compute how many milliseconds the insertion is ahead of the 1980 * current frame position: 1981 */ 1982 temp = (xfer->endpoint->isoc_next - nframes) & DWC_OTG_FRAME_MASK; 1983 1984 /* 1985 * pre-compute when the isochronous transfer will be finished: 1986 */ 1987 xfer->isoc_time_complete = 1988 usb_isoc_time_expand(&sc->sc_bus, nframes) + temp + 1989 xfer->nframes; 1990 1991 /* compute frame number for next insertion */ 1992 xfer->endpoint->isoc_next += xfer->nframes; 1993 1994 /* setup TDs */ 1995 dwc_otg_setup_standard_chain(xfer); 1996 } 1997 1998 static void 1999 dwc_otg_device_isoc_fs_start(struct usb_xfer *xfer) 2000 { 2001 /* start TD chain */ 2002 dwc_otg_start_standard_chain(xfer); 2003 } 2004 2005 struct usb_pipe_methods dwc_otg_device_isoc_fs_methods = 2006 { 2007 .open = dwc_otg_device_isoc_fs_open, 2008 .close = dwc_otg_device_isoc_fs_close, 2009 .enter = dwc_otg_device_isoc_fs_enter, 2010 .start = dwc_otg_device_isoc_fs_start, 2011 }; 2012 2013 /*------------------------------------------------------------------------* 2014 * at91dci root control support 2015 *------------------------------------------------------------------------* 2016 * Simulate a hardware HUB by handling all the necessary requests. 2017 *------------------------------------------------------------------------*/ 2018 2019 static const struct usb_device_descriptor dwc_otg_devd = { 2020 .bLength = sizeof(struct usb_device_descriptor), 2021 .bDescriptorType = UDESC_DEVICE, 2022 .bcdUSB = {0x00, 0x02}, 2023 .bDeviceClass = UDCLASS_HUB, 2024 .bDeviceSubClass = UDSUBCLASS_HUB, 2025 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2026 .bMaxPacketSize = 64, 2027 .bcdDevice = {0x00, 0x01}, 2028 .iManufacturer = 1, 2029 .iProduct = 2, 2030 .bNumConfigurations = 1, 2031 }; 2032 2033 static const struct dwc_otg_config_desc dwc_otg_confd = { 2034 .confd = { 2035 .bLength = sizeof(struct usb_config_descriptor), 2036 .bDescriptorType = UDESC_CONFIG, 2037 .wTotalLength[0] = sizeof(dwc_otg_confd), 2038 .bNumInterface = 1, 2039 .bConfigurationValue = 1, 2040 .iConfiguration = 0, 2041 .bmAttributes = UC_SELF_POWERED, 2042 .bMaxPower = 0, 2043 }, 2044 .ifcd = { 2045 .bLength = sizeof(struct usb_interface_descriptor), 2046 .bDescriptorType = UDESC_INTERFACE, 2047 .bNumEndpoints = 1, 2048 .bInterfaceClass = UICLASS_HUB, 2049 .bInterfaceSubClass = UISUBCLASS_HUB, 2050 .bInterfaceProtocol = 0, 2051 }, 2052 .endpd = { 2053 .bLength = sizeof(struct usb_endpoint_descriptor), 2054 .bDescriptorType = UDESC_ENDPOINT, 2055 .bEndpointAddress = (UE_DIR_IN | DWC_OTG_INTR_ENDPT), 2056 .bmAttributes = UE_INTERRUPT, 2057 .wMaxPacketSize[0] = 8, 2058 .bInterval = 255, 2059 }, 2060 }; 2061 2062 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2063 2064 static const struct usb_hub_descriptor_min dwc_otg_hubd = { 2065 .bDescLength = sizeof(dwc_otg_hubd), 2066 .bDescriptorType = UDESC_HUB, 2067 .bNbrPorts = 1, 2068 HSETW(.wHubCharacteristics, (UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL)), 2069 .bPwrOn2PwrGood = 50, 2070 .bHubContrCurrent = 0, 2071 .DeviceRemovable = {0}, /* port is removable */ 2072 }; 2073 2074 #define STRING_LANG \ 2075 0x09, 0x04, /* American English */ 2076 2077 #define STRING_VENDOR \ 2078 'D', 0, 'W', 0, 'C', 0, 'O', 0, 'T', 0, 'G', 0 2079 2080 #define STRING_PRODUCT \ 2081 'D', 0, 'C', 0, 'I', 0, ' ', 0, 'R', 0, \ 2082 'o', 0, 'o', 0, 't', 0, ' ', 0, 'H', 0, \ 2083 'U', 0, 'B', 0, 2084 2085 USB_MAKE_STRING_DESC(STRING_LANG, dwc_otg_langtab); 2086 USB_MAKE_STRING_DESC(STRING_VENDOR, dwc_otg_vendor); 2087 USB_MAKE_STRING_DESC(STRING_PRODUCT, dwc_otg_product); 2088 2089 static usb_error_t 2090 dwc_otg_roothub_exec(struct usb_device *udev, 2091 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2092 { 2093 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 2094 const void *ptr; 2095 uint16_t len; 2096 uint16_t value; 2097 uint16_t index; 2098 usb_error_t err; 2099 2100 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2101 2102 /* buffer reset */ 2103 ptr = (const void *)&sc->sc_hub_temp; 2104 len = 0; 2105 err = 0; 2106 2107 value = UGETW(req->wValue); 2108 index = UGETW(req->wIndex); 2109 2110 /* demultiplex the control request */ 2111 2112 switch (req->bmRequestType) { 2113 case UT_READ_DEVICE: 2114 switch (req->bRequest) { 2115 case UR_GET_DESCRIPTOR: 2116 goto tr_handle_get_descriptor; 2117 case UR_GET_CONFIG: 2118 goto tr_handle_get_config; 2119 case UR_GET_STATUS: 2120 goto tr_handle_get_status; 2121 default: 2122 goto tr_stalled; 2123 } 2124 break; 2125 2126 case UT_WRITE_DEVICE: 2127 switch (req->bRequest) { 2128 case UR_SET_ADDRESS: 2129 goto tr_handle_set_address; 2130 case UR_SET_CONFIG: 2131 goto tr_handle_set_config; 2132 case UR_CLEAR_FEATURE: 2133 goto tr_valid; /* nop */ 2134 case UR_SET_DESCRIPTOR: 2135 goto tr_valid; /* nop */ 2136 case UR_SET_FEATURE: 2137 default: 2138 goto tr_stalled; 2139 } 2140 break; 2141 2142 case UT_WRITE_ENDPOINT: 2143 switch (req->bRequest) { 2144 case UR_CLEAR_FEATURE: 2145 switch (UGETW(req->wValue)) { 2146 case UF_ENDPOINT_HALT: 2147 goto tr_handle_clear_halt; 2148 case UF_DEVICE_REMOTE_WAKEUP: 2149 goto tr_handle_clear_wakeup; 2150 default: 2151 goto tr_stalled; 2152 } 2153 break; 2154 case UR_SET_FEATURE: 2155 switch (UGETW(req->wValue)) { 2156 case UF_ENDPOINT_HALT: 2157 goto tr_handle_set_halt; 2158 case UF_DEVICE_REMOTE_WAKEUP: 2159 goto tr_handle_set_wakeup; 2160 default: 2161 goto tr_stalled; 2162 } 2163 break; 2164 case UR_SYNCH_FRAME: 2165 goto tr_valid; /* nop */ 2166 default: 2167 goto tr_stalled; 2168 } 2169 break; 2170 2171 case UT_READ_ENDPOINT: 2172 switch (req->bRequest) { 2173 case UR_GET_STATUS: 2174 goto tr_handle_get_ep_status; 2175 default: 2176 goto tr_stalled; 2177 } 2178 break; 2179 2180 case UT_WRITE_INTERFACE: 2181 switch (req->bRequest) { 2182 case UR_SET_INTERFACE: 2183 goto tr_handle_set_interface; 2184 case UR_CLEAR_FEATURE: 2185 goto tr_valid; /* nop */ 2186 case UR_SET_FEATURE: 2187 default: 2188 goto tr_stalled; 2189 } 2190 break; 2191 2192 case UT_READ_INTERFACE: 2193 switch (req->bRequest) { 2194 case UR_GET_INTERFACE: 2195 goto tr_handle_get_interface; 2196 case UR_GET_STATUS: 2197 goto tr_handle_get_iface_status; 2198 default: 2199 goto tr_stalled; 2200 } 2201 break; 2202 2203 case UT_WRITE_CLASS_INTERFACE: 2204 case UT_WRITE_VENDOR_INTERFACE: 2205 /* XXX forward */ 2206 break; 2207 2208 case UT_READ_CLASS_INTERFACE: 2209 case UT_READ_VENDOR_INTERFACE: 2210 /* XXX forward */ 2211 break; 2212 2213 case UT_WRITE_CLASS_DEVICE: 2214 switch (req->bRequest) { 2215 case UR_CLEAR_FEATURE: 2216 goto tr_valid; 2217 case UR_SET_DESCRIPTOR: 2218 case UR_SET_FEATURE: 2219 break; 2220 default: 2221 goto tr_stalled; 2222 } 2223 break; 2224 2225 case UT_WRITE_CLASS_OTHER: 2226 switch (req->bRequest) { 2227 case UR_CLEAR_FEATURE: 2228 goto tr_handle_clear_port_feature; 2229 case UR_SET_FEATURE: 2230 goto tr_handle_set_port_feature; 2231 case UR_CLEAR_TT_BUFFER: 2232 case UR_RESET_TT: 2233 case UR_STOP_TT: 2234 goto tr_valid; 2235 2236 default: 2237 goto tr_stalled; 2238 } 2239 break; 2240 2241 case UT_READ_CLASS_OTHER: 2242 switch (req->bRequest) { 2243 case UR_GET_TT_STATE: 2244 goto tr_handle_get_tt_state; 2245 case UR_GET_STATUS: 2246 goto tr_handle_get_port_status; 2247 default: 2248 goto tr_stalled; 2249 } 2250 break; 2251 2252 case UT_READ_CLASS_DEVICE: 2253 switch (req->bRequest) { 2254 case UR_GET_DESCRIPTOR: 2255 goto tr_handle_get_class_descriptor; 2256 case UR_GET_STATUS: 2257 goto tr_handle_get_class_status; 2258 2259 default: 2260 goto tr_stalled; 2261 } 2262 break; 2263 default: 2264 goto tr_stalled; 2265 } 2266 goto tr_valid; 2267 2268 tr_handle_get_descriptor: 2269 switch (value >> 8) { 2270 case UDESC_DEVICE: 2271 if (value & 0xff) { 2272 goto tr_stalled; 2273 } 2274 len = sizeof(dwc_otg_devd); 2275 ptr = (const void *)&dwc_otg_devd; 2276 goto tr_valid; 2277 case UDESC_CONFIG: 2278 if (value & 0xff) { 2279 goto tr_stalled; 2280 } 2281 len = sizeof(dwc_otg_confd); 2282 ptr = (const void *)&dwc_otg_confd; 2283 goto tr_valid; 2284 case UDESC_STRING: 2285 switch (value & 0xff) { 2286 case 0: /* Language table */ 2287 len = sizeof(dwc_otg_langtab); 2288 ptr = (const void *)&dwc_otg_langtab; 2289 goto tr_valid; 2290 2291 case 1: /* Vendor */ 2292 len = sizeof(dwc_otg_vendor); 2293 ptr = (const void *)&dwc_otg_vendor; 2294 goto tr_valid; 2295 2296 case 2: /* Product */ 2297 len = sizeof(dwc_otg_product); 2298 ptr = (const void *)&dwc_otg_product; 2299 goto tr_valid; 2300 default: 2301 break; 2302 } 2303 break; 2304 default: 2305 goto tr_stalled; 2306 } 2307 goto tr_stalled; 2308 2309 tr_handle_get_config: 2310 len = 1; 2311 sc->sc_hub_temp.wValue[0] = sc->sc_conf; 2312 goto tr_valid; 2313 2314 tr_handle_get_status: 2315 len = 2; 2316 USETW(sc->sc_hub_temp.wValue, UDS_SELF_POWERED); 2317 goto tr_valid; 2318 2319 tr_handle_set_address: 2320 if (value & 0xFF00) { 2321 goto tr_stalled; 2322 } 2323 sc->sc_rt_addr = value; 2324 goto tr_valid; 2325 2326 tr_handle_set_config: 2327 if (value >= 2) { 2328 goto tr_stalled; 2329 } 2330 sc->sc_conf = value; 2331 goto tr_valid; 2332 2333 tr_handle_get_interface: 2334 len = 1; 2335 sc->sc_hub_temp.wValue[0] = 0; 2336 goto tr_valid; 2337 2338 tr_handle_get_tt_state: 2339 tr_handle_get_class_status: 2340 tr_handle_get_iface_status: 2341 tr_handle_get_ep_status: 2342 len = 2; 2343 USETW(sc->sc_hub_temp.wValue, 0); 2344 goto tr_valid; 2345 2346 tr_handle_set_halt: 2347 tr_handle_set_interface: 2348 tr_handle_set_wakeup: 2349 tr_handle_clear_wakeup: 2350 tr_handle_clear_halt: 2351 goto tr_valid; 2352 2353 tr_handle_clear_port_feature: 2354 if (index != 1) { 2355 goto tr_stalled; 2356 } 2357 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE on port %d\n", index); 2358 2359 switch (value) { 2360 case UHF_PORT_SUSPEND: 2361 dwc_otg_wakeup_peer(sc); 2362 break; 2363 2364 case UHF_PORT_ENABLE: 2365 sc->sc_flags.port_enabled = 0; 2366 break; 2367 2368 case UHF_PORT_TEST: 2369 case UHF_PORT_INDICATOR: 2370 case UHF_C_PORT_ENABLE: 2371 case UHF_C_PORT_OVER_CURRENT: 2372 case UHF_C_PORT_RESET: 2373 /* nops */ 2374 break; 2375 case UHF_PORT_POWER: 2376 sc->sc_flags.port_powered = 0; 2377 dwc_otg_pull_down(sc); 2378 dwc_otg_clocks_off(sc); 2379 break; 2380 case UHF_C_PORT_CONNECTION: 2381 /* clear connect change flag */ 2382 sc->sc_flags.change_connect = 0; 2383 2384 if (!sc->sc_flags.status_bus_reset) { 2385 /* we are not connected */ 2386 break; 2387 } 2388 break; 2389 case UHF_C_PORT_SUSPEND: 2390 sc->sc_flags.change_suspend = 0; 2391 break; 2392 default: 2393 err = USB_ERR_IOERROR; 2394 goto done; 2395 } 2396 goto tr_valid; 2397 2398 tr_handle_set_port_feature: 2399 if (index != 1) { 2400 goto tr_stalled; 2401 } 2402 DPRINTFN(9, "UR_SET_PORT_FEATURE\n"); 2403 2404 switch (value) { 2405 case UHF_PORT_ENABLE: 2406 sc->sc_flags.port_enabled = 1; 2407 break; 2408 case UHF_PORT_SUSPEND: 2409 case UHF_PORT_RESET: 2410 case UHF_PORT_TEST: 2411 case UHF_PORT_INDICATOR: 2412 /* nops */ 2413 break; 2414 case UHF_PORT_POWER: 2415 sc->sc_flags.port_powered = 1; 2416 break; 2417 default: 2418 err = USB_ERR_IOERROR; 2419 goto done; 2420 } 2421 goto tr_valid; 2422 2423 tr_handle_get_port_status: 2424 2425 DPRINTFN(9, "UR_GET_PORT_STATUS\n"); 2426 2427 if (index != 1) { 2428 goto tr_stalled; 2429 } 2430 if (sc->sc_flags.status_vbus) { 2431 dwc_otg_clocks_on(sc); 2432 } else { 2433 dwc_otg_clocks_off(sc); 2434 } 2435 2436 /* Select Device Side Mode */ 2437 2438 value = UPS_PORT_MODE_DEVICE; 2439 2440 if (sc->sc_flags.status_high_speed) { 2441 value |= UPS_HIGH_SPEED; 2442 } 2443 if (sc->sc_flags.port_powered) { 2444 value |= UPS_PORT_POWER; 2445 } 2446 if (sc->sc_flags.port_enabled) { 2447 value |= UPS_PORT_ENABLED; 2448 } 2449 if (sc->sc_flags.status_vbus && 2450 sc->sc_flags.status_bus_reset) { 2451 value |= UPS_CURRENT_CONNECT_STATUS; 2452 } 2453 if (sc->sc_flags.status_suspend) { 2454 value |= UPS_SUSPEND; 2455 } 2456 USETW(sc->sc_hub_temp.ps.wPortStatus, value); 2457 2458 value = 0; 2459 2460 if (sc->sc_flags.change_connect) { 2461 value |= UPS_C_CONNECT_STATUS; 2462 } 2463 if (sc->sc_flags.change_suspend) { 2464 value |= UPS_C_SUSPEND; 2465 } 2466 USETW(sc->sc_hub_temp.ps.wPortChange, value); 2467 len = sizeof(sc->sc_hub_temp.ps); 2468 goto tr_valid; 2469 2470 tr_handle_get_class_descriptor: 2471 if (value & 0xFF) { 2472 goto tr_stalled; 2473 } 2474 ptr = (const void *)&dwc_otg_hubd; 2475 len = sizeof(dwc_otg_hubd); 2476 goto tr_valid; 2477 2478 tr_stalled: 2479 err = USB_ERR_STALLED; 2480 tr_valid: 2481 done: 2482 *plength = len; 2483 *pptr = ptr; 2484 return (err); 2485 } 2486 2487 static void 2488 dwc_otg_xfer_setup(struct usb_setup_params *parm) 2489 { 2490 const struct usb_hw_ep_profile *pf; 2491 struct usb_xfer *xfer; 2492 void *last_obj; 2493 uint32_t ntd; 2494 uint32_t n; 2495 uint8_t ep_no; 2496 2497 xfer = parm->curr_xfer; 2498 2499 /* 2500 * NOTE: This driver does not use any of the parameters that 2501 * are computed from the following values. Just set some 2502 * reasonable dummies: 2503 */ 2504 parm->hc_max_packet_size = 0x500; 2505 parm->hc_max_packet_count = 1; 2506 parm->hc_max_frame_size = 0x500; 2507 2508 usbd_transfer_setup_sub(parm); 2509 2510 /* 2511 * compute maximum number of TDs 2512 */ 2513 if ((xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) { 2514 2515 ntd = xfer->nframes + 1 /* STATUS */ + 1 /* SYNC 1 */ 2516 + 1 /* SYNC 2 */ ; 2517 } else { 2518 2519 ntd = xfer->nframes + 1 /* SYNC */ ; 2520 } 2521 2522 /* 2523 * check if "usbd_transfer_setup_sub" set an error 2524 */ 2525 if (parm->err) 2526 return; 2527 2528 /* 2529 * allocate transfer descriptors 2530 */ 2531 last_obj = NULL; 2532 2533 /* 2534 * get profile stuff 2535 */ 2536 ep_no = xfer->endpointno & UE_ADDR; 2537 dwc_otg_get_hw_ep_profile(parm->udev, &pf, ep_no); 2538 2539 if (pf == NULL) { 2540 /* should not happen */ 2541 parm->err = USB_ERR_INVAL; 2542 return; 2543 } 2544 2545 /* align data */ 2546 parm->size[0] += ((-parm->size[0]) & (USB_HOST_ALIGN - 1)); 2547 2548 for (n = 0; n != ntd; n++) { 2549 2550 struct dwc_otg_td *td; 2551 2552 if (parm->buf) { 2553 2554 td = USB_ADD_BYTES(parm->buf, parm->size[0]); 2555 2556 /* init TD */ 2557 td->max_packet_size = xfer->max_packet_size; 2558 td->ep_no = ep_no; 2559 td->obj_next = last_obj; 2560 2561 last_obj = td; 2562 } 2563 parm->size[0] += sizeof(*td); 2564 } 2565 2566 xfer->td_start[0] = last_obj; 2567 } 2568 2569 static void 2570 dwc_otg_xfer_unsetup(struct usb_xfer *xfer) 2571 { 2572 return; 2573 } 2574 2575 static void 2576 dwc_otg_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 2577 struct usb_endpoint *ep) 2578 { 2579 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(udev->bus); 2580 2581 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d,%d)\n", 2582 ep, udev->address, 2583 edesc->bEndpointAddress, udev->flags.usb_mode, 2584 sc->sc_rt_addr, udev->device_index); 2585 2586 if (udev->device_index != sc->sc_rt_addr) { 2587 2588 if (udev->flags.usb_mode != USB_MODE_DEVICE) { 2589 /* not supported */ 2590 return; 2591 } 2592 if (udev->speed != USB_SPEED_FULL && 2593 udev->speed != USB_SPEED_HIGH) { 2594 /* not supported */ 2595 return; 2596 } 2597 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) 2598 ep->methods = &dwc_otg_device_isoc_fs_methods; 2599 else 2600 ep->methods = &dwc_otg_device_non_isoc_methods; 2601 } 2602 } 2603 2604 static void 2605 dwc_otg_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 2606 { 2607 struct dwc_otg_softc *sc = DWC_OTG_BUS2SC(bus); 2608 2609 switch (state) { 2610 case USB_HW_POWER_SUSPEND: 2611 dwc_otg_suspend(sc); 2612 break; 2613 case USB_HW_POWER_SHUTDOWN: 2614 dwc_otg_uninit(sc); 2615 break; 2616 case USB_HW_POWER_RESUME: 2617 dwc_otg_resume(sc); 2618 break; 2619 default: 2620 break; 2621 } 2622 } 2623 2624 struct usb_bus_methods dwc_otg_bus_methods = 2625 { 2626 .endpoint_init = &dwc_otg_ep_init, 2627 .xfer_setup = &dwc_otg_xfer_setup, 2628 .xfer_unsetup = &dwc_otg_xfer_unsetup, 2629 .get_hw_ep_profile = &dwc_otg_get_hw_ep_profile, 2630 .xfer_stall = &dwc_otg_xfer_stall, 2631 .set_stall = &dwc_otg_set_stall, 2632 .clear_stall = &dwc_otg_clear_stall, 2633 .roothub_exec = &dwc_otg_roothub_exec, 2634 .xfer_poll = &dwc_otg_do_poll, 2635 .device_state_change = &dwc_otg_device_state_change, 2636 .set_hw_power_sleep = &dwc_otg_set_hw_power_sleep, 2637 }; 2638