1 /*- 2 * Copyright (c) 2015-2016 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "efx.h" 35 #include "efx_impl.h" 36 37 38 #if EFSYS_OPT_MEDFORD 39 40 static __checkReturn efx_rc_t 41 medford_nic_get_required_pcie_bandwidth( 42 __in efx_nic_t *enp, 43 __out uint32_t *bandwidth_mbpsp) 44 { 45 uint32_t port_modes; 46 uint32_t current_mode; 47 uint32_t bandwidth; 48 efx_rc_t rc; 49 50 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, 51 ¤t_mode)) != 0) { 52 /* No port mode info available. */ 53 bandwidth = 0; 54 goto out; 55 } 56 57 if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode, 58 &bandwidth)) != 0) 59 goto fail1; 60 61 out: 62 *bandwidth_mbpsp = bandwidth; 63 64 return (0); 65 66 fail1: 67 EFSYS_PROBE1(fail1, efx_rc_t, rc); 68 69 return (rc); 70 } 71 72 __checkReturn efx_rc_t 73 medford_board_cfg( 74 __in efx_nic_t *enp) 75 { 76 efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); 77 efx_nic_cfg_t *encp = &(enp->en_nic_cfg); 78 uint8_t mac_addr[6] = { 0 }; 79 uint32_t board_type = 0; 80 ef10_link_state_t els; 81 efx_port_t *epp = &(enp->en_port); 82 uint32_t port; 83 uint32_t pf; 84 uint32_t vf; 85 uint32_t mask; 86 uint32_t sysclk, dpcpu_clk; 87 uint32_t base, nvec; 88 uint32_t end_padding; 89 uint32_t bandwidth; 90 efx_rc_t rc; 91 92 /* 93 * FIXME: Likely to be incomplete and incorrect. 94 * Parts of this should be shared with Huntington. 95 */ 96 97 /* Medford has a fixed 8Kbyte VI window size */ 98 EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192); 99 EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192); 100 EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192); 101 EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192); 102 EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192); 103 104 EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192); 105 encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K; 106 107 108 if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0) 109 goto fail1; 110 111 /* 112 * NOTE: The MCDI protocol numbers ports from zero. 113 * The common code MCDI interface numbers ports from one. 114 */ 115 emip->emi_port = port + 1; 116 117 if ((rc = ef10_external_port_mapping(enp, port, 118 &encp->enc_external_port)) != 0) 119 goto fail2; 120 121 /* 122 * Get PCIe function number from firmware (used for 123 * per-function privilege and dynamic config info). 124 * - PCIe PF: pf = PF number, vf = 0xffff. 125 * - PCIe VF: pf = parent PF, vf = VF number. 126 */ 127 if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0) 128 goto fail3; 129 130 encp->enc_pf = pf; 131 encp->enc_vf = vf; 132 133 /* MAC address for this function */ 134 if (EFX_PCI_FUNCTION_IS_PF(encp)) { 135 rc = efx_mcdi_get_mac_address_pf(enp, mac_addr); 136 #if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC 137 /* 138 * Disable static config checking for Medford NICs, ONLY 139 * for manufacturing test and setup at the factory, to 140 * allow the static config to be installed. 141 */ 142 #else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */ 143 if ((rc == 0) && (mac_addr[0] & 0x02)) { 144 /* 145 * If the static config does not include a global MAC 146 * address pool then the board may return a locally 147 * administered MAC address (this should only happen on 148 * incorrectly programmed boards). 149 */ 150 rc = EINVAL; 151 } 152 #endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */ 153 } else { 154 rc = efx_mcdi_get_mac_address_vf(enp, mac_addr); 155 } 156 if (rc != 0) 157 goto fail4; 158 159 EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr); 160 161 /* Board configuration */ 162 rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL); 163 if (rc != 0) { 164 /* Unprivileged functions may not be able to read board cfg */ 165 if (rc == EACCES) 166 board_type = 0; 167 else 168 goto fail5; 169 } 170 171 encp->enc_board_type = board_type; 172 encp->enc_clk_mult = 1; /* not used for Medford */ 173 174 /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */ 175 if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0) 176 goto fail6; 177 178 /* Obtain the default PHY advertised capabilities */ 179 if ((rc = ef10_phy_get_link(enp, &els)) != 0) 180 goto fail7; 181 epp->ep_default_adv_cap_mask = els.els_adv_cap_mask; 182 epp->ep_adv_cap_mask = els.els_adv_cap_mask; 183 184 /* 185 * Enable firmware workarounds for hardware errata. 186 * Expected responses are: 187 * - 0 (zero): 188 * Success: workaround enabled or disabled as requested. 189 * - MC_CMD_ERR_ENOSYS (reported as ENOTSUP): 190 * Firmware does not support the MC_CMD_WORKAROUND request. 191 * (assume that the workaround is not supported). 192 * - MC_CMD_ERR_ENOENT (reported as ENOENT): 193 * Firmware does not support the requested workaround. 194 * - MC_CMD_ERR_EPERM (reported as EACCES): 195 * Unprivileged function cannot enable/disable workarounds. 196 * 197 * See efx_mcdi_request_errcode() for MCDI error translations. 198 */ 199 200 201 if (EFX_PCI_FUNCTION_IS_VF(encp)) { 202 /* 203 * Interrupt testing does not work for VFs. See bug50084 and 204 * bug71432 comment 21. 205 */ 206 encp->enc_bug41750_workaround = B_TRUE; 207 } 208 209 /* Chained multicast is always enabled on Medford */ 210 encp->enc_bug26807_workaround = B_TRUE; 211 212 /* 213 * If the bug61265 workaround is enabled, then interrupt holdoff timers 214 * cannot be controlled by timer table writes, so MCDI must be used 215 * (timer table writes can still be used for wakeup timers). 216 */ 217 rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG61265, B_TRUE, 218 NULL); 219 if ((rc == 0) || (rc == EACCES)) 220 encp->enc_bug61265_workaround = B_TRUE; 221 else if ((rc == ENOTSUP) || (rc == ENOENT)) 222 encp->enc_bug61265_workaround = B_FALSE; 223 else 224 goto fail8; 225 226 /* Get clock frequencies (in MHz). */ 227 if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0) 228 goto fail9; 229 230 /* 231 * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for 232 * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units. 233 */ 234 encp->enc_evq_timer_quantum_ns = 1536000UL / dpcpu_clk; /* 1536 cycles */ 235 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns << 236 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000; 237 238 /* Check capabilities of running datapath firmware */ 239 if ((rc = ef10_get_datapath_caps(enp)) != 0) 240 goto fail10; 241 242 /* Alignment for receive packet DMA buffers */ 243 encp->enc_rx_buf_align_start = 1; 244 245 /* Get the RX DMA end padding alignment configuration */ 246 if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) { 247 if (rc != EACCES) 248 goto fail11; 249 250 /* Assume largest tail padding size supported by hardware */ 251 end_padding = 256; 252 } 253 encp->enc_rx_buf_align_end = end_padding; 254 255 /* Alignment for WPTR updates */ 256 encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN; 257 258 /* 259 * Maximum number of exclusive RSS contexts which can be allocated. The 260 * hardware supports 64, but 6 are reserved for shared contexts. They 261 * are a global resource so not all may be available. 262 */ 263 encp->enc_rx_scale_max_exclusive_contexts = 58; 264 265 encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); 266 /* No boundary crossing limits */ 267 encp->enc_tx_dma_desc_boundary = 0; 268 269 /* 270 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use 271 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available 272 * resources (allocated to this PCIe function), which is zero until 273 * after we have allocated VIs. 274 */ 275 encp->enc_evq_limit = 1024; 276 encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET; 277 encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET; 278 279 /* 280 * The maximum supported transmit queue size is 2048. TXQs with 4096 281 * descriptors are not supported as the top bit is used for vfifo 282 * stuffing. 283 */ 284 encp->enc_txq_max_ndescs = 2048; 285 286 encp->enc_buftbl_limit = 0xFFFFFFFF; 287 288 EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); 289 encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS; 290 encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE; 291 encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE; 292 293 /* 294 * Get the current privilege mask. Note that this may be modified 295 * dynamically, so this value is informational only. DO NOT use 296 * the privilege mask to check for sufficient privileges, as that 297 * can result in time-of-check/time-of-use bugs. 298 */ 299 if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0) 300 goto fail12; 301 encp->enc_privilege_mask = mask; 302 303 /* Get interrupt vector limits */ 304 if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) { 305 if (EFX_PCI_FUNCTION_IS_PF(encp)) 306 goto fail13; 307 308 /* Ignore error (cannot query vector limits from a VF). */ 309 base = 0; 310 nvec = 1024; 311 } 312 encp->enc_intr_vec_base = base; 313 encp->enc_intr_limit = nvec; 314 315 /* 316 * Maximum number of bytes into the frame the TCP header can start for 317 * firmware assisted TSO to work. 318 */ 319 encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; 320 321 /* 322 * Medford stores a single global copy of VPD, not per-PF as on 323 * Huntington. 324 */ 325 encp->enc_vpd_is_global = B_TRUE; 326 327 rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth); 328 if (rc != 0) 329 goto fail14; 330 encp->enc_required_pcie_bandwidth_mbps = bandwidth; 331 encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3; 332 333 return (0); 334 335 fail14: 336 EFSYS_PROBE(fail14); 337 fail13: 338 EFSYS_PROBE(fail13); 339 fail12: 340 EFSYS_PROBE(fail12); 341 fail11: 342 EFSYS_PROBE(fail11); 343 fail10: 344 EFSYS_PROBE(fail10); 345 fail9: 346 EFSYS_PROBE(fail9); 347 fail8: 348 EFSYS_PROBE(fail8); 349 fail7: 350 EFSYS_PROBE(fail7); 351 fail6: 352 EFSYS_PROBE(fail6); 353 fail5: 354 EFSYS_PROBE(fail5); 355 fail4: 356 EFSYS_PROBE(fail4); 357 fail3: 358 EFSYS_PROBE(fail3); 359 fail2: 360 EFSYS_PROBE(fail2); 361 fail1: 362 EFSYS_PROBE1(fail1, efx_rc_t, rc); 363 364 return (rc); 365 } 366 367 #endif /* EFSYS_OPT_MEDFORD */ 368