1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _SYS_EFX_IMPL_H 36 #define _SYS_EFX_IMPL_H 37 38 #include "efx.h" 39 #include "efx_regs.h" 40 #include "efx_regs_ef10.h" 41 42 /* FIXME: Add definition for driver generated software events */ 43 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV 44 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV 45 #endif 46 47 48 #if EFSYS_OPT_SIENA 49 #include "siena_impl.h" 50 #endif /* EFSYS_OPT_SIENA */ 51 52 #if EFSYS_OPT_HUNTINGTON 53 #include "hunt_impl.h" 54 #endif /* EFSYS_OPT_HUNTINGTON */ 55 56 #if EFSYS_OPT_MEDFORD 57 #include "medford_impl.h" 58 #endif /* EFSYS_OPT_MEDFORD */ 59 60 #if EFSYS_OPT_MEDFORD2 61 #include "medford2_impl.h" 62 #endif /* EFSYS_OPT_MEDFORD2 */ 63 64 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) 65 #include "ef10_impl.h" 66 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ 67 68 #ifdef __cplusplus 69 extern "C" { 70 #endif 71 72 #define EFX_MOD_MCDI 0x00000001 73 #define EFX_MOD_PROBE 0x00000002 74 #define EFX_MOD_NVRAM 0x00000004 75 #define EFX_MOD_VPD 0x00000008 76 #define EFX_MOD_NIC 0x00000010 77 #define EFX_MOD_INTR 0x00000020 78 #define EFX_MOD_EV 0x00000040 79 #define EFX_MOD_RX 0x00000080 80 #define EFX_MOD_TX 0x00000100 81 #define EFX_MOD_PORT 0x00000200 82 #define EFX_MOD_MON 0x00000400 83 #define EFX_MOD_FILTER 0x00001000 84 #define EFX_MOD_LIC 0x00002000 85 #define EFX_MOD_TUNNEL 0x00004000 86 87 #define EFX_RESET_PHY 0x00000001 88 #define EFX_RESET_RXQ_ERR 0x00000002 89 #define EFX_RESET_TXQ_ERR 0x00000004 90 91 typedef enum efx_mac_type_e { 92 EFX_MAC_INVALID = 0, 93 EFX_MAC_SIENA, 94 EFX_MAC_HUNTINGTON, 95 EFX_MAC_MEDFORD, 96 EFX_MAC_MEDFORD2, 97 EFX_MAC_NTYPES 98 } efx_mac_type_t; 99 100 typedef struct efx_ev_ops_s { 101 efx_rc_t (*eevo_init)(efx_nic_t *); 102 void (*eevo_fini)(efx_nic_t *); 103 efx_rc_t (*eevo_qcreate)(efx_nic_t *, unsigned int, 104 efsys_mem_t *, size_t, uint32_t, 105 uint32_t, uint32_t, efx_evq_t *); 106 void (*eevo_qdestroy)(efx_evq_t *); 107 efx_rc_t (*eevo_qprime)(efx_evq_t *, unsigned int); 108 void (*eevo_qpost)(efx_evq_t *, uint16_t); 109 efx_rc_t (*eevo_qmoderate)(efx_evq_t *, unsigned int); 110 #if EFSYS_OPT_QSTATS 111 void (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *); 112 #endif 113 } efx_ev_ops_t; 114 115 typedef struct efx_tx_ops_s { 116 efx_rc_t (*etxo_init)(efx_nic_t *); 117 void (*etxo_fini)(efx_nic_t *); 118 efx_rc_t (*etxo_qcreate)(efx_nic_t *, 119 unsigned int, unsigned int, 120 efsys_mem_t *, size_t, 121 uint32_t, uint16_t, 122 efx_evq_t *, efx_txq_t *, 123 unsigned int *); 124 void (*etxo_qdestroy)(efx_txq_t *); 125 efx_rc_t (*etxo_qpost)(efx_txq_t *, efx_buffer_t *, 126 unsigned int, unsigned int, 127 unsigned int *); 128 void (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int); 129 efx_rc_t (*etxo_qpace)(efx_txq_t *, unsigned int); 130 efx_rc_t (*etxo_qflush)(efx_txq_t *); 131 void (*etxo_qenable)(efx_txq_t *); 132 efx_rc_t (*etxo_qpio_enable)(efx_txq_t *); 133 void (*etxo_qpio_disable)(efx_txq_t *); 134 efx_rc_t (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t, 135 size_t); 136 efx_rc_t (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int, 137 unsigned int *); 138 efx_rc_t (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *, 139 unsigned int, unsigned int, 140 unsigned int *); 141 void (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t, 142 size_t, boolean_t, 143 efx_desc_t *); 144 void (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t, 145 uint32_t, uint8_t, 146 efx_desc_t *); 147 void (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t, 148 uint32_t, uint16_t, 149 efx_desc_t *, int); 150 void (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t, 151 efx_desc_t *); 152 void (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t, 153 efx_desc_t *); 154 #if EFSYS_OPT_QSTATS 155 void (*etxo_qstats_update)(efx_txq_t *, 156 efsys_stat_t *); 157 #endif 158 } efx_tx_ops_t; 159 160 typedef struct efx_rx_ops_s { 161 efx_rc_t (*erxo_init)(efx_nic_t *); 162 void (*erxo_fini)(efx_nic_t *); 163 #if EFSYS_OPT_RX_SCATTER 164 efx_rc_t (*erxo_scatter_enable)(efx_nic_t *, unsigned int); 165 #endif 166 #if EFSYS_OPT_RX_SCALE 167 efx_rc_t (*erxo_scale_context_alloc)(efx_nic_t *, 168 efx_rx_scale_context_type_t, 169 uint32_t, uint32_t *); 170 efx_rc_t (*erxo_scale_context_free)(efx_nic_t *, uint32_t); 171 efx_rc_t (*erxo_scale_mode_set)(efx_nic_t *, uint32_t, 172 efx_rx_hash_alg_t, 173 efx_rx_hash_type_t, boolean_t); 174 efx_rc_t (*erxo_scale_key_set)(efx_nic_t *, uint32_t, 175 uint8_t *, size_t); 176 efx_rc_t (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t, 177 unsigned int *, size_t); 178 uint32_t (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t, 179 uint8_t *); 180 #endif /* EFSYS_OPT_RX_SCALE */ 181 efx_rc_t (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *, 182 uint16_t *); 183 void (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t, 184 unsigned int, unsigned int, 185 unsigned int); 186 void (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *); 187 #if EFSYS_OPT_RX_PACKED_STREAM 188 void (*erxo_qpush_ps_credits)(efx_rxq_t *); 189 uint8_t * (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *, 190 uint32_t, uint32_t, 191 uint16_t *, uint32_t *, uint32_t *); 192 #endif 193 efx_rc_t (*erxo_qflush)(efx_rxq_t *); 194 void (*erxo_qenable)(efx_rxq_t *); 195 efx_rc_t (*erxo_qcreate)(efx_nic_t *enp, unsigned int, 196 unsigned int, efx_rxq_type_t, uint32_t, 197 efsys_mem_t *, size_t, uint32_t, 198 unsigned int, 199 efx_evq_t *, efx_rxq_t *); 200 void (*erxo_qdestroy)(efx_rxq_t *); 201 } efx_rx_ops_t; 202 203 typedef struct efx_mac_ops_s { 204 efx_rc_t (*emo_poll)(efx_nic_t *, efx_link_mode_t *); 205 efx_rc_t (*emo_up)(efx_nic_t *, boolean_t *); 206 efx_rc_t (*emo_addr_set)(efx_nic_t *); 207 efx_rc_t (*emo_pdu_set)(efx_nic_t *); 208 efx_rc_t (*emo_pdu_get)(efx_nic_t *, size_t *); 209 efx_rc_t (*emo_reconfigure)(efx_nic_t *); 210 efx_rc_t (*emo_multicast_list_set)(efx_nic_t *); 211 efx_rc_t (*emo_filter_default_rxq_set)(efx_nic_t *, 212 efx_rxq_t *, boolean_t); 213 void (*emo_filter_default_rxq_clear)(efx_nic_t *); 214 #if EFSYS_OPT_LOOPBACK 215 efx_rc_t (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t, 216 efx_loopback_type_t); 217 #endif /* EFSYS_OPT_LOOPBACK */ 218 #if EFSYS_OPT_MAC_STATS 219 efx_rc_t (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t); 220 efx_rc_t (*emo_stats_clear)(efx_nic_t *); 221 efx_rc_t (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *); 222 efx_rc_t (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *, 223 uint16_t, boolean_t); 224 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 225 efsys_stat_t *, uint32_t *); 226 #endif /* EFSYS_OPT_MAC_STATS */ 227 } efx_mac_ops_t; 228 229 typedef struct efx_phy_ops_s { 230 efx_rc_t (*epo_power)(efx_nic_t *, boolean_t); /* optional */ 231 efx_rc_t (*epo_reset)(efx_nic_t *); 232 efx_rc_t (*epo_reconfigure)(efx_nic_t *); 233 efx_rc_t (*epo_verify)(efx_nic_t *); 234 efx_rc_t (*epo_oui_get)(efx_nic_t *, uint32_t *); 235 #if EFSYS_OPT_PHY_STATS 236 efx_rc_t (*epo_stats_update)(efx_nic_t *, efsys_mem_t *, 237 uint32_t *); 238 #endif /* EFSYS_OPT_PHY_STATS */ 239 #if EFSYS_OPT_BIST 240 efx_rc_t (*epo_bist_enable_offline)(efx_nic_t *); 241 efx_rc_t (*epo_bist_start)(efx_nic_t *, efx_bist_type_t); 242 efx_rc_t (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t, 243 efx_bist_result_t *, uint32_t *, 244 unsigned long *, size_t); 245 void (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t); 246 #endif /* EFSYS_OPT_BIST */ 247 } efx_phy_ops_t; 248 249 #if EFSYS_OPT_FILTER 250 typedef struct efx_filter_ops_s { 251 efx_rc_t (*efo_init)(efx_nic_t *); 252 void (*efo_fini)(efx_nic_t *); 253 efx_rc_t (*efo_restore)(efx_nic_t *); 254 efx_rc_t (*efo_add)(efx_nic_t *, efx_filter_spec_t *, 255 boolean_t may_replace); 256 efx_rc_t (*efo_delete)(efx_nic_t *, efx_filter_spec_t *); 257 efx_rc_t (*efo_supported_filters)(efx_nic_t *, uint32_t *, 258 size_t, size_t *); 259 efx_rc_t (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t, 260 boolean_t, boolean_t, boolean_t, 261 uint8_t const *, uint32_t); 262 } efx_filter_ops_t; 263 264 extern __checkReturn efx_rc_t 265 efx_filter_reconfigure( 266 __in efx_nic_t *enp, 267 __in_ecount(6) uint8_t const *mac_addr, 268 __in boolean_t all_unicst, 269 __in boolean_t mulcst, 270 __in boolean_t all_mulcst, 271 __in boolean_t brdcst, 272 __in_ecount(6*count) uint8_t const *addrs, 273 __in uint32_t count); 274 275 #endif /* EFSYS_OPT_FILTER */ 276 277 #if EFSYS_OPT_TUNNEL 278 typedef struct efx_tunnel_ops_s { 279 boolean_t (*eto_udp_encap_supported)(efx_nic_t *); 280 efx_rc_t (*eto_reconfigure)(efx_nic_t *); 281 } efx_tunnel_ops_t; 282 #endif /* EFSYS_OPT_TUNNEL */ 283 284 typedef struct efx_port_s { 285 efx_mac_type_t ep_mac_type; 286 uint32_t ep_phy_type; 287 uint8_t ep_port; 288 uint32_t ep_mac_pdu; 289 uint8_t ep_mac_addr[6]; 290 efx_link_mode_t ep_link_mode; 291 boolean_t ep_all_unicst; 292 boolean_t ep_mulcst; 293 boolean_t ep_all_mulcst; 294 boolean_t ep_brdcst; 295 unsigned int ep_fcntl; 296 boolean_t ep_fcntl_autoneg; 297 efx_oword_t ep_multicst_hash[2]; 298 uint8_t ep_mulcst_addr_list[EFX_MAC_ADDR_LEN * 299 EFX_MAC_MULTICAST_LIST_MAX]; 300 uint32_t ep_mulcst_addr_count; 301 #if EFSYS_OPT_LOOPBACK 302 efx_loopback_type_t ep_loopback_type; 303 efx_link_mode_t ep_loopback_link_mode; 304 #endif /* EFSYS_OPT_LOOPBACK */ 305 #if EFSYS_OPT_PHY_FLAGS 306 uint32_t ep_phy_flags; 307 #endif /* EFSYS_OPT_PHY_FLAGS */ 308 #if EFSYS_OPT_PHY_LED_CONTROL 309 efx_phy_led_mode_t ep_phy_led_mode; 310 #endif /* EFSYS_OPT_PHY_LED_CONTROL */ 311 efx_phy_media_type_t ep_fixed_port_type; 312 efx_phy_media_type_t ep_module_type; 313 uint32_t ep_adv_cap_mask; 314 uint32_t ep_lp_cap_mask; 315 uint32_t ep_default_adv_cap_mask; 316 uint32_t ep_phy_cap_mask; 317 boolean_t ep_mac_drain; 318 #if EFSYS_OPT_BIST 319 efx_bist_type_t ep_current_bist; 320 #endif 321 const efx_mac_ops_t *ep_emop; 322 const efx_phy_ops_t *ep_epop; 323 } efx_port_t; 324 325 typedef struct efx_mon_ops_s { 326 #if EFSYS_OPT_MON_STATS 327 efx_rc_t (*emo_stats_update)(efx_nic_t *, efsys_mem_t *, 328 efx_mon_stat_value_t *); 329 #endif /* EFSYS_OPT_MON_STATS */ 330 } efx_mon_ops_t; 331 332 typedef struct efx_mon_s { 333 efx_mon_type_t em_type; 334 const efx_mon_ops_t *em_emop; 335 } efx_mon_t; 336 337 typedef struct efx_intr_ops_s { 338 efx_rc_t (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *); 339 void (*eio_enable)(efx_nic_t *); 340 void (*eio_disable)(efx_nic_t *); 341 void (*eio_disable_unlocked)(efx_nic_t *); 342 efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); 343 void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); 344 void (*eio_status_message)(efx_nic_t *, unsigned int, 345 boolean_t *); 346 void (*eio_fatal)(efx_nic_t *); 347 void (*eio_fini)(efx_nic_t *); 348 } efx_intr_ops_t; 349 350 typedef struct efx_intr_s { 351 const efx_intr_ops_t *ei_eiop; 352 efsys_mem_t *ei_esmp; 353 efx_intr_type_t ei_type; 354 unsigned int ei_level; 355 } efx_intr_t; 356 357 typedef struct efx_nic_ops_s { 358 efx_rc_t (*eno_probe)(efx_nic_t *); 359 efx_rc_t (*eno_board_cfg)(efx_nic_t *); 360 efx_rc_t (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*); 361 efx_rc_t (*eno_reset)(efx_nic_t *); 362 efx_rc_t (*eno_init)(efx_nic_t *); 363 efx_rc_t (*eno_get_vi_pool)(efx_nic_t *, uint32_t *); 364 efx_rc_t (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t, 365 uint32_t *, size_t *); 366 #if EFSYS_OPT_DIAG 367 efx_rc_t (*eno_register_test)(efx_nic_t *); 368 #endif /* EFSYS_OPT_DIAG */ 369 void (*eno_fini)(efx_nic_t *); 370 void (*eno_unprobe)(efx_nic_t *); 371 } efx_nic_ops_t; 372 373 #ifndef EFX_TXQ_LIMIT_TARGET 374 #define EFX_TXQ_LIMIT_TARGET 259 375 #endif 376 #ifndef EFX_RXQ_LIMIT_TARGET 377 #define EFX_RXQ_LIMIT_TARGET 512 378 #endif 379 380 381 #if EFSYS_OPT_FILTER 382 383 #if EFSYS_OPT_SIENA 384 385 typedef struct siena_filter_spec_s { 386 uint8_t sfs_type; 387 uint32_t sfs_flags; 388 uint32_t sfs_dmaq_id; 389 uint32_t sfs_dword[3]; 390 } siena_filter_spec_t; 391 392 typedef enum siena_filter_type_e { 393 EFX_SIENA_FILTER_RX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 394 EFX_SIENA_FILTER_RX_TCP_WILD, /* TCP/IPv4 {dIP,dTCP, -, -} */ 395 EFX_SIENA_FILTER_RX_UDP_FULL, /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */ 396 EFX_SIENA_FILTER_RX_UDP_WILD, /* UDP/IPv4 {dIP,dUDP, -, -} */ 397 EFX_SIENA_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */ 398 EFX_SIENA_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */ 399 400 EFX_SIENA_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */ 401 EFX_SIENA_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */ 402 EFX_SIENA_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */ 403 EFX_SIENA_FILTER_TX_UDP_WILD, /* UDP/IPv4 { -, -,sIP,sUDP} */ 404 EFX_SIENA_FILTER_TX_MAC_FULL, /* Ethernet {sMAC,VLAN} */ 405 EFX_SIENA_FILTER_TX_MAC_WILD, /* Ethernet {sMAC, -} */ 406 407 EFX_SIENA_FILTER_NTYPES 408 } siena_filter_type_t; 409 410 typedef enum siena_filter_tbl_id_e { 411 EFX_SIENA_FILTER_TBL_RX_IP = 0, 412 EFX_SIENA_FILTER_TBL_RX_MAC, 413 EFX_SIENA_FILTER_TBL_TX_IP, 414 EFX_SIENA_FILTER_TBL_TX_MAC, 415 EFX_SIENA_FILTER_NTBLS 416 } siena_filter_tbl_id_t; 417 418 typedef struct siena_filter_tbl_s { 419 int sft_size; /* number of entries */ 420 int sft_used; /* active count */ 421 uint32_t *sft_bitmap; /* active bitmap */ 422 siena_filter_spec_t *sft_spec; /* array of saved specs */ 423 } siena_filter_tbl_t; 424 425 typedef struct siena_filter_s { 426 siena_filter_tbl_t sf_tbl[EFX_SIENA_FILTER_NTBLS]; 427 unsigned int sf_depth[EFX_SIENA_FILTER_NTYPES]; 428 } siena_filter_t; 429 430 #endif /* EFSYS_OPT_SIENA */ 431 432 typedef struct efx_filter_s { 433 #if EFSYS_OPT_SIENA 434 siena_filter_t *ef_siena_filter; 435 #endif /* EFSYS_OPT_SIENA */ 436 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 437 ef10_filter_table_t *ef_ef10_filter_table; 438 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */ 439 } efx_filter_t; 440 441 #if EFSYS_OPT_SIENA 442 443 extern void 444 siena_filter_tbl_clear( 445 __in efx_nic_t *enp, 446 __in siena_filter_tbl_id_t tbl); 447 448 #endif /* EFSYS_OPT_SIENA */ 449 450 #endif /* EFSYS_OPT_FILTER */ 451 452 #if EFSYS_OPT_MCDI 453 454 #define EFX_TUNNEL_MAXNENTRIES (16) 455 456 #if EFSYS_OPT_TUNNEL 457 458 typedef struct efx_tunnel_udp_entry_s { 459 uint16_t etue_port; /* host/cpu-endian */ 460 uint16_t etue_protocol; 461 } efx_tunnel_udp_entry_t; 462 463 typedef struct efx_tunnel_cfg_s { 464 efx_tunnel_udp_entry_t etc_udp_entries[EFX_TUNNEL_MAXNENTRIES]; 465 unsigned int etc_udp_entries_num; 466 } efx_tunnel_cfg_t; 467 468 #endif /* EFSYS_OPT_TUNNEL */ 469 470 typedef struct efx_mcdi_ops_s { 471 efx_rc_t (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *); 472 void (*emco_send_request)(efx_nic_t *, void *, size_t, 473 void *, size_t); 474 efx_rc_t (*emco_poll_reboot)(efx_nic_t *); 475 boolean_t (*emco_poll_response)(efx_nic_t *); 476 void (*emco_read_response)(efx_nic_t *, void *, size_t, size_t); 477 void (*emco_fini)(efx_nic_t *); 478 efx_rc_t (*emco_feature_supported)(efx_nic_t *, 479 efx_mcdi_feature_id_t, boolean_t *); 480 void (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *, 481 uint32_t *); 482 } efx_mcdi_ops_t; 483 484 typedef struct efx_mcdi_s { 485 const efx_mcdi_ops_t *em_emcop; 486 const efx_mcdi_transport_t *em_emtp; 487 efx_mcdi_iface_t em_emip; 488 } efx_mcdi_t; 489 490 #endif /* EFSYS_OPT_MCDI */ 491 492 #if EFSYS_OPT_NVRAM 493 494 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */ 495 #define EFX_NVRAM_PARTN_INVALID (0xffffffffu) 496 497 typedef struct efx_nvram_ops_s { 498 #if EFSYS_OPT_DIAG 499 efx_rc_t (*envo_test)(efx_nic_t *); 500 #endif /* EFSYS_OPT_DIAG */ 501 efx_rc_t (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t, 502 uint32_t *); 503 efx_rc_t (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *); 504 efx_rc_t (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *); 505 efx_rc_t (*envo_partn_read)(efx_nic_t *, uint32_t, 506 unsigned int, caddr_t, size_t); 507 efx_rc_t (*envo_partn_read_backup)(efx_nic_t *, uint32_t, 508 unsigned int, caddr_t, size_t); 509 efx_rc_t (*envo_partn_erase)(efx_nic_t *, uint32_t, 510 unsigned int, size_t); 511 efx_rc_t (*envo_partn_write)(efx_nic_t *, uint32_t, 512 unsigned int, caddr_t, size_t); 513 efx_rc_t (*envo_partn_rw_finish)(efx_nic_t *, uint32_t, 514 uint32_t *); 515 efx_rc_t (*envo_partn_get_version)(efx_nic_t *, uint32_t, 516 uint32_t *, uint16_t *); 517 efx_rc_t (*envo_partn_set_version)(efx_nic_t *, uint32_t, 518 uint16_t *); 519 efx_rc_t (*envo_buffer_validate)(efx_nic_t *, uint32_t, 520 caddr_t, size_t); 521 } efx_nvram_ops_t; 522 #endif /* EFSYS_OPT_NVRAM */ 523 524 #if EFSYS_OPT_VPD 525 typedef struct efx_vpd_ops_s { 526 efx_rc_t (*evpdo_init)(efx_nic_t *); 527 efx_rc_t (*evpdo_size)(efx_nic_t *, size_t *); 528 efx_rc_t (*evpdo_read)(efx_nic_t *, caddr_t, size_t); 529 efx_rc_t (*evpdo_verify)(efx_nic_t *, caddr_t, size_t); 530 efx_rc_t (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t); 531 efx_rc_t (*evpdo_get)(efx_nic_t *, caddr_t, size_t, 532 efx_vpd_value_t *); 533 efx_rc_t (*evpdo_set)(efx_nic_t *, caddr_t, size_t, 534 efx_vpd_value_t *); 535 efx_rc_t (*evpdo_next)(efx_nic_t *, caddr_t, size_t, 536 efx_vpd_value_t *, unsigned int *); 537 efx_rc_t (*evpdo_write)(efx_nic_t *, caddr_t, size_t); 538 void (*evpdo_fini)(efx_nic_t *); 539 } efx_vpd_ops_t; 540 #endif /* EFSYS_OPT_VPD */ 541 542 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM 543 544 __checkReturn efx_rc_t 545 efx_mcdi_nvram_partitions( 546 __in efx_nic_t *enp, 547 __out_bcount(size) caddr_t data, 548 __in size_t size, 549 __out unsigned int *npartnp); 550 551 __checkReturn efx_rc_t 552 efx_mcdi_nvram_metadata( 553 __in efx_nic_t *enp, 554 __in uint32_t partn, 555 __out uint32_t *subtypep, 556 __out_ecount(4) uint16_t version[4], 557 __out_bcount_opt(size) char *descp, 558 __in size_t size); 559 560 __checkReturn efx_rc_t 561 efx_mcdi_nvram_info( 562 __in efx_nic_t *enp, 563 __in uint32_t partn, 564 __out_opt size_t *sizep, 565 __out_opt uint32_t *addressp, 566 __out_opt uint32_t *erase_sizep, 567 __out_opt uint32_t *write_sizep); 568 569 __checkReturn efx_rc_t 570 efx_mcdi_nvram_update_start( 571 __in efx_nic_t *enp, 572 __in uint32_t partn); 573 574 __checkReturn efx_rc_t 575 efx_mcdi_nvram_read( 576 __in efx_nic_t *enp, 577 __in uint32_t partn, 578 __in uint32_t offset, 579 __out_bcount(size) caddr_t data, 580 __in size_t size, 581 __in uint32_t mode); 582 583 __checkReturn efx_rc_t 584 efx_mcdi_nvram_erase( 585 __in efx_nic_t *enp, 586 __in uint32_t partn, 587 __in uint32_t offset, 588 __in size_t size); 589 590 __checkReturn efx_rc_t 591 efx_mcdi_nvram_write( 592 __in efx_nic_t *enp, 593 __in uint32_t partn, 594 __in uint32_t offset, 595 __out_bcount(size) caddr_t data, 596 __in size_t size); 597 598 __checkReturn efx_rc_t 599 efx_mcdi_nvram_update_finish( 600 __in efx_nic_t *enp, 601 __in uint32_t partn, 602 __in boolean_t reboot, 603 __out_opt uint32_t *verify_resultp); 604 605 #if EFSYS_OPT_DIAG 606 607 __checkReturn efx_rc_t 608 efx_mcdi_nvram_test( 609 __in efx_nic_t *enp, 610 __in uint32_t partn); 611 612 #endif /* EFSYS_OPT_DIAG */ 613 614 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */ 615 616 #if EFSYS_OPT_LICENSING 617 618 typedef struct efx_lic_ops_s { 619 efx_rc_t (*elo_update_licenses)(efx_nic_t *); 620 efx_rc_t (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *); 621 efx_rc_t (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *); 622 efx_rc_t (*elo_get_id)(efx_nic_t *, size_t, uint32_t *, 623 size_t *, uint8_t *); 624 efx_rc_t (*elo_find_start) 625 (efx_nic_t *, caddr_t, size_t, uint32_t *); 626 efx_rc_t (*elo_find_end)(efx_nic_t *, caddr_t, size_t, 627 uint32_t, uint32_t *); 628 boolean_t (*elo_find_key)(efx_nic_t *, caddr_t, size_t, 629 uint32_t, uint32_t *, uint32_t *); 630 boolean_t (*elo_validate_key)(efx_nic_t *, 631 caddr_t, uint32_t); 632 efx_rc_t (*elo_read_key)(efx_nic_t *, 633 caddr_t, size_t, uint32_t, uint32_t, 634 caddr_t, size_t, uint32_t *); 635 efx_rc_t (*elo_write_key)(efx_nic_t *, 636 caddr_t, size_t, uint32_t, 637 caddr_t, uint32_t, uint32_t *); 638 efx_rc_t (*elo_delete_key)(efx_nic_t *, 639 caddr_t, size_t, uint32_t, 640 uint32_t, uint32_t, uint32_t *); 641 efx_rc_t (*elo_create_partition)(efx_nic_t *, 642 caddr_t, size_t); 643 efx_rc_t (*elo_finish_partition)(efx_nic_t *, 644 caddr_t, size_t); 645 } efx_lic_ops_t; 646 647 #endif 648 649 typedef struct efx_drv_cfg_s { 650 uint32_t edc_min_vi_count; 651 uint32_t edc_max_vi_count; 652 653 uint32_t edc_max_piobuf_count; 654 uint32_t edc_pio_alloc_size; 655 } efx_drv_cfg_t; 656 657 struct efx_nic_s { 658 uint32_t en_magic; 659 efx_family_t en_family; 660 uint32_t en_features; 661 efsys_identifier_t *en_esip; 662 efsys_lock_t *en_eslp; 663 efsys_bar_t *en_esbp; 664 unsigned int en_mod_flags; 665 unsigned int en_reset_flags; 666 efx_nic_cfg_t en_nic_cfg; 667 efx_drv_cfg_t en_drv_cfg; 668 efx_port_t en_port; 669 efx_mon_t en_mon; 670 efx_intr_t en_intr; 671 uint32_t en_ev_qcount; 672 uint32_t en_rx_qcount; 673 uint32_t en_tx_qcount; 674 const efx_nic_ops_t *en_enop; 675 const efx_ev_ops_t *en_eevop; 676 const efx_tx_ops_t *en_etxop; 677 const efx_rx_ops_t *en_erxop; 678 #if EFSYS_OPT_FILTER 679 efx_filter_t en_filter; 680 const efx_filter_ops_t *en_efop; 681 #endif /* EFSYS_OPT_FILTER */ 682 #if EFSYS_OPT_TUNNEL 683 efx_tunnel_cfg_t en_tunnel_cfg; 684 const efx_tunnel_ops_t *en_etop; 685 #endif /* EFSYS_OPT_TUNNEL */ 686 #if EFSYS_OPT_MCDI 687 efx_mcdi_t en_mcdi; 688 #endif /* EFSYS_OPT_MCDI */ 689 #if EFSYS_OPT_NVRAM 690 uint32_t en_nvram_partn_locked; 691 const efx_nvram_ops_t *en_envop; 692 #endif /* EFSYS_OPT_NVRAM */ 693 #if EFSYS_OPT_VPD 694 const efx_vpd_ops_t *en_evpdop; 695 #endif /* EFSYS_OPT_VPD */ 696 #if EFSYS_OPT_RX_SCALE 697 efx_rx_hash_support_t en_hash_support; 698 efx_rx_scale_context_type_t en_rss_context_type; 699 uint32_t en_rss_context; 700 #endif /* EFSYS_OPT_RX_SCALE */ 701 uint32_t en_vport_id; 702 #if EFSYS_OPT_LICENSING 703 const efx_lic_ops_t *en_elop; 704 boolean_t en_licensing_supported; 705 #endif 706 union { 707 #if EFSYS_OPT_SIENA 708 struct { 709 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD 710 unsigned int enu_partn_mask; 711 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ 712 #if EFSYS_OPT_VPD 713 caddr_t enu_svpd; 714 size_t enu_svpd_length; 715 #endif /* EFSYS_OPT_VPD */ 716 int enu_unused; 717 } siena; 718 #endif /* EFSYS_OPT_SIENA */ 719 int enu_unused; 720 } en_u; 721 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) 722 union en_arch { 723 struct { 724 int ena_vi_base; 725 int ena_vi_count; 726 int ena_vi_shift; 727 #if EFSYS_OPT_VPD 728 caddr_t ena_svpd; 729 size_t ena_svpd_length; 730 #endif /* EFSYS_OPT_VPD */ 731 efx_piobuf_handle_t ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS]; 732 uint32_t ena_piobuf_count; 733 uint32_t ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS]; 734 uint32_t ena_pio_write_vi_base; 735 /* Memory BAR mapping regions */ 736 uint32_t ena_uc_mem_map_offset; 737 size_t ena_uc_mem_map_size; 738 uint32_t ena_wc_mem_map_offset; 739 size_t ena_wc_mem_map_size; 740 } ef10; 741 } en_arch; 742 #endif /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */ 743 }; 744 745 746 #define EFX_NIC_MAGIC 0x02121996 747 748 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *, 749 const efx_ev_callbacks_t *, void *); 750 751 typedef struct efx_evq_rxq_state_s { 752 unsigned int eers_rx_read_ptr; 753 unsigned int eers_rx_mask; 754 #if EFSYS_OPT_RX_PACKED_STREAM 755 unsigned int eers_rx_stream_npackets; 756 boolean_t eers_rx_packed_stream; 757 unsigned int eers_rx_packed_stream_credits; 758 #endif 759 } efx_evq_rxq_state_t; 760 761 struct efx_evq_s { 762 uint32_t ee_magic; 763 efx_nic_t *ee_enp; 764 unsigned int ee_index; 765 unsigned int ee_mask; 766 efsys_mem_t *ee_esmp; 767 #if EFSYS_OPT_QSTATS 768 uint32_t ee_stat[EV_NQSTATS]; 769 #endif /* EFSYS_OPT_QSTATS */ 770 771 efx_ev_handler_t ee_rx; 772 efx_ev_handler_t ee_tx; 773 efx_ev_handler_t ee_driver; 774 efx_ev_handler_t ee_global; 775 efx_ev_handler_t ee_drv_gen; 776 #if EFSYS_OPT_MCDI 777 efx_ev_handler_t ee_mcdi; 778 #endif /* EFSYS_OPT_MCDI */ 779 780 efx_evq_rxq_state_t ee_rxq_state[EFX_EV_RX_NLABELS]; 781 782 uint32_t ee_flags; 783 }; 784 785 #define EFX_EVQ_MAGIC 0x08081997 786 787 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */ 788 789 struct efx_rxq_s { 790 uint32_t er_magic; 791 efx_nic_t *er_enp; 792 efx_evq_t *er_eep; 793 unsigned int er_index; 794 unsigned int er_label; 795 unsigned int er_mask; 796 efsys_mem_t *er_esmp; 797 efx_evq_rxq_state_t *er_ev_qstate; 798 }; 799 800 #define EFX_RXQ_MAGIC 0x15022005 801 802 struct efx_txq_s { 803 uint32_t et_magic; 804 efx_nic_t *et_enp; 805 unsigned int et_index; 806 unsigned int et_mask; 807 efsys_mem_t *et_esmp; 808 #if EFSYS_OPT_HUNTINGTON 809 uint32_t et_pio_bufnum; 810 uint32_t et_pio_blknum; 811 uint32_t et_pio_write_offset; 812 uint32_t et_pio_offset; 813 size_t et_pio_size; 814 #endif 815 #if EFSYS_OPT_QSTATS 816 uint32_t et_stat[TX_NQSTATS]; 817 #endif /* EFSYS_OPT_QSTATS */ 818 }; 819 820 #define EFX_TXQ_MAGIC 0x05092005 821 822 #define EFX_MAC_ADDR_COPY(_dst, _src) \ 823 do { \ 824 (_dst)[0] = (_src)[0]; \ 825 (_dst)[1] = (_src)[1]; \ 826 (_dst)[2] = (_src)[2]; \ 827 (_dst)[3] = (_src)[3]; \ 828 (_dst)[4] = (_src)[4]; \ 829 (_dst)[5] = (_src)[5]; \ 830 _NOTE(CONSTANTCONDITION) \ 831 } while (B_FALSE) 832 833 #define EFX_MAC_BROADCAST_ADDR_SET(_dst) \ 834 do { \ 835 uint16_t *_d = (uint16_t *)(_dst); \ 836 _d[0] = 0xffff; \ 837 _d[1] = 0xffff; \ 838 _d[2] = 0xffff; \ 839 _NOTE(CONSTANTCONDITION) \ 840 } while (B_FALSE) 841 842 #if EFSYS_OPT_CHECK_REG 843 #define EFX_CHECK_REG(_enp, _reg) \ 844 do { \ 845 const char *name = #_reg; \ 846 char min = name[4]; \ 847 char max = name[5]; \ 848 char rev; \ 849 \ 850 switch ((_enp)->en_family) { \ 851 case EFX_FAMILY_SIENA: \ 852 rev = 'C'; \ 853 break; \ 854 \ 855 case EFX_FAMILY_HUNTINGTON: \ 856 rev = 'D'; \ 857 break; \ 858 \ 859 case EFX_FAMILY_MEDFORD: \ 860 rev = 'E'; \ 861 break; \ 862 \ 863 case EFX_FAMILY_MEDFORD2: \ 864 rev = 'F'; \ 865 break; \ 866 \ 867 default: \ 868 rev = '?'; \ 869 break; \ 870 } \ 871 \ 872 EFSYS_ASSERT3S(rev, >=, min); \ 873 EFSYS_ASSERT3S(rev, <=, max); \ 874 \ 875 _NOTE(CONSTANTCONDITION) \ 876 } while (B_FALSE) 877 #else 878 #define EFX_CHECK_REG(_enp, _reg) do { \ 879 _NOTE(CONSTANTCONDITION) \ 880 } while (B_FALSE) 881 #endif 882 883 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \ 884 do { \ 885 EFX_CHECK_REG((_enp), (_reg)); \ 886 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \ 887 (_edp), (_lock)); \ 888 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \ 889 uint32_t, _reg ## _OFST, \ 890 uint32_t, (_edp)->ed_u32[0]); \ 891 _NOTE(CONSTANTCONDITION) \ 892 } while (B_FALSE) 893 894 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \ 895 do { \ 896 EFX_CHECK_REG((_enp), (_reg)); \ 897 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \ 898 uint32_t, _reg ## _OFST, \ 899 uint32_t, (_edp)->ed_u32[0]); \ 900 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \ 901 (_edp), (_lock)); \ 902 _NOTE(CONSTANTCONDITION) \ 903 } while (B_FALSE) 904 905 #define EFX_BAR_READQ(_enp, _reg, _eqp) \ 906 do { \ 907 EFX_CHECK_REG((_enp), (_reg)); \ 908 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \ 909 (_eqp)); \ 910 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \ 911 uint32_t, _reg ## _OFST, \ 912 uint32_t, (_eqp)->eq_u32[1], \ 913 uint32_t, (_eqp)->eq_u32[0]); \ 914 _NOTE(CONSTANTCONDITION) \ 915 } while (B_FALSE) 916 917 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \ 918 do { \ 919 EFX_CHECK_REG((_enp), (_reg)); \ 920 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \ 921 uint32_t, _reg ## _OFST, \ 922 uint32_t, (_eqp)->eq_u32[1], \ 923 uint32_t, (_eqp)->eq_u32[0]); \ 924 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \ 925 (_eqp)); \ 926 _NOTE(CONSTANTCONDITION) \ 927 } while (B_FALSE) 928 929 #define EFX_BAR_READO(_enp, _reg, _eop) \ 930 do { \ 931 EFX_CHECK_REG((_enp), (_reg)); \ 932 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \ 933 (_eop), B_TRUE); \ 934 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \ 935 uint32_t, _reg ## _OFST, \ 936 uint32_t, (_eop)->eo_u32[3], \ 937 uint32_t, (_eop)->eo_u32[2], \ 938 uint32_t, (_eop)->eo_u32[1], \ 939 uint32_t, (_eop)->eo_u32[0]); \ 940 _NOTE(CONSTANTCONDITION) \ 941 } while (B_FALSE) 942 943 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \ 944 do { \ 945 EFX_CHECK_REG((_enp), (_reg)); \ 946 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \ 947 uint32_t, _reg ## _OFST, \ 948 uint32_t, (_eop)->eo_u32[3], \ 949 uint32_t, (_eop)->eo_u32[2], \ 950 uint32_t, (_eop)->eo_u32[1], \ 951 uint32_t, (_eop)->eo_u32[0]); \ 952 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \ 953 (_eop), B_TRUE); \ 954 _NOTE(CONSTANTCONDITION) \ 955 } while (B_FALSE) 956 957 /* 958 * Accessors for memory BAR non-VI tables. 959 * 960 * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers, 961 * to ensure the correct runtime VI window size is used on Medford2. 962 * 963 * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers. 964 */ 965 966 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \ 967 do { \ 968 EFX_CHECK_REG((_enp), (_reg)); \ 969 EFSYS_BAR_READD((_enp)->en_esbp, \ 970 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 971 (_edp), (_lock)); \ 972 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \ 973 uint32_t, (_index), \ 974 uint32_t, _reg ## _OFST, \ 975 uint32_t, (_edp)->ed_u32[0]); \ 976 _NOTE(CONSTANTCONDITION) \ 977 } while (B_FALSE) 978 979 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \ 980 do { \ 981 EFX_CHECK_REG((_enp), (_reg)); \ 982 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 983 uint32_t, (_index), \ 984 uint32_t, _reg ## _OFST, \ 985 uint32_t, (_edp)->ed_u32[0]); \ 986 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 987 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 988 (_edp), (_lock)); \ 989 _NOTE(CONSTANTCONDITION) \ 990 } while (B_FALSE) 991 992 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \ 993 do { \ 994 EFX_CHECK_REG((_enp), (_reg)); \ 995 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \ 996 uint32_t, (_index), \ 997 uint32_t, _reg ## _OFST, \ 998 uint32_t, (_edp)->ed_u32[0]); \ 999 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1000 (_reg ## _OFST + \ 1001 (3 * sizeof (efx_dword_t)) + \ 1002 ((_index) * _reg ## _STEP)), \ 1003 (_edp), (_lock)); \ 1004 _NOTE(CONSTANTCONDITION) \ 1005 } while (B_FALSE) 1006 1007 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \ 1008 do { \ 1009 EFX_CHECK_REG((_enp), (_reg)); \ 1010 EFSYS_BAR_READQ((_enp)->en_esbp, \ 1011 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1012 (_eqp)); \ 1013 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \ 1014 uint32_t, (_index), \ 1015 uint32_t, _reg ## _OFST, \ 1016 uint32_t, (_eqp)->eq_u32[1], \ 1017 uint32_t, (_eqp)->eq_u32[0]); \ 1018 _NOTE(CONSTANTCONDITION) \ 1019 } while (B_FALSE) 1020 1021 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \ 1022 do { \ 1023 EFX_CHECK_REG((_enp), (_reg)); \ 1024 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \ 1025 uint32_t, (_index), \ 1026 uint32_t, _reg ## _OFST, \ 1027 uint32_t, (_eqp)->eq_u32[1], \ 1028 uint32_t, (_eqp)->eq_u32[0]); \ 1029 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \ 1030 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1031 (_eqp)); \ 1032 _NOTE(CONSTANTCONDITION) \ 1033 } while (B_FALSE) 1034 1035 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock) \ 1036 do { \ 1037 EFX_CHECK_REG((_enp), (_reg)); \ 1038 EFSYS_BAR_READO((_enp)->en_esbp, \ 1039 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1040 (_eop), (_lock)); \ 1041 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \ 1042 uint32_t, (_index), \ 1043 uint32_t, _reg ## _OFST, \ 1044 uint32_t, (_eop)->eo_u32[3], \ 1045 uint32_t, (_eop)->eo_u32[2], \ 1046 uint32_t, (_eop)->eo_u32[1], \ 1047 uint32_t, (_eop)->eo_u32[0]); \ 1048 _NOTE(CONSTANTCONDITION) \ 1049 } while (B_FALSE) 1050 1051 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock) \ 1052 do { \ 1053 EFX_CHECK_REG((_enp), (_reg)); \ 1054 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \ 1055 uint32_t, (_index), \ 1056 uint32_t, _reg ## _OFST, \ 1057 uint32_t, (_eop)->eo_u32[3], \ 1058 uint32_t, (_eop)->eo_u32[2], \ 1059 uint32_t, (_eop)->eo_u32[1], \ 1060 uint32_t, (_eop)->eo_u32[0]); \ 1061 EFSYS_BAR_WRITEO((_enp)->en_esbp, \ 1062 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \ 1063 (_eop), (_lock)); \ 1064 _NOTE(CONSTANTCONDITION) \ 1065 } while (B_FALSE) 1066 1067 /* 1068 * Accessors for memory BAR per-VI registers. 1069 * 1070 * The VI window size is 8KB for Medford and all earlier controllers. 1071 * For Medford2, the VI window size can be 8KB, 16KB or 64KB. 1072 */ 1073 1074 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock) \ 1075 do { \ 1076 EFX_CHECK_REG((_enp), (_reg)); \ 1077 EFSYS_BAR_READD((_enp)->en_esbp, \ 1078 ((_reg ## _OFST) + \ 1079 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1080 (_edp), (_lock)); \ 1081 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg, \ 1082 uint32_t, (_index), \ 1083 uint32_t, _reg ## _OFST, \ 1084 uint32_t, (_edp)->ed_u32[0]); \ 1085 _NOTE(CONSTANTCONDITION) \ 1086 } while (B_FALSE) 1087 1088 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock) \ 1089 do { \ 1090 EFX_CHECK_REG((_enp), (_reg)); \ 1091 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1092 uint32_t, (_index), \ 1093 uint32_t, _reg ## _OFST, \ 1094 uint32_t, (_edp)->ed_u32[0]); \ 1095 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1096 ((_reg ## _OFST) + \ 1097 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1098 (_edp), (_lock)); \ 1099 _NOTE(CONSTANTCONDITION) \ 1100 } while (B_FALSE) 1101 1102 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock) \ 1103 do { \ 1104 EFX_CHECK_REG((_enp), (_reg)); \ 1105 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg, \ 1106 uint32_t, (_index), \ 1107 uint32_t, _reg ## _OFST, \ 1108 uint32_t, (_edp)->ed_u32[0]); \ 1109 EFSYS_BAR_WRITED((_enp)->en_esbp, \ 1110 ((_reg ## _OFST) + \ 1111 (2 * sizeof (efx_dword_t)) + \ 1112 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1113 (_edp), (_lock)); \ 1114 _NOTE(CONSTANTCONDITION) \ 1115 } while (B_FALSE) 1116 1117 /* 1118 * Allow drivers to perform optimised 128-bit VI doorbell writes. 1119 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are 1120 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid 1121 * the need for locking in the host, and are the only ones known to be safe to 1122 * use 128-bites write with. 1123 */ 1124 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop) \ 1125 do { \ 1126 EFX_CHECK_REG((_enp), (_reg)); \ 1127 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo, \ 1128 const char *, #_reg, \ 1129 uint32_t, (_index), \ 1130 uint32_t, _reg ## _OFST, \ 1131 uint32_t, (_eop)->eo_u32[3], \ 1132 uint32_t, (_eop)->eo_u32[2], \ 1133 uint32_t, (_eop)->eo_u32[1], \ 1134 uint32_t, (_eop)->eo_u32[0]); \ 1135 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp, \ 1136 (_reg ## _OFST + \ 1137 ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \ 1138 (_eop)); \ 1139 _NOTE(CONSTANTCONDITION) \ 1140 } while (B_FALSE) 1141 1142 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr) \ 1143 do { \ 1144 unsigned int _new = (_wptr); \ 1145 unsigned int _old = (_owptr); \ 1146 \ 1147 if ((_new) >= (_old)) \ 1148 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1149 (_old) * sizeof (efx_desc_t), \ 1150 ((_new) - (_old)) * sizeof (efx_desc_t)); \ 1151 else \ 1152 /* \ 1153 * It is cheaper to sync entire map than sync \ 1154 * two parts especially when offset/size are \ 1155 * ignored and entire map is synced in any case.\ 1156 */ \ 1157 EFSYS_DMA_SYNC_FOR_DEVICE((_esmp), \ 1158 0, \ 1159 (_entries) * sizeof (efx_desc_t)); \ 1160 _NOTE(CONSTANTCONDITION) \ 1161 } while (B_FALSE) 1162 1163 extern __checkReturn efx_rc_t 1164 efx_mac_select( 1165 __in efx_nic_t *enp); 1166 1167 extern void 1168 efx_mac_multicast_hash_compute( 1169 __in_ecount(6*count) uint8_t const *addrs, 1170 __in int count, 1171 __out efx_oword_t *hash_low, 1172 __out efx_oword_t *hash_high); 1173 1174 extern __checkReturn efx_rc_t 1175 efx_phy_probe( 1176 __in efx_nic_t *enp); 1177 1178 extern void 1179 efx_phy_unprobe( 1180 __in efx_nic_t *enp); 1181 1182 #if EFSYS_OPT_VPD 1183 1184 /* VPD utility functions */ 1185 1186 extern __checkReturn efx_rc_t 1187 efx_vpd_hunk_length( 1188 __in_bcount(size) caddr_t data, 1189 __in size_t size, 1190 __out size_t *lengthp); 1191 1192 extern __checkReturn efx_rc_t 1193 efx_vpd_hunk_verify( 1194 __in_bcount(size) caddr_t data, 1195 __in size_t size, 1196 __out_opt boolean_t *cksummedp); 1197 1198 extern __checkReturn efx_rc_t 1199 efx_vpd_hunk_reinit( 1200 __in_bcount(size) caddr_t data, 1201 __in size_t size, 1202 __in boolean_t wantpid); 1203 1204 extern __checkReturn efx_rc_t 1205 efx_vpd_hunk_get( 1206 __in_bcount(size) caddr_t data, 1207 __in size_t size, 1208 __in efx_vpd_tag_t tag, 1209 __in efx_vpd_keyword_t keyword, 1210 __out unsigned int *payloadp, 1211 __out uint8_t *paylenp); 1212 1213 extern __checkReturn efx_rc_t 1214 efx_vpd_hunk_next( 1215 __in_bcount(size) caddr_t data, 1216 __in size_t size, 1217 __out efx_vpd_tag_t *tagp, 1218 __out efx_vpd_keyword_t *keyword, 1219 __out_opt unsigned int *payloadp, 1220 __out_opt uint8_t *paylenp, 1221 __inout unsigned int *contp); 1222 1223 extern __checkReturn efx_rc_t 1224 efx_vpd_hunk_set( 1225 __in_bcount(size) caddr_t data, 1226 __in size_t size, 1227 __in efx_vpd_value_t *evvp); 1228 1229 #endif /* EFSYS_OPT_VPD */ 1230 1231 #if EFSYS_OPT_MCDI 1232 1233 extern __checkReturn efx_rc_t 1234 efx_mcdi_set_workaround( 1235 __in efx_nic_t *enp, 1236 __in uint32_t type, 1237 __in boolean_t enabled, 1238 __out_opt uint32_t *flagsp); 1239 1240 extern __checkReturn efx_rc_t 1241 efx_mcdi_get_workarounds( 1242 __in efx_nic_t *enp, 1243 __out_opt uint32_t *implementedp, 1244 __out_opt uint32_t *enabledp); 1245 1246 #endif /* EFSYS_OPT_MCDI */ 1247 1248 #if EFSYS_OPT_MAC_STATS 1249 1250 /* 1251 * Closed range of stats (i.e. the first and the last are included). 1252 * The last must be greater or equal (if the range is one item only) to 1253 * the first. 1254 */ 1255 struct efx_mac_stats_range { 1256 efx_mac_stat_t first; 1257 efx_mac_stat_t last; 1258 }; 1259 1260 extern efx_rc_t 1261 efx_mac_stats_mask_add_ranges( 1262 __inout_bcount(mask_size) uint32_t *maskp, 1263 __in size_t mask_size, 1264 __in_ecount(rng_count) const struct efx_mac_stats_range *rngp, 1265 __in unsigned int rng_count); 1266 1267 #endif /* EFSYS_OPT_MAC_STATS */ 1268 1269 #ifdef __cplusplus 1270 } 1271 #endif 1272 1273 #endif /* _SYS_EFX_IMPL_H */ 1274