1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com> 8 * Chandrakanth Patil <chandrakanth.patil@broadcom.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation and/or other 18 * materials provided with the distribution. 19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * The views and conclusions contained in the software and documentation are 36 * those of the authors and should not be interpreted as representing 37 * official policies,either expressed or implied, of the FreeBSD Project. 38 * 39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 40 * 41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 #include <sys/conf.h> 51 #include <sys/malloc.h> 52 #include <sys/sysctl.h> 53 #include <sys/uio.h> 54 55 #include <machine/bus.h> 56 #include <machine/resource.h> 57 #include <sys/rman.h> 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pci_private.h> 62 63 #include <cam/cam.h> 64 #include <cam/cam_ccb.h> 65 #include <cam/cam_debug.h> 66 #include <cam/cam_sim.h> 67 #include <cam/cam_xpt_sim.h> 68 #include <cam/cam_xpt_periph.h> 69 #include <cam/cam_periph.h> 70 #include <cam/scsi/scsi_all.h> 71 #include <cam/scsi/scsi_message.h> 72 #include <cam/scsi/smp_all.h> 73 #include <sys/queue.h> 74 #include <sys/kthread.h> 75 #include "mpi3mr.h" 76 #include "mpi3mr_cam.h" 77 #include "mpi3mr_app.h" 78 79 static void mpi3mr_repost_reply_buf(struct mpi3mr_softc *sc, 80 U64 reply_dma); 81 static int mpi3mr_complete_admin_cmd(struct mpi3mr_softc *sc); 82 static void mpi3mr_port_enable_complete(struct mpi3mr_softc *sc, 83 struct mpi3mr_drvr_cmd *drvrcmd); 84 static void mpi3mr_flush_io(struct mpi3mr_softc *sc); 85 static int mpi3mr_issue_reset(struct mpi3mr_softc *sc, U16 reset_type, 86 U32 reset_reason); 87 static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_softc *sc, U16 handle, 88 struct mpi3mr_drvr_cmd *cmdparam, U8 iou_rc); 89 static void mpi3mr_dev_rmhs_complete_iou(struct mpi3mr_softc *sc, 90 struct mpi3mr_drvr_cmd *drv_cmd); 91 static void mpi3mr_dev_rmhs_complete_tm(struct mpi3mr_softc *sc, 92 struct mpi3mr_drvr_cmd *drv_cmd); 93 static void mpi3mr_send_evt_ack(struct mpi3mr_softc *sc, U8 event, 94 struct mpi3mr_drvr_cmd *cmdparam, U32 event_ctx); 95 static void mpi3mr_print_fault_info(struct mpi3mr_softc *sc); 96 static inline void mpi3mr_set_diagsave(struct mpi3mr_softc *sc); 97 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code); 98 99 void 100 mpi3mr_hexdump(void *buf, int sz, int format) 101 { 102 int i; 103 U32 *buf_loc = (U32 *)buf; 104 105 for (i = 0; i < (sz / sizeof(U32)); i++) { 106 if ((i % format) == 0) { 107 if (i != 0) 108 printf("\n"); 109 printf("%08x: ", (i * 4)); 110 } 111 printf("%08x ", buf_loc[i]); 112 } 113 printf("\n"); 114 } 115 116 void 117 init_completion(struct completion *completion) 118 { 119 completion->done = 0; 120 } 121 122 void 123 complete(struct completion *completion) 124 { 125 completion->done = 1; 126 wakeup(complete); 127 } 128 129 void wait_for_completion_timeout(struct completion *completion, 130 U32 timeout) 131 { 132 U32 count = timeout * 1000; 133 134 while ((completion->done == 0) && count) { 135 DELAY(1000); 136 count--; 137 } 138 139 if (completion->done == 0) { 140 printf("%s: Command is timedout\n", __func__); 141 completion->done = 1; 142 } 143 } 144 void wait_for_completion_timeout_tm(struct completion *completion, 145 U32 timeout, struct mpi3mr_softc *sc) 146 { 147 U32 count = timeout * 1000; 148 149 while ((completion->done == 0) && count) { 150 msleep(&sc->tm_chan, &sc->mpi3mr_mtx, PRIBIO, 151 "TM command", 1 * hz); 152 count--; 153 } 154 155 if (completion->done == 0) { 156 printf("%s: Command is timedout\n", __func__); 157 completion->done = 1; 158 } 159 } 160 161 162 void 163 poll_for_command_completion(struct mpi3mr_softc *sc, 164 struct mpi3mr_drvr_cmd *cmd, U16 wait) 165 { 166 int wait_time = wait * 1000; 167 while (wait_time) { 168 mpi3mr_complete_admin_cmd(sc); 169 if (cmd->state & MPI3MR_CMD_COMPLETE) 170 break; 171 DELAY(1000); 172 wait_time--; 173 } 174 } 175 176 /** 177 * mpi3mr_trigger_snapdump - triggers firmware snapdump 178 * @sc: Adapter instance reference 179 * @reason_code: reason code for the fault. 180 * 181 * This routine will trigger the snapdump and wait for it to 182 * complete or timeout before it returns. 183 * This will be called during initilaization time faults/resets/timeouts 184 * before soft reset invocation. 185 * 186 * Return: None. 187 */ 188 static void 189 mpi3mr_trigger_snapdump(struct mpi3mr_softc *sc, U32 reason_code) 190 { 191 U32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 192 193 mpi3mr_dprint(sc, MPI3MR_INFO, "snapdump triggered: reason code: %s\n", 194 mpi3mr_reset_rc_name(reason_code)); 195 196 mpi3mr_set_diagsave(sc); 197 mpi3mr_issue_reset(sc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 198 reason_code); 199 200 do { 201 host_diagnostic = mpi3mr_regread(sc, MPI3_SYSIF_HOST_DIAG_OFFSET); 202 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 203 break; 204 DELAY(100 * 1000); 205 } while (--timeout); 206 207 return; 208 } 209 210 /** 211 * mpi3mr_check_rh_fault_ioc - check reset history and fault 212 * controller 213 * @sc: Adapter instance reference 214 * @reason_code, reason code for the fault. 215 * 216 * This routine will fault the controller with 217 * the given reason code if it is not already in the fault or 218 * not asynchronosuly reset. This will be used to handle 219 * initilaization time faults/resets/timeout as in those cases 220 * immediate soft reset invocation is not required. 221 * 222 * Return: None. 223 */ 224 static void mpi3mr_check_rh_fault_ioc(struct mpi3mr_softc *sc, U32 reason_code) 225 { 226 U32 ioc_status; 227 228 if (sc->unrecoverable) { 229 mpi3mr_dprint(sc, MPI3MR_ERROR, "controller is unrecoverable\n"); 230 return; 231 } 232 233 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 234 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 235 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 236 mpi3mr_print_fault_info(sc); 237 return; 238 } 239 240 mpi3mr_trigger_snapdump(sc, reason_code); 241 242 return; 243 } 244 245 static void * mpi3mr_get_reply_virt_addr(struct mpi3mr_softc *sc, 246 bus_addr_t phys_addr) 247 { 248 if (!phys_addr) 249 return NULL; 250 if ((phys_addr < sc->reply_buf_dma_min_address) || 251 (phys_addr > sc->reply_buf_dma_max_address)) 252 return NULL; 253 254 return sc->reply_buf + (phys_addr - sc->reply_buf_phys); 255 } 256 257 static void * mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_softc *sc, 258 bus_addr_t phys_addr) 259 { 260 if (!phys_addr) 261 return NULL; 262 return sc->sense_buf + (phys_addr - sc->sense_buf_phys); 263 } 264 265 static void mpi3mr_repost_reply_buf(struct mpi3mr_softc *sc, 266 U64 reply_dma) 267 { 268 U32 old_idx = 0; 269 270 mtx_lock_spin(&sc->reply_free_q_lock); 271 old_idx = sc->reply_free_q_host_index; 272 sc->reply_free_q_host_index = ((sc->reply_free_q_host_index == 273 (sc->reply_free_q_sz - 1)) ? 0 : 274 (sc->reply_free_q_host_index + 1)); 275 sc->reply_free_q[old_idx] = reply_dma; 276 mpi3mr_regwrite(sc, MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET, 277 sc->reply_free_q_host_index); 278 mtx_unlock_spin(&sc->reply_free_q_lock); 279 } 280 281 static void mpi3mr_repost_sense_buf(struct mpi3mr_softc *sc, 282 U64 sense_buf_phys) 283 { 284 U32 old_idx = 0; 285 286 mtx_lock_spin(&sc->sense_buf_q_lock); 287 old_idx = sc->sense_buf_q_host_index; 288 sc->sense_buf_q_host_index = ((sc->sense_buf_q_host_index == 289 (sc->sense_buf_q_sz - 1)) ? 0 : 290 (sc->sense_buf_q_host_index + 1)); 291 sc->sense_buf_q[old_idx] = sense_buf_phys; 292 mpi3mr_regwrite(sc, MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET, 293 sc->sense_buf_q_host_index); 294 mtx_unlock_spin(&sc->sense_buf_q_lock); 295 296 } 297 298 void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc, 299 struct mpi3mr_throttle_group_info *tg, U8 divert_value) 300 { 301 struct mpi3mr_target *target; 302 303 mtx_lock_spin(&sc->target_lock); 304 TAILQ_FOREACH(target, &sc->cam_sc->tgt_list, tgt_next) { 305 if (target->throttle_group == tg) 306 target->io_divert = divert_value; 307 } 308 mtx_unlock_spin(&sc->target_lock); 309 } 310 311 /** 312 * mpi3mr_submit_admin_cmd - Submit request to admin queue 313 * @mrioc: Adapter reference 314 * @admin_req: MPI3 request 315 * @admin_req_sz: Request size 316 * 317 * Post the MPI3 request into admin request queue and 318 * inform the controller, if the queue is full return 319 * appropriate error. 320 * 321 * Return: 0 on success, non-zero on failure. 322 */ 323 int mpi3mr_submit_admin_cmd(struct mpi3mr_softc *sc, void *admin_req, 324 U16 admin_req_sz) 325 { 326 U16 areq_pi = 0, areq_ci = 0, max_entries = 0; 327 int retval = 0; 328 U8 *areq_entry; 329 330 mtx_lock_spin(&sc->admin_req_lock); 331 areq_pi = sc->admin_req_pi; 332 areq_ci = sc->admin_req_ci; 333 max_entries = sc->num_admin_reqs; 334 335 if (sc->unrecoverable) 336 return -EFAULT; 337 338 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 339 (areq_pi == (max_entries - 1)))) { 340 printf(IOCNAME "AdminReqQ full condition detected\n", 341 sc->name); 342 retval = -EAGAIN; 343 goto out; 344 } 345 areq_entry = (U8 *)sc->admin_req + (areq_pi * 346 MPI3MR_AREQ_FRAME_SZ); 347 memset(areq_entry, 0, MPI3MR_AREQ_FRAME_SZ); 348 memcpy(areq_entry, (U8 *)admin_req, admin_req_sz); 349 350 if (++areq_pi == max_entries) 351 areq_pi = 0; 352 sc->admin_req_pi = areq_pi; 353 354 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET, sc->admin_req_pi); 355 356 out: 357 mtx_unlock_spin(&sc->admin_req_lock); 358 return retval; 359 } 360 361 /** 362 * mpi3mr_check_req_qfull - Check request queue is full or not 363 * @op_req_q: Operational reply queue info 364 * 365 * Return: true when queue full, false otherwise. 366 */ 367 static inline bool 368 mpi3mr_check_req_qfull(struct mpi3mr_op_req_queue *op_req_q) 369 { 370 U16 pi, ci, max_entries; 371 bool is_qfull = false; 372 373 pi = op_req_q->pi; 374 ci = op_req_q->ci; 375 max_entries = op_req_q->num_reqs; 376 377 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 378 is_qfull = true; 379 380 return is_qfull; 381 } 382 383 /** 384 * mpi3mr_submit_io - Post IO command to firmware 385 * @sc: Adapter instance reference 386 * @op_req_q: Operational Request queue reference 387 * @req: MPT request data 388 * 389 * This function submits IO command to firmware. 390 * 391 * Return: Nothing 392 */ 393 int mpi3mr_submit_io(struct mpi3mr_softc *sc, 394 struct mpi3mr_op_req_queue *op_req_q, U8 *req) 395 { 396 U16 pi, max_entries; 397 int retval = 0; 398 U8 *req_entry; 399 U16 req_sz = sc->facts.op_req_sz; 400 struct mpi3mr_irq_context *irq_ctx; 401 402 mtx_lock_spin(&op_req_q->q_lock); 403 404 pi = op_req_q->pi; 405 max_entries = op_req_q->num_reqs; 406 if (mpi3mr_check_req_qfull(op_req_q)) { 407 irq_ctx = &sc->irq_ctx[op_req_q->reply_qid - 1]; 408 mpi3mr_complete_io_cmd(sc, irq_ctx); 409 410 if (mpi3mr_check_req_qfull(op_req_q)) { 411 printf(IOCNAME "OpReqQ full condition detected\n", 412 sc->name); 413 retval = -EBUSY; 414 goto out; 415 } 416 } 417 418 req_entry = (U8 *)op_req_q->q_base + (pi * req_sz); 419 memset(req_entry, 0, req_sz); 420 memcpy(req_entry, req, MPI3MR_AREQ_FRAME_SZ); 421 if (++pi == max_entries) 422 pi = 0; 423 op_req_q->pi = pi; 424 425 mpi3mr_atomic_inc(&sc->op_reply_q[op_req_q->reply_qid - 1].pend_ios); 426 427 mpi3mr_regwrite(sc, MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(op_req_q->qid), op_req_q->pi); 428 if (sc->mpi3mr_debug & MPI3MR_TRACE) { 429 device_printf(sc->mpi3mr_dev, "IO submission: QID:%d PI:0x%x\n", op_req_q->qid, op_req_q->pi); 430 mpi3mr_hexdump(req_entry, MPI3MR_AREQ_FRAME_SZ, 8); 431 } 432 433 out: 434 mtx_unlock_spin(&op_req_q->q_lock); 435 return retval; 436 } 437 438 inline void 439 mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length, 440 bus_addr_t dma_addr) 441 { 442 Mpi3SGESimple_t *sgel = paddr; 443 444 sgel->Flags = flags; 445 sgel->Length = (length); 446 sgel->Address = (U64)dma_addr; 447 } 448 449 void mpi3mr_build_zero_len_sge(void *paddr) 450 { 451 U8 sgl_flags = (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | 452 MPI3_SGE_FLAGS_DLAS_SYSTEM | MPI3_SGE_FLAGS_END_OF_LIST); 453 454 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 455 456 } 457 458 void mpi3mr_enable_interrupts(struct mpi3mr_softc *sc) 459 { 460 sc->intr_enabled = 1; 461 } 462 463 void mpi3mr_disable_interrupts(struct mpi3mr_softc *sc) 464 { 465 sc->intr_enabled = 0; 466 } 467 468 void 469 mpi3mr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 470 { 471 bus_addr_t *addr; 472 473 addr = arg; 474 *addr = segs[0].ds_addr; 475 } 476 477 static int mpi3mr_delete_op_reply_queue(struct mpi3mr_softc *sc, U16 qid) 478 { 479 Mpi3DeleteReplyQueueRequest_t delq_req; 480 struct mpi3mr_op_reply_queue *op_reply_q; 481 int retval = 0; 482 483 484 op_reply_q = &sc->op_reply_q[qid - 1]; 485 486 if (!op_reply_q->qid) 487 { 488 retval = -1; 489 printf(IOCNAME "Issue DelRepQ: called with invalid Reply QID\n", 490 sc->name); 491 goto out; 492 } 493 494 memset(&delq_req, 0, sizeof(delq_req)); 495 496 mtx_lock(&sc->init_cmds.completion.lock); 497 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 498 retval = -1; 499 printf(IOCNAME "Issue DelRepQ: Init command is in use\n", 500 sc->name); 501 mtx_unlock(&sc->init_cmds.completion.lock); 502 goto out; 503 } 504 505 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 506 retval = -1; 507 printf(IOCNAME "Issue DelRepQ: Init command is in use\n", 508 sc->name); 509 goto out; 510 } 511 sc->init_cmds.state = MPI3MR_CMD_PENDING; 512 sc->init_cmds.is_waiting = 1; 513 sc->init_cmds.callback = NULL; 514 delq_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 515 delq_req.Function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 516 delq_req.QueueID = qid; 517 518 init_completion(&sc->init_cmds.completion); 519 retval = mpi3mr_submit_admin_cmd(sc, &delq_req, sizeof(delq_req)); 520 if (retval) { 521 printf(IOCNAME "Issue DelRepQ: Admin Post failed\n", 522 sc->name); 523 goto out_unlock; 524 } 525 wait_for_completion_timeout(&sc->init_cmds.completion, 526 (MPI3MR_INTADMCMD_TIMEOUT)); 527 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 528 printf(IOCNAME "Issue DelRepQ: command timed out\n", 529 sc->name); 530 mpi3mr_check_rh_fault_ioc(sc, 531 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 532 sc->unrecoverable = 1; 533 534 retval = -1; 535 goto out_unlock; 536 } 537 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 538 != MPI3_IOCSTATUS_SUCCESS ) { 539 printf(IOCNAME "Issue DelRepQ: Failed IOCStatus(0x%04x) " 540 " Loginfo(0x%08x) \n" , sc->name, 541 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 542 sc->init_cmds.ioc_loginfo); 543 retval = -1; 544 goto out_unlock; 545 } 546 sc->irq_ctx[qid - 1].op_reply_q = NULL; 547 548 if (sc->op_reply_q[qid - 1].q_base_phys != 0) 549 bus_dmamap_unload(sc->op_reply_q[qid - 1].q_base_tag, sc->op_reply_q[qid - 1].q_base_dmamap); 550 if (sc->op_reply_q[qid - 1].q_base != NULL) 551 bus_dmamem_free(sc->op_reply_q[qid - 1].q_base_tag, sc->op_reply_q[qid - 1].q_base, sc->op_reply_q[qid - 1].q_base_dmamap); 552 if (sc->op_reply_q[qid - 1].q_base_tag != NULL) 553 bus_dma_tag_destroy(sc->op_reply_q[qid - 1].q_base_tag); 554 555 sc->op_reply_q[qid - 1].q_base = NULL; 556 sc->op_reply_q[qid - 1].qid = 0; 557 out_unlock: 558 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 559 mtx_unlock(&sc->init_cmds.completion.lock); 560 out: 561 return retval; 562 } 563 564 /** 565 * mpi3mr_create_op_reply_queue - create operational reply queue 566 * @sc: Adapter instance reference 567 * @qid: operational reply queue id 568 * 569 * Create operatinal reply queue by issuing MPI request 570 * through admin queue. 571 * 572 * Return: 0 on success, non-zero on failure. 573 */ 574 static int mpi3mr_create_op_reply_queue(struct mpi3mr_softc *sc, U16 qid) 575 { 576 Mpi3CreateReplyQueueRequest_t create_req; 577 struct mpi3mr_op_reply_queue *op_reply_q; 578 int retval = 0; 579 char q_lock_name[32]; 580 581 op_reply_q = &sc->op_reply_q[qid - 1]; 582 583 if (op_reply_q->qid) 584 { 585 retval = -1; 586 printf(IOCNAME "CreateRepQ: called for duplicate qid %d\n", 587 sc->name, op_reply_q->qid); 588 return retval; 589 } 590 591 op_reply_q->ci = 0; 592 if (pci_get_revid(sc->mpi3mr_dev) == SAS4116_CHIP_REV_A0) 593 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD_A0; 594 else 595 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 596 597 op_reply_q->qsz = op_reply_q->num_replies * sc->op_reply_sz; 598 op_reply_q->ephase = 1; 599 600 if (!op_reply_q->q_base) { 601 snprintf(q_lock_name, 32, "Reply Queue Lock[%d]", qid); 602 mtx_init(&op_reply_q->q_lock, q_lock_name, NULL, MTX_SPIN); 603 604 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 605 4, 0, /* algnmnt, boundary */ 606 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 607 BUS_SPACE_MAXADDR, /* highaddr */ 608 NULL, NULL, /* filter, filterarg */ 609 op_reply_q->qsz, /* maxsize */ 610 1, /* nsegments */ 611 op_reply_q->qsz, /* maxsegsize */ 612 0, /* flags */ 613 NULL, NULL, /* lockfunc, lockarg */ 614 &op_reply_q->q_base_tag)) { 615 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate Operational reply DMA tag\n"); 616 return (ENOMEM); 617 } 618 619 if (bus_dmamem_alloc(op_reply_q->q_base_tag, (void **)&op_reply_q->q_base, 620 BUS_DMA_NOWAIT, &op_reply_q->q_base_dmamap)) { 621 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 622 return (ENOMEM); 623 } 624 bzero(op_reply_q->q_base, op_reply_q->qsz); 625 bus_dmamap_load(op_reply_q->q_base_tag, op_reply_q->q_base_dmamap, op_reply_q->q_base, op_reply_q->qsz, 626 mpi3mr_memaddr_cb, &op_reply_q->q_base_phys, 0); 627 mpi3mr_dprint(sc, MPI3MR_XINFO, "Operational Reply queue ID: %d phys addr= %#016jx virt_addr: %pa size= %d\n", 628 qid, (uintmax_t)op_reply_q->q_base_phys, op_reply_q->q_base, op_reply_q->qsz); 629 630 if (!op_reply_q->q_base) 631 { 632 retval = -1; 633 printf(IOCNAME "CreateRepQ: memory alloc failed for qid %d\n", 634 sc->name, qid); 635 goto out; 636 } 637 } 638 639 memset(&create_req, 0, sizeof(create_req)); 640 641 mtx_lock(&sc->init_cmds.completion.lock); 642 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 643 retval = -1; 644 printf(IOCNAME "CreateRepQ: Init command is in use\n", 645 sc->name); 646 mtx_unlock(&sc->init_cmds.completion.lock); 647 goto out; 648 } 649 650 sc->init_cmds.state = MPI3MR_CMD_PENDING; 651 sc->init_cmds.is_waiting = 1; 652 sc->init_cmds.callback = NULL; 653 create_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 654 create_req.Function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 655 create_req.QueueID = qid; 656 create_req.Flags = MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 657 create_req.MSIxIndex = sc->irq_ctx[qid - 1].msix_index; 658 create_req.BaseAddress = (U64)op_reply_q->q_base_phys; 659 create_req.Size = op_reply_q->num_replies; 660 661 init_completion(&sc->init_cmds.completion); 662 retval = mpi3mr_submit_admin_cmd(sc, &create_req, 663 sizeof(create_req)); 664 if (retval) { 665 printf(IOCNAME "CreateRepQ: Admin Post failed\n", 666 sc->name); 667 goto out_unlock; 668 } 669 670 wait_for_completion_timeout(&sc->init_cmds.completion, 671 MPI3MR_INTADMCMD_TIMEOUT); 672 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 673 printf(IOCNAME "CreateRepQ: command timed out\n", 674 sc->name); 675 mpi3mr_check_rh_fault_ioc(sc, 676 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 677 sc->unrecoverable = 1; 678 retval = -1; 679 goto out_unlock; 680 } 681 682 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 683 != MPI3_IOCSTATUS_SUCCESS ) { 684 printf(IOCNAME "CreateRepQ: Failed IOCStatus(0x%04x) " 685 " Loginfo(0x%08x) \n" , sc->name, 686 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 687 sc->init_cmds.ioc_loginfo); 688 retval = -1; 689 goto out_unlock; 690 } 691 op_reply_q->qid = qid; 692 sc->irq_ctx[qid - 1].op_reply_q = op_reply_q; 693 694 out_unlock: 695 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 696 mtx_unlock(&sc->init_cmds.completion.lock); 697 out: 698 if (retval) { 699 if (op_reply_q->q_base_phys != 0) 700 bus_dmamap_unload(op_reply_q->q_base_tag, op_reply_q->q_base_dmamap); 701 if (op_reply_q->q_base != NULL) 702 bus_dmamem_free(op_reply_q->q_base_tag, op_reply_q->q_base, op_reply_q->q_base_dmamap); 703 if (op_reply_q->q_base_tag != NULL) 704 bus_dma_tag_destroy(op_reply_q->q_base_tag); 705 op_reply_q->q_base = NULL; 706 op_reply_q->qid = 0; 707 } 708 709 return retval; 710 } 711 712 /** 713 * mpi3mr_create_op_req_queue - create operational request queue 714 * @sc: Adapter instance reference 715 * @req_qid: operational request queue id 716 * @reply_qid: Reply queue ID 717 * 718 * Create operatinal request queue by issuing MPI request 719 * through admin queue. 720 * 721 * Return: 0 on success, non-zero on failure. 722 */ 723 static int mpi3mr_create_op_req_queue(struct mpi3mr_softc *sc, U16 req_qid, U8 reply_qid) 724 { 725 Mpi3CreateRequestQueueRequest_t create_req; 726 struct mpi3mr_op_req_queue *op_req_q; 727 int retval = 0; 728 char q_lock_name[32]; 729 730 op_req_q = &sc->op_req_q[req_qid - 1]; 731 732 if (op_req_q->qid) 733 { 734 retval = -1; 735 printf(IOCNAME "CreateReqQ: called for duplicate qid %d\n", 736 sc->name, op_req_q->qid); 737 return retval; 738 } 739 740 op_req_q->ci = 0; 741 op_req_q->pi = 0; 742 op_req_q->num_reqs = MPI3MR_OP_REQ_Q_QD; 743 op_req_q->qsz = op_req_q->num_reqs * sc->facts.op_req_sz; 744 op_req_q->reply_qid = reply_qid; 745 746 if (!op_req_q->q_base) { 747 snprintf(q_lock_name, 32, "Request Queue Lock[%d]", req_qid); 748 mtx_init(&op_req_q->q_lock, q_lock_name, NULL, MTX_SPIN); 749 750 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 751 4, 0, /* algnmnt, boundary */ 752 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 753 BUS_SPACE_MAXADDR, /* highaddr */ 754 NULL, NULL, /* filter, filterarg */ 755 op_req_q->qsz, /* maxsize */ 756 1, /* nsegments */ 757 op_req_q->qsz, /* maxsegsize */ 758 0, /* flags */ 759 NULL, NULL, /* lockfunc, lockarg */ 760 &op_req_q->q_base_tag)) { 761 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 762 return (ENOMEM); 763 } 764 765 if (bus_dmamem_alloc(op_req_q->q_base_tag, (void **)&op_req_q->q_base, 766 BUS_DMA_NOWAIT, &op_req_q->q_base_dmamap)) { 767 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 768 return (ENOMEM); 769 } 770 771 bzero(op_req_q->q_base, op_req_q->qsz); 772 773 bus_dmamap_load(op_req_q->q_base_tag, op_req_q->q_base_dmamap, op_req_q->q_base, op_req_q->qsz, 774 mpi3mr_memaddr_cb, &op_req_q->q_base_phys, 0); 775 776 mpi3mr_dprint(sc, MPI3MR_XINFO, "Operational Request QID: %d phys addr= %#016jx virt addr= %pa size= %d associated Reply QID: %d\n", 777 req_qid, (uintmax_t)op_req_q->q_base_phys, op_req_q->q_base, op_req_q->qsz, reply_qid); 778 779 if (!op_req_q->q_base) { 780 retval = -1; 781 printf(IOCNAME "CreateReqQ: memory alloc failed for qid %d\n", 782 sc->name, req_qid); 783 goto out; 784 } 785 } 786 787 memset(&create_req, 0, sizeof(create_req)); 788 789 mtx_lock(&sc->init_cmds.completion.lock); 790 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 791 retval = -1; 792 printf(IOCNAME "CreateReqQ: Init command is in use\n", 793 sc->name); 794 mtx_unlock(&sc->init_cmds.completion.lock); 795 goto out; 796 } 797 798 sc->init_cmds.state = MPI3MR_CMD_PENDING; 799 sc->init_cmds.is_waiting = 1; 800 sc->init_cmds.callback = NULL; 801 create_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 802 create_req.Function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 803 create_req.QueueID = req_qid; 804 create_req.Flags = 0; 805 create_req.ReplyQueueID = reply_qid; 806 create_req.BaseAddress = (U64)op_req_q->q_base_phys; 807 create_req.Size = op_req_q->num_reqs; 808 809 init_completion(&sc->init_cmds.completion); 810 retval = mpi3mr_submit_admin_cmd(sc, &create_req, 811 sizeof(create_req)); 812 if (retval) { 813 printf(IOCNAME "CreateReqQ: Admin Post failed\n", 814 sc->name); 815 goto out_unlock; 816 } 817 818 wait_for_completion_timeout(&sc->init_cmds.completion, 819 (MPI3MR_INTADMCMD_TIMEOUT)); 820 821 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 822 printf(IOCNAME "CreateReqQ: command timed out\n", 823 sc->name); 824 mpi3mr_check_rh_fault_ioc(sc, 825 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT); 826 sc->unrecoverable = 1; 827 retval = -1; 828 goto out_unlock; 829 } 830 831 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 832 != MPI3_IOCSTATUS_SUCCESS ) { 833 printf(IOCNAME "CreateReqQ: Failed IOCStatus(0x%04x) " 834 " Loginfo(0x%08x) \n" , sc->name, 835 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 836 sc->init_cmds.ioc_loginfo); 837 retval = -1; 838 goto out_unlock; 839 } 840 op_req_q->qid = req_qid; 841 842 out_unlock: 843 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 844 mtx_unlock(&sc->init_cmds.completion.lock); 845 out: 846 if (retval) { 847 if (op_req_q->q_base_phys != 0) 848 bus_dmamap_unload(op_req_q->q_base_tag, op_req_q->q_base_dmamap); 849 if (op_req_q->q_base != NULL) 850 bus_dmamem_free(op_req_q->q_base_tag, op_req_q->q_base, op_req_q->q_base_dmamap); 851 if (op_req_q->q_base_tag != NULL) 852 bus_dma_tag_destroy(op_req_q->q_base_tag); 853 op_req_q->q_base = NULL; 854 op_req_q->qid = 0; 855 } 856 return retval; 857 } 858 859 /** 860 * mpi3mr_create_op_queues - create operational queues 861 * @sc: Adapter instance reference 862 * 863 * Create operatinal queues(request queues and reply queues). 864 * Return: 0 on success, non-zero on failure. 865 */ 866 static int mpi3mr_create_op_queues(struct mpi3mr_softc *sc) 867 { 868 int retval = 0; 869 U16 num_queues = 0, i = 0, qid; 870 871 num_queues = min(sc->facts.max_op_reply_q, 872 sc->facts.max_op_req_q); 873 num_queues = min(num_queues, sc->msix_count); 874 875 /* 876 * During reset set the num_queues to the number of queues 877 * that was set before the reset. 878 */ 879 if (sc->num_queues) 880 num_queues = sc->num_queues; 881 882 mpi3mr_dprint(sc, MPI3MR_XINFO, "Trying to create %d Operational Q pairs\n", 883 num_queues); 884 885 if (!sc->op_req_q) { 886 sc->op_req_q = malloc(sizeof(struct mpi3mr_op_req_queue) * 887 num_queues, M_MPI3MR, M_NOWAIT | M_ZERO); 888 889 if (!sc->op_req_q) { 890 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to alloc memory for Request queue info\n"); 891 retval = -1; 892 goto out_failed; 893 } 894 } 895 896 if (!sc->op_reply_q) { 897 sc->op_reply_q = malloc(sizeof(struct mpi3mr_op_reply_queue) * num_queues, 898 M_MPI3MR, M_NOWAIT | M_ZERO); 899 900 if (!sc->op_reply_q) { 901 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to alloc memory for Reply queue info\n"); 902 retval = -1; 903 goto out_failed; 904 } 905 } 906 907 sc->num_hosttag_op_req_q = (sc->max_host_ios + 1) / num_queues; 908 909 /*Operational Request and reply queue ID starts with 1*/ 910 for (i = 0; i < num_queues; i++) { 911 qid = i + 1; 912 if (mpi3mr_create_op_reply_queue(sc, qid)) { 913 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to create Reply queue %d\n", 914 qid); 915 break; 916 } 917 if (mpi3mr_create_op_req_queue(sc, qid, 918 sc->op_reply_q[qid - 1].qid)) { 919 mpi3mr_delete_op_reply_queue(sc, qid); 920 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to create Request queue %d\n", 921 qid); 922 break; 923 } 924 925 } 926 927 /* Not even one queue is created successfully*/ 928 if (i == 0) { 929 retval = -1; 930 goto out_failed; 931 } 932 933 if (!sc->num_queues) { 934 sc->num_queues = i; 935 } else { 936 if (num_queues != i) { 937 mpi3mr_dprint(sc, MPI3MR_ERROR, "Number of queues (%d) post reset are not same as" 938 "queues allocated (%d) during driver init\n", i, num_queues); 939 goto out_failed; 940 } 941 } 942 943 mpi3mr_dprint(sc, MPI3MR_INFO, "Successfully created %d Operational Queue pairs\n", 944 sc->num_queues); 945 mpi3mr_dprint(sc, MPI3MR_INFO, "Request Queue QD: %d Reply queue QD: %d\n", 946 sc->op_req_q[0].num_reqs, sc->op_reply_q[0].num_replies); 947 948 return retval; 949 out_failed: 950 if (sc->op_req_q) { 951 free(sc->op_req_q, M_MPI3MR); 952 sc->op_req_q = NULL; 953 } 954 if (sc->op_reply_q) { 955 free(sc->op_reply_q, M_MPI3MR); 956 sc->op_reply_q = NULL; 957 } 958 return retval; 959 } 960 961 /** 962 * mpi3mr_setup_admin_qpair - Setup admin queue pairs 963 * @sc: Adapter instance reference 964 * 965 * Allocation and setup admin queues(request queues and reply queues). 966 * Return: 0 on success, non-zero on failure. 967 */ 968 static int mpi3mr_setup_admin_qpair(struct mpi3mr_softc *sc) 969 { 970 int retval = 0; 971 U32 num_adm_entries = 0; 972 973 sc->admin_req_q_sz = MPI3MR_AREQQ_SIZE; 974 sc->num_admin_reqs = sc->admin_req_q_sz / MPI3MR_AREQ_FRAME_SZ; 975 sc->admin_req_ci = sc->admin_req_pi = 0; 976 977 sc->admin_reply_q_sz = MPI3MR_AREPQ_SIZE; 978 sc->num_admin_replies = sc->admin_reply_q_sz/ MPI3MR_AREP_FRAME_SZ; 979 sc->admin_reply_ci = 0; 980 sc->admin_reply_ephase = 1; 981 982 if (!sc->admin_req) { 983 /* 984 * We need to create the tag for the admin queue to get the 985 * iofacts to see how many bits the controller decodes. Solve 986 * this chicken and egg problem by only doing lower 4GB DMA. 987 */ 988 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 989 4, 0, /* algnmnt, boundary */ 990 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 991 BUS_SPACE_MAXADDR, /* highaddr */ 992 NULL, NULL, /* filter, filterarg */ 993 sc->admin_req_q_sz, /* maxsize */ 994 1, /* nsegments */ 995 sc->admin_req_q_sz, /* maxsegsize */ 996 0, /* flags */ 997 NULL, NULL, /* lockfunc, lockarg */ 998 &sc->admin_req_tag)) { 999 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 1000 return (ENOMEM); 1001 } 1002 1003 if (bus_dmamem_alloc(sc->admin_req_tag, (void **)&sc->admin_req, 1004 BUS_DMA_NOWAIT, &sc->admin_req_dmamap)) { 1005 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 1006 return (ENOMEM); 1007 } 1008 bzero(sc->admin_req, sc->admin_req_q_sz); 1009 bus_dmamap_load(sc->admin_req_tag, sc->admin_req_dmamap, sc->admin_req, sc->admin_req_q_sz, 1010 mpi3mr_memaddr_cb, &sc->admin_req_phys, 0); 1011 mpi3mr_dprint(sc, MPI3MR_XINFO, "Admin Req queue phys addr= %#016jx size= %d\n", 1012 (uintmax_t)sc->admin_req_phys, sc->admin_req_q_sz); 1013 1014 if (!sc->admin_req) 1015 { 1016 retval = -1; 1017 printf(IOCNAME "Memory alloc for AdminReqQ: failed\n", 1018 sc->name); 1019 goto out_failed; 1020 } 1021 } 1022 1023 if (!sc->admin_reply) { 1024 mtx_init(&sc->admin_reply_lock, "Admin Reply Queue Lock", NULL, MTX_SPIN); 1025 1026 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1027 4, 0, /* algnmnt, boundary */ 1028 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1029 BUS_SPACE_MAXADDR, /* highaddr */ 1030 NULL, NULL, /* filter, filterarg */ 1031 sc->admin_reply_q_sz, /* maxsize */ 1032 1, /* nsegments */ 1033 sc->admin_reply_q_sz, /* maxsegsize */ 1034 0, /* flags */ 1035 NULL, NULL, /* lockfunc, lockarg */ 1036 &sc->admin_reply_tag)) { 1037 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate reply DMA tag\n"); 1038 return (ENOMEM); 1039 } 1040 1041 if (bus_dmamem_alloc(sc->admin_reply_tag, (void **)&sc->admin_reply, 1042 BUS_DMA_NOWAIT, &sc->admin_reply_dmamap)) { 1043 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 1044 return (ENOMEM); 1045 } 1046 bzero(sc->admin_reply, sc->admin_reply_q_sz); 1047 bus_dmamap_load(sc->admin_reply_tag, sc->admin_reply_dmamap, sc->admin_reply, sc->admin_reply_q_sz, 1048 mpi3mr_memaddr_cb, &sc->admin_reply_phys, 0); 1049 mpi3mr_dprint(sc, MPI3MR_XINFO, "Admin Reply queue phys addr= %#016jx size= %d\n", 1050 (uintmax_t)sc->admin_reply_phys, sc->admin_req_q_sz); 1051 1052 1053 if (!sc->admin_reply) 1054 { 1055 retval = -1; 1056 printf(IOCNAME "Memory alloc for AdminRepQ: failed\n", 1057 sc->name); 1058 goto out_failed; 1059 } 1060 } 1061 1062 num_adm_entries = (sc->num_admin_replies << 16) | 1063 (sc->num_admin_reqs); 1064 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET, num_adm_entries); 1065 mpi3mr_regwrite64(sc, MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET, sc->admin_req_phys); 1066 mpi3mr_regwrite64(sc, MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET, sc->admin_reply_phys); 1067 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET, sc->admin_req_pi); 1068 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET, sc->admin_reply_ci); 1069 1070 return retval; 1071 1072 out_failed: 1073 /* Free Admin reply*/ 1074 if (sc->admin_reply_phys) 1075 bus_dmamap_unload(sc->admin_reply_tag, sc->admin_reply_dmamap); 1076 1077 if (sc->admin_reply != NULL) 1078 bus_dmamem_free(sc->admin_reply_tag, sc->admin_reply, 1079 sc->admin_reply_dmamap); 1080 1081 if (sc->admin_reply_tag != NULL) 1082 bus_dma_tag_destroy(sc->admin_reply_tag); 1083 1084 /* Free Admin request*/ 1085 if (sc->admin_req_phys) 1086 bus_dmamap_unload(sc->admin_req_tag, sc->admin_req_dmamap); 1087 1088 if (sc->admin_req != NULL) 1089 bus_dmamem_free(sc->admin_req_tag, sc->admin_req, 1090 sc->admin_req_dmamap); 1091 1092 if (sc->admin_req_tag != NULL) 1093 bus_dma_tag_destroy(sc->admin_req_tag); 1094 1095 return retval; 1096 } 1097 1098 /** 1099 * mpi3mr_print_fault_info - Display fault information 1100 * @sc: Adapter instance reference 1101 * 1102 * Display the controller fault information if there is a 1103 * controller fault. 1104 * 1105 * Return: Nothing. 1106 */ 1107 static void mpi3mr_print_fault_info(struct mpi3mr_softc *sc) 1108 { 1109 U32 ioc_status, code, code1, code2, code3; 1110 1111 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1112 1113 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1114 code = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_OFFSET) & 1115 MPI3_SYSIF_FAULT_CODE_MASK; 1116 code1 = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_INFO0_OFFSET); 1117 code2 = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_INFO1_OFFSET); 1118 code3 = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_INFO2_OFFSET); 1119 printf(IOCNAME "fault codes 0x%04x:0x%04x:0x%04x:0x%04x\n", 1120 sc->name, code, code1, code2, code3); 1121 } 1122 } 1123 1124 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc) 1125 { 1126 U32 ioc_status, ioc_control; 1127 U8 ready, enabled; 1128 1129 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1130 ioc_control = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1131 1132 if(sc->unrecoverable) 1133 return MRIOC_STATE_UNRECOVERABLE; 1134 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 1135 return MRIOC_STATE_FAULT; 1136 1137 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 1138 enabled = (ioc_control & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 1139 1140 if (ready && enabled) 1141 return MRIOC_STATE_READY; 1142 if ((!ready) && (!enabled)) 1143 return MRIOC_STATE_RESET; 1144 if ((!ready) && (enabled)) 1145 return MRIOC_STATE_BECOMING_READY; 1146 1147 return MRIOC_STATE_RESET_REQUESTED; 1148 } 1149 1150 static inline void mpi3mr_clear_resethistory(struct mpi3mr_softc *sc) 1151 { 1152 U32 ioc_status; 1153 1154 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1155 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1156 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_STATUS_OFFSET, ioc_status); 1157 1158 } 1159 1160 /** 1161 * mpi3mr_mur_ioc - Message unit Reset handler 1162 * @sc: Adapter instance reference 1163 * @reset_reason: Reset reason code 1164 * 1165 * Issue Message unit Reset to the controller and wait for it to 1166 * be complete. 1167 * 1168 * Return: 0 on success, -1 on failure. 1169 */ 1170 static int mpi3mr_mur_ioc(struct mpi3mr_softc *sc, U32 reset_reason) 1171 { 1172 U32 ioc_config, timeout, ioc_status; 1173 int retval = -1; 1174 1175 mpi3mr_dprint(sc, MPI3MR_INFO, "Issuing Message Unit Reset(MUR)\n"); 1176 if (sc->unrecoverable) { 1177 mpi3mr_dprint(sc, MPI3MR_ERROR, "IOC is unrecoverable MUR not issued\n"); 1178 return retval; 1179 } 1180 mpi3mr_clear_resethistory(sc); 1181 mpi3mr_regwrite(sc, MPI3_SYSIF_SCRATCHPAD0_OFFSET, reset_reason); 1182 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1183 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1184 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 1185 1186 timeout = MPI3MR_MUR_TIMEOUT * 10; 1187 do { 1188 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1189 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 1190 mpi3mr_clear_resethistory(sc); 1191 ioc_config = 1192 mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1193 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1194 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1195 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) { 1196 retval = 0; 1197 break; 1198 } 1199 } 1200 DELAY(100 * 1000); 1201 } while (--timeout); 1202 1203 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1204 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1205 1206 mpi3mr_dprint(sc, MPI3MR_INFO, "IOC Status/Config after %s MUR is (0x%x)/(0x%x)\n", 1207 !retval ? "successful":"failed", ioc_status, ioc_config); 1208 return retval; 1209 } 1210 1211 /** 1212 * mpi3mr_bring_ioc_ready - Bring controller to ready state 1213 * @sc: Adapter instance reference 1214 * 1215 * Set Enable IOC bit in IOC configuration register and wait for 1216 * the controller to become ready. 1217 * 1218 * Return: 0 on success, appropriate error on failure. 1219 */ 1220 static int mpi3mr_bring_ioc_ready(struct mpi3mr_softc *sc) 1221 { 1222 U32 ioc_config, timeout; 1223 enum mpi3mr_iocstate current_state; 1224 1225 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1226 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1227 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 1228 1229 timeout = sc->ready_timeout * 10; 1230 do { 1231 current_state = mpi3mr_get_iocstate(sc); 1232 if (current_state == MRIOC_STATE_READY) 1233 return 0; 1234 DELAY(100 * 1000); 1235 } while (--timeout); 1236 1237 return -1; 1238 } 1239 1240 static const struct { 1241 enum mpi3mr_iocstate value; 1242 char *name; 1243 } mrioc_states[] = { 1244 { MRIOC_STATE_READY, "ready" }, 1245 { MRIOC_STATE_FAULT, "fault" }, 1246 { MRIOC_STATE_RESET, "reset" }, 1247 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 1248 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 1249 { MRIOC_STATE_COUNT, "Count" }, 1250 }; 1251 1252 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 1253 { 1254 int i; 1255 char *name = NULL; 1256 1257 for (i = 0; i < MRIOC_STATE_COUNT; i++) { 1258 if (mrioc_states[i].value == mrioc_state){ 1259 name = mrioc_states[i].name; 1260 break; 1261 } 1262 } 1263 return name; 1264 } 1265 1266 /* Reset reason to name mapper structure*/ 1267 static const struct { 1268 enum mpi3mr_reset_reason value; 1269 char *name; 1270 } mpi3mr_reset_reason_codes[] = { 1271 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" }, 1272 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" }, 1273 { MPI3MR_RESET_FROM_IOCTL, "application" }, 1274 { MPI3MR_RESET_FROM_EH_HOS, "error handling" }, 1275 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" }, 1276 { MPI3MR_RESET_FROM_IOCTL_TIMEOUT, "IOCTL timeout" }, 1277 { MPI3MR_RESET_FROM_SCSIIO_TIMEOUT, "SCSIIO timeout" }, 1278 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" }, 1279 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" }, 1280 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" }, 1281 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" }, 1282 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" }, 1283 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" }, 1284 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" }, 1285 { 1286 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT, 1287 "create request queue timeout" 1288 }, 1289 { 1290 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT, 1291 "create reply queue timeout" 1292 }, 1293 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" }, 1294 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" }, 1295 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" }, 1296 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" }, 1297 { 1298 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1299 "component image activation timeout" 1300 }, 1301 { 1302 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT, 1303 "get package version timeout" 1304 }, 1305 { 1306 MPI3MR_RESET_FROM_PELABORT_TIMEOUT, 1307 "persistent event log abort timeout" 1308 }, 1309 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" }, 1310 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" }, 1311 { 1312 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT, 1313 "diagnostic buffer post timeout" 1314 }, 1315 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronus reset" }, 1316 { MPI3MR_RESET_REASON_COUNT, "Reset reason count" }, 1317 }; 1318 1319 /** 1320 * mpi3mr_reset_rc_name - get reset reason code name 1321 * @reason_code: reset reason code value 1322 * 1323 * Map reset reason to an NULL terminated ASCII string 1324 * 1325 * Return: Name corresponding to reset reason value or NULL. 1326 */ 1327 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code) 1328 { 1329 int i; 1330 char *name = NULL; 1331 1332 for (i = 0; i < MPI3MR_RESET_REASON_COUNT; i++) { 1333 if (mpi3mr_reset_reason_codes[i].value == reason_code) { 1334 name = mpi3mr_reset_reason_codes[i].name; 1335 break; 1336 } 1337 } 1338 return name; 1339 } 1340 1341 #define MAX_RESET_TYPE 3 1342 /* Reset type to name mapper structure*/ 1343 static const struct { 1344 U16 reset_type; 1345 char *name; 1346 } mpi3mr_reset_types[] = { 1347 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" }, 1348 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" }, 1349 { MAX_RESET_TYPE, "count"} 1350 }; 1351 1352 /** 1353 * mpi3mr_reset_type_name - get reset type name 1354 * @reset_type: reset type value 1355 * 1356 * Map reset type to an NULL terminated ASCII string 1357 * 1358 * Return: Name corresponding to reset type value or NULL. 1359 */ 1360 static const char *mpi3mr_reset_type_name(U16 reset_type) 1361 { 1362 int i; 1363 char *name = NULL; 1364 1365 for (i = 0; i < MAX_RESET_TYPE; i++) { 1366 if (mpi3mr_reset_types[i].reset_type == reset_type) { 1367 name = mpi3mr_reset_types[i].name; 1368 break; 1369 } 1370 } 1371 return name; 1372 } 1373 1374 /** 1375 * mpi3mr_soft_reset_success - Check softreset is success or not 1376 * @ioc_status: IOC status register value 1377 * @ioc_config: IOC config register value 1378 * 1379 * Check whether the soft reset is successful or not based on 1380 * IOC status and IOC config register values. 1381 * 1382 * Return: True when the soft reset is success, false otherwise. 1383 */ 1384 static inline bool 1385 mpi3mr_soft_reset_success(U32 ioc_status, U32 ioc_config) 1386 { 1387 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1388 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1389 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1390 return true; 1391 return false; 1392 } 1393 1394 /** 1395 * mpi3mr_diagfault_success - Check diag fault is success or not 1396 * @sc: Adapter reference 1397 * @ioc_status: IOC status register value 1398 * 1399 * Check whether the controller hit diag reset fault code. 1400 * 1401 * Return: True when there is diag fault, false otherwise. 1402 */ 1403 static inline bool mpi3mr_diagfault_success(struct mpi3mr_softc *sc, 1404 U32 ioc_status) 1405 { 1406 U32 fault; 1407 1408 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) 1409 return false; 1410 fault = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_OFFSET) & MPI3_SYSIF_FAULT_CODE_MASK; 1411 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) 1412 return true; 1413 return false; 1414 } 1415 1416 /** 1417 * mpi3mr_issue_iocfacts - Send IOC Facts 1418 * @sc: Adapter instance reference 1419 * @facts_data: Cached IOC facts data 1420 * 1421 * Issue IOC Facts MPI request through admin queue and wait for 1422 * the completion of it or time out. 1423 * 1424 * Return: 0 on success, non-zero on failures. 1425 */ 1426 static int mpi3mr_issue_iocfacts(struct mpi3mr_softc *sc, 1427 Mpi3IOCFactsData_t *facts_data) 1428 { 1429 Mpi3IOCFactsRequest_t iocfacts_req; 1430 bus_dma_tag_t data_tag = NULL; 1431 bus_dmamap_t data_map = NULL; 1432 bus_addr_t data_phys = 0; 1433 void *data = NULL; 1434 U32 data_len = sizeof(*facts_data); 1435 int retval = 0; 1436 1437 U8 sgl_flags = (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | 1438 MPI3_SGE_FLAGS_DLAS_SYSTEM | 1439 MPI3_SGE_FLAGS_END_OF_LIST); 1440 1441 1442 /* 1443 * We can't use sc->dma_loaddr / hiaddr here. We set those only after 1444 * we get the iocfacts. So allocate in the lower 4GB. The amount of 1445 * data is tiny and we don't do this that often, so any bouncing we 1446 * might have to do isn't a cause for concern. 1447 */ 1448 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1449 4, 0, /* algnmnt, boundary */ 1450 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1451 BUS_SPACE_MAXADDR, /* highaddr */ 1452 NULL, NULL, /* filter, filterarg */ 1453 data_len, /* maxsize */ 1454 1, /* nsegments */ 1455 data_len, /* maxsegsize */ 1456 0, /* flags */ 1457 NULL, NULL, /* lockfunc, lockarg */ 1458 &data_tag)) { 1459 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 1460 return (ENOMEM); 1461 } 1462 1463 if (bus_dmamem_alloc(data_tag, (void **)&data, 1464 BUS_DMA_NOWAIT, &data_map)) { 1465 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d Data DMA mem alloc failed\n", 1466 __func__, __LINE__); 1467 return (ENOMEM); 1468 } 1469 1470 bzero(data, data_len); 1471 bus_dmamap_load(data_tag, data_map, data, data_len, 1472 mpi3mr_memaddr_cb, &data_phys, 0); 1473 mpi3mr_dprint(sc, MPI3MR_XINFO, "Func: %s line: %d IOCfacts data phys addr= %#016jx size= %d\n", 1474 __func__, __LINE__, (uintmax_t)data_phys, data_len); 1475 1476 if (!data) 1477 { 1478 retval = -1; 1479 printf(IOCNAME "Memory alloc for IOCFactsData: failed\n", 1480 sc->name); 1481 goto out; 1482 } 1483 1484 mtx_lock(&sc->init_cmds.completion.lock); 1485 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 1486 1487 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 1488 retval = -1; 1489 printf(IOCNAME "Issue IOCFacts: Init command is in use\n", 1490 sc->name); 1491 mtx_unlock(&sc->init_cmds.completion.lock); 1492 goto out; 1493 } 1494 1495 sc->init_cmds.state = MPI3MR_CMD_PENDING; 1496 sc->init_cmds.is_waiting = 1; 1497 sc->init_cmds.callback = NULL; 1498 iocfacts_req.HostTag = (MPI3MR_HOSTTAG_INITCMDS); 1499 iocfacts_req.Function = MPI3_FUNCTION_IOC_FACTS; 1500 1501 mpi3mr_add_sg_single(&iocfacts_req.SGL, sgl_flags, data_len, 1502 data_phys); 1503 1504 init_completion(&sc->init_cmds.completion); 1505 1506 retval = mpi3mr_submit_admin_cmd(sc, &iocfacts_req, 1507 sizeof(iocfacts_req)); 1508 1509 if (retval) { 1510 printf(IOCNAME "Issue IOCFacts: Admin Post failed\n", 1511 sc->name); 1512 goto out_unlock; 1513 } 1514 1515 wait_for_completion_timeout(&sc->init_cmds.completion, 1516 (MPI3MR_INTADMCMD_TIMEOUT)); 1517 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1518 printf(IOCNAME "Issue IOCFacts: command timed out\n", 1519 sc->name); 1520 mpi3mr_check_rh_fault_ioc(sc, 1521 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 1522 sc->unrecoverable = 1; 1523 retval = -1; 1524 goto out_unlock; 1525 } 1526 1527 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1528 != MPI3_IOCSTATUS_SUCCESS ) { 1529 printf(IOCNAME "Issue IOCFacts: Failed IOCStatus(0x%04x) " 1530 " Loginfo(0x%08x) \n" , sc->name, 1531 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1532 sc->init_cmds.ioc_loginfo); 1533 retval = -1; 1534 goto out_unlock; 1535 } 1536 1537 memcpy(facts_data, (U8 *)data, data_len); 1538 out_unlock: 1539 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1540 mtx_unlock(&sc->init_cmds.completion.lock); 1541 1542 out: 1543 if (data_phys != 0) 1544 bus_dmamap_unload(data_tag, data_map); 1545 if (data != NULL) 1546 bus_dmamem_free(data_tag, data, data_map); 1547 if (data_tag != NULL) 1548 bus_dma_tag_destroy(data_tag); 1549 return retval; 1550 } 1551 1552 /** 1553 * mpi3mr_process_factsdata - Process IOC facts data 1554 * @sc: Adapter instance reference 1555 * @facts_data: Cached IOC facts data 1556 * 1557 * Convert IOC facts data into cpu endianness and cache it in 1558 * the driver . 1559 * 1560 * Return: Nothing. 1561 */ 1562 static int mpi3mr_process_factsdata(struct mpi3mr_softc *sc, 1563 Mpi3IOCFactsData_t *facts_data) 1564 { 1565 int retval = 0; 1566 U32 ioc_config, req_sz, facts_flags; 1567 1568 if (le16toh(facts_data->IOCFactsDataLength) != 1569 (sizeof(*facts_data) / 4)) { 1570 mpi3mr_dprint(sc, MPI3MR_INFO, "IOCFacts data length mismatch " 1571 " driver_sz(%ld) firmware_sz(%d) \n", 1572 sizeof(*facts_data), 1573 facts_data->IOCFactsDataLength); 1574 } 1575 1576 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1577 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 1578 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 1579 1580 if (facts_data->IOCRequestFrameSize != (req_sz/4)) { 1581 mpi3mr_dprint(sc, MPI3MR_INFO, "IOCFacts data reqFrameSize mismatch " 1582 " hw_size(%d) firmware_sz(%d) \n" , req_sz/4, 1583 facts_data->IOCRequestFrameSize); 1584 } 1585 1586 memset(&sc->facts, 0, sizeof(sc->facts)); 1587 1588 facts_flags = le32toh(facts_data->Flags); 1589 sc->facts.op_req_sz = req_sz; 1590 sc->op_reply_sz = 1 << ((ioc_config & 1591 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 1592 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 1593 1594 sc->facts.ioc_num = facts_data->IOCNumber; 1595 sc->facts.who_init = facts_data->WhoInit; 1596 sc->facts.max_msix_vectors = facts_data->MaxMSIxVectors; 1597 sc->facts.personality = (facts_flags & 1598 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 1599 sc->facts.dma_mask = (facts_flags & 1600 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 1601 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 1602 sc->facts.protocol_flags = facts_data->ProtocolFlags; 1603 sc->facts.mpi_version = (facts_data->MPIVersion.Word); 1604 sc->facts.max_reqs = (facts_data->MaxOutstandingRequests); 1605 sc->facts.product_id = (facts_data->ProductID); 1606 sc->facts.reply_sz = (facts_data->ReplyFrameSize) * 4; 1607 sc->facts.exceptions = (facts_data->IOCExceptions); 1608 sc->facts.max_perids = (facts_data->MaxPersistentID); 1609 sc->facts.max_vds = (facts_data->MaxVDs); 1610 sc->facts.max_hpds = (facts_data->MaxHostPDs); 1611 sc->facts.max_advhpds = (facts_data->MaxAdvHostPDs); 1612 sc->facts.max_raidpds = (facts_data->MaxRAIDPDs); 1613 sc->facts.max_nvme = (facts_data->MaxNVMe); 1614 sc->facts.max_pcieswitches = 1615 (facts_data->MaxPCIeSwitches); 1616 sc->facts.max_sasexpanders = 1617 (facts_data->MaxSASExpanders); 1618 sc->facts.max_sasinitiators = 1619 (facts_data->MaxSASInitiators); 1620 sc->facts.max_enclosures = (facts_data->MaxEnclosures); 1621 sc->facts.min_devhandle = (facts_data->MinDevHandle); 1622 sc->facts.max_devhandle = (facts_data->MaxDevHandle); 1623 sc->facts.max_op_req_q = 1624 (facts_data->MaxOperationalRequestQueues); 1625 sc->facts.max_op_reply_q = 1626 (facts_data->MaxOperationalReplyQueues); 1627 sc->facts.ioc_capabilities = 1628 (facts_data->IOCCapabilities); 1629 sc->facts.fw_ver.build_num = 1630 (facts_data->FWVersion.BuildNum); 1631 sc->facts.fw_ver.cust_id = 1632 (facts_data->FWVersion.CustomerID); 1633 sc->facts.fw_ver.ph_minor = facts_data->FWVersion.PhaseMinor; 1634 sc->facts.fw_ver.ph_major = facts_data->FWVersion.PhaseMajor; 1635 sc->facts.fw_ver.gen_minor = facts_data->FWVersion.GenMinor; 1636 sc->facts.fw_ver.gen_major = facts_data->FWVersion.GenMajor; 1637 sc->max_msix_vectors = min(sc->max_msix_vectors, 1638 sc->facts.max_msix_vectors); 1639 sc->facts.sge_mod_mask = facts_data->SGEModifierMask; 1640 sc->facts.sge_mod_value = facts_data->SGEModifierValue; 1641 sc->facts.sge_mod_shift = facts_data->SGEModifierShift; 1642 sc->facts.shutdown_timeout = 1643 (facts_data->ShutdownTimeout); 1644 sc->facts.max_dev_per_tg = facts_data->MaxDevicesPerThrottleGroup; 1645 sc->facts.io_throttle_data_length = 1646 facts_data->IOThrottleDataLength; 1647 sc->facts.max_io_throttle_group = 1648 facts_data->MaxIOThrottleGroup; 1649 sc->facts.io_throttle_low = facts_data->IOThrottleLow; 1650 sc->facts.io_throttle_high = facts_data->IOThrottleHigh; 1651 1652 /*Store in 512b block count*/ 1653 if (sc->facts.io_throttle_data_length) 1654 sc->io_throttle_data_length = 1655 (sc->facts.io_throttle_data_length * 2 * 4); 1656 else 1657 /* set the length to 1MB + 1K to disable throttle*/ 1658 sc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2; 1659 1660 sc->io_throttle_high = (sc->facts.io_throttle_high * 2 * 1024); 1661 sc->io_throttle_low = (sc->facts.io_throttle_low * 2 * 1024); 1662 1663 mpi3mr_dprint(sc, MPI3MR_INFO, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d)," 1664 "maxreqs(%d), mindh(%d) maxPDs(%d) maxvectors(%d) maxperids(%d)\n", 1665 sc->facts.ioc_num, sc->facts.max_op_req_q, 1666 sc->facts.max_op_reply_q, sc->facts.max_devhandle, 1667 sc->facts.max_reqs, sc->facts.min_devhandle, 1668 sc->facts.max_pds, sc->facts.max_msix_vectors, 1669 sc->facts.max_perids); 1670 mpi3mr_dprint(sc, MPI3MR_INFO, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x\n", 1671 sc->facts.sge_mod_mask, sc->facts.sge_mod_value, 1672 sc->facts.sge_mod_shift); 1673 mpi3mr_dprint(sc, MPI3MR_INFO, 1674 "max_dev_per_throttle_group(%d), max_throttle_groups(%d), io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n", 1675 sc->facts.max_dev_per_tg, sc->facts.max_io_throttle_group, 1676 sc->facts.io_throttle_data_length * 4, 1677 sc->facts.io_throttle_high, sc->facts.io_throttle_low); 1678 1679 sc->max_host_ios = sc->facts.max_reqs - 1680 (MPI3MR_INTERNALCMDS_RESVD + 1); 1681 1682 /* 1683 * Set the DMA mask for the card. dma_mask is the number of bits that 1684 * can have bits set in them. Translate this into bus_dma loaddr/hiaddr 1685 * args. Add sanity for more bits than address space or other overflow 1686 * situations. 1687 */ 1688 if (sc->facts.dma_mask == 0 || 1689 (sc->facts.dma_mask >= sizeof(bus_addr_t) * 8)) 1690 sc->dma_loaddr = BUS_SPACE_MAXADDR; 1691 else 1692 sc->dma_loaddr = ~((1ull << sc->facts.dma_mask) - 1); 1693 sc->dma_hiaddr = BUS_SPACE_MAXADDR; 1694 mpi3mr_dprint(sc, MPI3MR_INFO, 1695 "dma_mask bits: %d loaddr 0x%jx hiaddr 0x%jx\n", 1696 sc->facts.dma_mask, sc->dma_loaddr, sc->dma_hiaddr); 1697 1698 return retval; 1699 } 1700 1701 static inline void mpi3mr_setup_reply_free_queues(struct mpi3mr_softc *sc) 1702 { 1703 int i; 1704 bus_addr_t phys_addr; 1705 1706 /* initialize Reply buffer Queue */ 1707 for (i = 0, phys_addr = sc->reply_buf_phys; 1708 i < sc->num_reply_bufs; i++, phys_addr += sc->reply_sz) 1709 sc->reply_free_q[i] = phys_addr; 1710 sc->reply_free_q[i] = (0); 1711 1712 /* initialize Sense Buffer Queue */ 1713 for (i = 0, phys_addr = sc->sense_buf_phys; 1714 i < sc->num_sense_bufs; i++, phys_addr += MPI3MR_SENSEBUF_SZ) 1715 sc->sense_buf_q[i] = phys_addr; 1716 sc->sense_buf_q[i] = (0); 1717 1718 } 1719 1720 static int mpi3mr_reply_dma_alloc(struct mpi3mr_softc *sc) 1721 { 1722 U32 sz; 1723 1724 sc->num_reply_bufs = sc->facts.max_reqs + MPI3MR_NUM_EVTREPLIES; 1725 sc->reply_free_q_sz = sc->num_reply_bufs + 1; 1726 sc->num_sense_bufs = sc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 1727 sc->sense_buf_q_sz = sc->num_sense_bufs + 1; 1728 1729 sz = sc->num_reply_bufs * sc->reply_sz; 1730 1731 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1732 16, 0, /* algnmnt, boundary */ 1733 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1734 BUS_SPACE_MAXADDR, /* highaddr */ 1735 NULL, NULL, /* filter, filterarg */ 1736 sz, /* maxsize */ 1737 1, /* nsegments */ 1738 sz, /* maxsegsize */ 1739 0, /* flags */ 1740 NULL, NULL, /* lockfunc, lockarg */ 1741 &sc->reply_buf_tag)) { 1742 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 1743 return (ENOMEM); 1744 } 1745 1746 if (bus_dmamem_alloc(sc->reply_buf_tag, (void **)&sc->reply_buf, 1747 BUS_DMA_NOWAIT, &sc->reply_buf_dmamap)) { 1748 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 1749 __func__, __LINE__); 1750 return (ENOMEM); 1751 } 1752 1753 bzero(sc->reply_buf, sz); 1754 bus_dmamap_load(sc->reply_buf_tag, sc->reply_buf_dmamap, sc->reply_buf, sz, 1755 mpi3mr_memaddr_cb, &sc->reply_buf_phys, 0); 1756 1757 sc->reply_buf_dma_min_address = sc->reply_buf_phys; 1758 sc->reply_buf_dma_max_address = sc->reply_buf_phys + sz; 1759 mpi3mr_dprint(sc, MPI3MR_XINFO, "reply buf (0x%p): depth(%d), frame_size(%d), " 1760 "pool_size(%d kB), reply_buf_dma(0x%llx)\n", 1761 sc->reply_buf, sc->num_reply_bufs, sc->reply_sz, 1762 (sz / 1024), (unsigned long long)sc->reply_buf_phys); 1763 1764 /* reply free queue, 8 byte align */ 1765 sz = sc->reply_free_q_sz * 8; 1766 1767 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1768 8, 0, /* algnmnt, boundary */ 1769 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1770 BUS_SPACE_MAXADDR, /* highaddr */ 1771 NULL, NULL, /* filter, filterarg */ 1772 sz, /* maxsize */ 1773 1, /* nsegments */ 1774 sz, /* maxsegsize */ 1775 0, /* flags */ 1776 NULL, NULL, /* lockfunc, lockarg */ 1777 &sc->reply_free_q_tag)) { 1778 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate reply free queue DMA tag\n"); 1779 return (ENOMEM); 1780 } 1781 1782 if (bus_dmamem_alloc(sc->reply_free_q_tag, (void **)&sc->reply_free_q, 1783 BUS_DMA_NOWAIT, &sc->reply_free_q_dmamap)) { 1784 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 1785 __func__, __LINE__); 1786 return (ENOMEM); 1787 } 1788 1789 bzero(sc->reply_free_q, sz); 1790 bus_dmamap_load(sc->reply_free_q_tag, sc->reply_free_q_dmamap, sc->reply_free_q, sz, 1791 mpi3mr_memaddr_cb, &sc->reply_free_q_phys, 0); 1792 1793 mpi3mr_dprint(sc, MPI3MR_XINFO, "reply_free_q (0x%p): depth(%d), frame_size(%d), " 1794 "pool_size(%d kB), reply_free_q_dma(0x%llx)\n", 1795 sc->reply_free_q, sc->reply_free_q_sz, 8, (sz / 1024), 1796 (unsigned long long)sc->reply_free_q_phys); 1797 1798 /* sense buffer pool, 4 byte align */ 1799 sz = sc->num_sense_bufs * MPI3MR_SENSEBUF_SZ; 1800 1801 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1802 4, 0, /* algnmnt, boundary */ 1803 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1804 BUS_SPACE_MAXADDR, /* highaddr */ 1805 NULL, NULL, /* filter, filterarg */ 1806 sz, /* maxsize */ 1807 1, /* nsegments */ 1808 sz, /* maxsegsize */ 1809 0, /* flags */ 1810 NULL, NULL, /* lockfunc, lockarg */ 1811 &sc->sense_buf_tag)) { 1812 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate Sense buffer DMA tag\n"); 1813 return (ENOMEM); 1814 } 1815 1816 if (bus_dmamem_alloc(sc->sense_buf_tag, (void **)&sc->sense_buf, 1817 BUS_DMA_NOWAIT, &sc->sense_buf_dmamap)) { 1818 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 1819 __func__, __LINE__); 1820 return (ENOMEM); 1821 } 1822 1823 bzero(sc->sense_buf, sz); 1824 bus_dmamap_load(sc->sense_buf_tag, sc->sense_buf_dmamap, sc->sense_buf, sz, 1825 mpi3mr_memaddr_cb, &sc->sense_buf_phys, 0); 1826 1827 mpi3mr_dprint(sc, MPI3MR_XINFO, "sense_buf (0x%p): depth(%d), frame_size(%d), " 1828 "pool_size(%d kB), sense_dma(0x%llx)\n", 1829 sc->sense_buf, sc->num_sense_bufs, MPI3MR_SENSEBUF_SZ, 1830 (sz / 1024), (unsigned long long)sc->sense_buf_phys); 1831 1832 /* sense buffer queue, 8 byte align */ 1833 sz = sc->sense_buf_q_sz * 8; 1834 1835 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1836 8, 0, /* algnmnt, boundary */ 1837 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1838 BUS_SPACE_MAXADDR, /* highaddr */ 1839 NULL, NULL, /* filter, filterarg */ 1840 sz, /* maxsize */ 1841 1, /* nsegments */ 1842 sz, /* maxsegsize */ 1843 0, /* flags */ 1844 NULL, NULL, /* lockfunc, lockarg */ 1845 &sc->sense_buf_q_tag)) { 1846 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate Sense buffer Queue DMA tag\n"); 1847 return (ENOMEM); 1848 } 1849 1850 if (bus_dmamem_alloc(sc->sense_buf_q_tag, (void **)&sc->sense_buf_q, 1851 BUS_DMA_NOWAIT, &sc->sense_buf_q_dmamap)) { 1852 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 1853 __func__, __LINE__); 1854 return (ENOMEM); 1855 } 1856 1857 bzero(sc->sense_buf_q, sz); 1858 bus_dmamap_load(sc->sense_buf_q_tag, sc->sense_buf_q_dmamap, sc->sense_buf_q, sz, 1859 mpi3mr_memaddr_cb, &sc->sense_buf_q_phys, 0); 1860 1861 mpi3mr_dprint(sc, MPI3MR_XINFO, "sense_buf_q (0x%p): depth(%d), frame_size(%d), " 1862 "pool_size(%d kB), sense_dma(0x%llx)\n", 1863 sc->sense_buf_q, sc->sense_buf_q_sz, 8, (sz / 1024), 1864 (unsigned long long)sc->sense_buf_q_phys); 1865 1866 return 0; 1867 } 1868 1869 static int mpi3mr_reply_alloc(struct mpi3mr_softc *sc) 1870 { 1871 int retval = 0; 1872 U32 i; 1873 1874 if (sc->init_cmds.reply) 1875 goto post_reply_sbuf; 1876 1877 sc->init_cmds.reply = malloc(sc->reply_sz, 1878 M_MPI3MR, M_NOWAIT | M_ZERO); 1879 1880 if (!sc->init_cmds.reply) { 1881 printf(IOCNAME "Cannot allocate memory for init_cmds.reply\n", 1882 sc->name); 1883 goto out_failed; 1884 } 1885 1886 sc->ioctl_cmds.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 1887 if (!sc->ioctl_cmds.reply) { 1888 printf(IOCNAME "Cannot allocate memory for ioctl_cmds.reply\n", 1889 sc->name); 1890 goto out_failed; 1891 } 1892 1893 sc->host_tm_cmds.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 1894 if (!sc->host_tm_cmds.reply) { 1895 printf(IOCNAME "Cannot allocate memory for host_tm.reply\n", 1896 sc->name); 1897 goto out_failed; 1898 } 1899 for (i=0; i<MPI3MR_NUM_DEVRMCMD; i++) { 1900 sc->dev_rmhs_cmds[i].reply = malloc(sc->reply_sz, 1901 M_MPI3MR, M_NOWAIT | M_ZERO); 1902 if (!sc->dev_rmhs_cmds[i].reply) { 1903 printf(IOCNAME "Cannot allocate memory for" 1904 " dev_rmhs_cmd[%d].reply\n", 1905 sc->name, i); 1906 goto out_failed; 1907 } 1908 } 1909 1910 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 1911 sc->evtack_cmds[i].reply = malloc(sc->reply_sz, 1912 M_MPI3MR, M_NOWAIT | M_ZERO); 1913 if (!sc->evtack_cmds[i].reply) 1914 goto out_failed; 1915 } 1916 1917 sc->dev_handle_bitmap_sz = MPI3MR_DIV_ROUND_UP(sc->facts.max_devhandle, 8); 1918 1919 sc->removepend_bitmap = malloc(sc->dev_handle_bitmap_sz, 1920 M_MPI3MR, M_NOWAIT | M_ZERO); 1921 if (!sc->removepend_bitmap) { 1922 printf(IOCNAME "Cannot alloc memory for remove pend bitmap\n", 1923 sc->name); 1924 goto out_failed; 1925 } 1926 1927 sc->devrem_bitmap_sz = MPI3MR_DIV_ROUND_UP(MPI3MR_NUM_DEVRMCMD, 8); 1928 sc->devrem_bitmap = malloc(sc->devrem_bitmap_sz, 1929 M_MPI3MR, M_NOWAIT | M_ZERO); 1930 if (!sc->devrem_bitmap) { 1931 printf(IOCNAME "Cannot alloc memory for dev remove bitmap\n", 1932 sc->name); 1933 goto out_failed; 1934 } 1935 1936 sc->evtack_cmds_bitmap_sz = MPI3MR_DIV_ROUND_UP(MPI3MR_NUM_EVTACKCMD, 8); 1937 1938 sc->evtack_cmds_bitmap = malloc(sc->evtack_cmds_bitmap_sz, 1939 M_MPI3MR, M_NOWAIT | M_ZERO); 1940 if (!sc->evtack_cmds_bitmap) 1941 goto out_failed; 1942 1943 if (mpi3mr_reply_dma_alloc(sc)) { 1944 printf(IOCNAME "func:%s line:%d DMA memory allocation failed\n", 1945 sc->name, __func__, __LINE__); 1946 goto out_failed; 1947 } 1948 1949 post_reply_sbuf: 1950 mpi3mr_setup_reply_free_queues(sc); 1951 return retval; 1952 out_failed: 1953 mpi3mr_cleanup_interrupts(sc); 1954 mpi3mr_free_mem(sc); 1955 retval = -1; 1956 return retval; 1957 } 1958 1959 static void 1960 mpi3mr_print_fw_pkg_ver(struct mpi3mr_softc *sc) 1961 { 1962 int retval = 0; 1963 void *fw_pkg_ver = NULL; 1964 bus_dma_tag_t fw_pkg_ver_tag; 1965 bus_dmamap_t fw_pkg_ver_map; 1966 bus_addr_t fw_pkg_ver_dma; 1967 Mpi3CIUploadRequest_t ci_upload; 1968 Mpi3ComponentImageHeader_t *ci_header; 1969 U32 fw_pkg_ver_len = sizeof(*ci_header); 1970 U8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 1971 1972 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1973 4, 0, /* algnmnt, boundary */ 1974 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1975 BUS_SPACE_MAXADDR, /* highaddr */ 1976 NULL, NULL, /* filter, filterarg */ 1977 fw_pkg_ver_len, /* maxsize */ 1978 1, /* nsegments */ 1979 fw_pkg_ver_len, /* maxsegsize */ 1980 0, /* flags */ 1981 NULL, NULL, /* lockfunc, lockarg */ 1982 &fw_pkg_ver_tag)) { 1983 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate fw package version request DMA tag\n"); 1984 return; 1985 } 1986 1987 if (bus_dmamem_alloc(fw_pkg_ver_tag, (void **)&fw_pkg_ver, BUS_DMA_NOWAIT, &fw_pkg_ver_map)) { 1988 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d fw package version DMA mem alloc failed\n", 1989 __func__, __LINE__); 1990 return; 1991 } 1992 1993 bzero(fw_pkg_ver, fw_pkg_ver_len); 1994 1995 bus_dmamap_load(fw_pkg_ver_tag, fw_pkg_ver_map, fw_pkg_ver, fw_pkg_ver_len, mpi3mr_memaddr_cb, &fw_pkg_ver_dma, 0); 1996 1997 mpi3mr_dprint(sc, MPI3MR_XINFO, "Func: %s line: %d fw package version phys addr= %#016jx size= %d\n", 1998 __func__, __LINE__, (uintmax_t)fw_pkg_ver_dma, fw_pkg_ver_len); 1999 2000 if (!fw_pkg_ver) { 2001 mpi3mr_dprint(sc, MPI3MR_ERROR, "Memory alloc for fw package version failed\n"); 2002 goto out; 2003 } 2004 2005 memset(&ci_upload, 0, sizeof(ci_upload)); 2006 mtx_lock(&sc->init_cmds.completion.lock); 2007 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 2008 mpi3mr_dprint(sc, MPI3MR_INFO,"Issue CI Header Upload: command is in use\n"); 2009 mtx_unlock(&sc->init_cmds.completion.lock); 2010 goto out; 2011 } 2012 sc->init_cmds.state = MPI3MR_CMD_PENDING; 2013 sc->init_cmds.is_waiting = 1; 2014 sc->init_cmds.callback = NULL; 2015 ci_upload.HostTag = htole16(MPI3MR_HOSTTAG_INITCMDS); 2016 ci_upload.Function = MPI3_FUNCTION_CI_UPLOAD; 2017 ci_upload.MsgFlags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY; 2018 ci_upload.ImageOffset = MPI3_IMAGE_HEADER_SIGNATURE0_OFFSET; 2019 ci_upload.SegmentSize = MPI3_IMAGE_HEADER_SIZE; 2020 2021 mpi3mr_add_sg_single(&ci_upload.SGL, sgl_flags, fw_pkg_ver_len, 2022 fw_pkg_ver_dma); 2023 2024 init_completion(&sc->init_cmds.completion); 2025 if ((retval = mpi3mr_submit_admin_cmd(sc, &ci_upload, sizeof(ci_upload)))) { 2026 mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue CI Header Upload: Admin Post failed\n"); 2027 goto out_unlock; 2028 } 2029 wait_for_completion_timeout(&sc->init_cmds.completion, 2030 (MPI3MR_INTADMCMD_TIMEOUT)); 2031 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2032 mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue CI Header Upload: command timed out\n"); 2033 sc->init_cmds.is_waiting = 0; 2034 if (!(sc->init_cmds.state & MPI3MR_CMD_RESET)) 2035 mpi3mr_check_rh_fault_ioc(sc, 2036 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT); 2037 goto out_unlock; 2038 } 2039 if ((GET_IOC_STATUS(sc->init_cmds.ioc_status)) != MPI3_IOCSTATUS_SUCCESS) { 2040 mpi3mr_dprint(sc, MPI3MR_ERROR, 2041 "Issue CI Header Upload: Failed IOCStatus(0x%04x) Loginfo(0x%08x)\n", 2042 GET_IOC_STATUS(sc->init_cmds.ioc_status), sc->init_cmds.ioc_loginfo); 2043 goto out_unlock; 2044 } 2045 2046 ci_header = (Mpi3ComponentImageHeader_t *) fw_pkg_ver; 2047 mpi3mr_dprint(sc, MPI3MR_XINFO, 2048 "Issue CI Header Upload:EnvVariableOffset(0x%x) \ 2049 HeaderSize(0x%x) Signature1(0x%x)\n", 2050 ci_header->EnvironmentVariableOffset, 2051 ci_header->HeaderSize, 2052 ci_header->Signature1); 2053 mpi3mr_dprint(sc, MPI3MR_INFO, "FW Package Version: %02d.%02d.%02d.%02d\n", 2054 ci_header->ComponentImageVersion.GenMajor, 2055 ci_header->ComponentImageVersion.GenMinor, 2056 ci_header->ComponentImageVersion.PhaseMajor, 2057 ci_header->ComponentImageVersion.PhaseMinor); 2058 out_unlock: 2059 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2060 mtx_unlock(&sc->init_cmds.completion.lock); 2061 2062 out: 2063 if (fw_pkg_ver_dma != 0) 2064 bus_dmamap_unload(fw_pkg_ver_tag, fw_pkg_ver_map); 2065 if (fw_pkg_ver) 2066 bus_dmamem_free(fw_pkg_ver_tag, fw_pkg_ver, fw_pkg_ver_map); 2067 if (fw_pkg_ver_tag) 2068 bus_dma_tag_destroy(fw_pkg_ver_tag); 2069 2070 } 2071 2072 /** 2073 * mpi3mr_issue_iocinit - Send IOC Init 2074 * @sc: Adapter instance reference 2075 * 2076 * Issue IOC Init MPI request through admin queue and wait for 2077 * the completion of it or time out. 2078 * 2079 * Return: 0 on success, non-zero on failures. 2080 */ 2081 static int mpi3mr_issue_iocinit(struct mpi3mr_softc *sc) 2082 { 2083 Mpi3IOCInitRequest_t iocinit_req; 2084 Mpi3DriverInfoLayout_t *drvr_info = NULL; 2085 bus_dma_tag_t drvr_info_tag; 2086 bus_dmamap_t drvr_info_map; 2087 bus_addr_t drvr_info_phys; 2088 U32 drvr_info_len = sizeof(*drvr_info); 2089 int retval = 0; 2090 struct timeval now; 2091 uint64_t time_in_msec; 2092 2093 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 2094 4, 0, /* algnmnt, boundary */ 2095 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2096 BUS_SPACE_MAXADDR, /* highaddr */ 2097 NULL, NULL, /* filter, filterarg */ 2098 drvr_info_len, /* maxsize */ 2099 1, /* nsegments */ 2100 drvr_info_len, /* maxsegsize */ 2101 0, /* flags */ 2102 NULL, NULL, /* lockfunc, lockarg */ 2103 &drvr_info_tag)) { 2104 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 2105 return (ENOMEM); 2106 } 2107 2108 if (bus_dmamem_alloc(drvr_info_tag, (void **)&drvr_info, 2109 BUS_DMA_NOWAIT, &drvr_info_map)) { 2110 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d Data DMA mem alloc failed\n", 2111 __func__, __LINE__); 2112 return (ENOMEM); 2113 } 2114 2115 bzero(drvr_info, drvr_info_len); 2116 bus_dmamap_load(drvr_info_tag, drvr_info_map, drvr_info, drvr_info_len, 2117 mpi3mr_memaddr_cb, &drvr_info_phys, 0); 2118 mpi3mr_dprint(sc, MPI3MR_XINFO, "Func: %s line: %d IOCfacts drvr_info phys addr= %#016jx size= %d\n", 2119 __func__, __LINE__, (uintmax_t)drvr_info_phys, drvr_info_len); 2120 2121 if (!drvr_info) 2122 { 2123 retval = -1; 2124 printf(IOCNAME "Memory alloc for Driver Info failed\n", 2125 sc->name); 2126 goto out; 2127 } 2128 drvr_info->InformationLength = (drvr_info_len); 2129 strcpy(drvr_info->DriverSignature, "Broadcom"); 2130 strcpy(drvr_info->OsName, "FreeBSD"); 2131 strcpy(drvr_info->OsVersion, fmt_os_ver); 2132 strcpy(drvr_info->DriverName, MPI3MR_DRIVER_NAME); 2133 strcpy(drvr_info->DriverVersion, MPI3MR_DRIVER_VERSION); 2134 strcpy(drvr_info->DriverReleaseDate, MPI3MR_DRIVER_RELDATE); 2135 drvr_info->DriverCapabilities = 0; 2136 memcpy((U8 *)&sc->driver_info, (U8 *)drvr_info, sizeof(sc->driver_info)); 2137 2138 memset(&iocinit_req, 0, sizeof(iocinit_req)); 2139 mtx_lock(&sc->init_cmds.completion.lock); 2140 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 2141 retval = -1; 2142 printf(IOCNAME "Issue IOCInit: Init command is in use\n", 2143 sc->name); 2144 mtx_unlock(&sc->init_cmds.completion.lock); 2145 goto out; 2146 } 2147 sc->init_cmds.state = MPI3MR_CMD_PENDING; 2148 sc->init_cmds.is_waiting = 1; 2149 sc->init_cmds.callback = NULL; 2150 iocinit_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 2151 iocinit_req.Function = MPI3_FUNCTION_IOC_INIT; 2152 iocinit_req.MPIVersion.Struct.Dev = MPI3_VERSION_DEV; 2153 iocinit_req.MPIVersion.Struct.Unit = MPI3_VERSION_UNIT; 2154 iocinit_req.MPIVersion.Struct.Major = MPI3_VERSION_MAJOR; 2155 iocinit_req.MPIVersion.Struct.Minor = MPI3_VERSION_MINOR; 2156 iocinit_req.WhoInit = MPI3_WHOINIT_HOST_DRIVER; 2157 iocinit_req.ReplyFreeQueueDepth = sc->reply_free_q_sz; 2158 iocinit_req.ReplyFreeQueueAddress = 2159 sc->reply_free_q_phys; 2160 iocinit_req.SenseBufferLength = MPI3MR_SENSEBUF_SZ; 2161 iocinit_req.SenseBufferFreeQueueDepth = 2162 sc->sense_buf_q_sz; 2163 iocinit_req.SenseBufferFreeQueueAddress = 2164 sc->sense_buf_q_phys; 2165 iocinit_req.DriverInformationAddress = drvr_info_phys; 2166 2167 getmicrotime(&now); 2168 time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000); 2169 iocinit_req.TimeStamp = htole64(time_in_msec); 2170 2171 init_completion(&sc->init_cmds.completion); 2172 retval = mpi3mr_submit_admin_cmd(sc, &iocinit_req, 2173 sizeof(iocinit_req)); 2174 2175 if (retval) { 2176 printf(IOCNAME "Issue IOCInit: Admin Post failed\n", 2177 sc->name); 2178 goto out_unlock; 2179 } 2180 2181 wait_for_completion_timeout(&sc->init_cmds.completion, 2182 (MPI3MR_INTADMCMD_TIMEOUT)); 2183 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2184 printf(IOCNAME "Issue IOCInit: command timed out\n", 2185 sc->name); 2186 mpi3mr_check_rh_fault_ioc(sc, 2187 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 2188 sc->unrecoverable = 1; 2189 retval = -1; 2190 goto out_unlock; 2191 } 2192 2193 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2194 != MPI3_IOCSTATUS_SUCCESS ) { 2195 printf(IOCNAME "Issue IOCInit: Failed IOCStatus(0x%04x) " 2196 " Loginfo(0x%08x) \n" , sc->name, 2197 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2198 sc->init_cmds.ioc_loginfo); 2199 retval = -1; 2200 goto out_unlock; 2201 } 2202 2203 out_unlock: 2204 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2205 mtx_unlock(&sc->init_cmds.completion.lock); 2206 2207 out: 2208 if (drvr_info_phys != 0) 2209 bus_dmamap_unload(drvr_info_tag, drvr_info_map); 2210 if (drvr_info != NULL) 2211 bus_dmamem_free(drvr_info_tag, drvr_info, drvr_info_map); 2212 if (drvr_info_tag != NULL) 2213 bus_dma_tag_destroy(drvr_info_tag); 2214 return retval; 2215 } 2216 2217 static void 2218 mpi3mr_display_ioc_info(struct mpi3mr_softc *sc) 2219 { 2220 int i = 0; 2221 char personality[16]; 2222 struct mpi3mr_compimg_ver *fwver = &sc->facts.fw_ver; 2223 2224 switch (sc->facts.personality) { 2225 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA: 2226 strcpy(personality, "Enhanced HBA"); 2227 break; 2228 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR: 2229 strcpy(personality, "RAID"); 2230 break; 2231 default: 2232 strcpy(personality, "Unknown"); 2233 break; 2234 } 2235 2236 mpi3mr_dprint(sc, MPI3MR_INFO, "Current Personality: %s\n", personality); 2237 2238 mpi3mr_dprint(sc, MPI3MR_INFO, "FW Version: %d.%d.%d.%d.%05d-%05d\n", 2239 fwver->gen_major, fwver->gen_minor, fwver->ph_major, 2240 fwver->ph_minor, fwver->cust_id, fwver->build_num); 2241 2242 mpi3mr_dprint(sc, MPI3MR_INFO, "Protocol=("); 2243 2244 if (sc->facts.protocol_flags & 2245 MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 2246 printf("Initiator"); 2247 i++; 2248 } 2249 2250 if (sc->facts.protocol_flags & 2251 MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET) { 2252 printf("%sTarget", i ? "," : ""); 2253 i++; 2254 } 2255 2256 if (sc->facts.protocol_flags & 2257 MPI3_IOCFACTS_PROTOCOL_NVME) { 2258 printf("%sNVMe attachment", i ? "," : ""); 2259 i++; 2260 } 2261 i = 0; 2262 printf("), "); 2263 printf("Capabilities=("); 2264 2265 if (sc->facts.ioc_capabilities & 2266 MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE) { 2267 printf("RAID"); 2268 i++; 2269 } 2270 2271 printf(")\n"); 2272 } 2273 2274 /** 2275 * mpi3mr_unmask_events - Unmask events in event mask bitmap 2276 * @sc: Adapter instance reference 2277 * @event: MPI event ID 2278 * 2279 * Un mask the specific event by resetting the event_mask 2280 * bitmap. 2281 * 2282 * Return: None. 2283 */ 2284 static void mpi3mr_unmask_events(struct mpi3mr_softc *sc, U16 event) 2285 { 2286 U32 desired_event; 2287 2288 if (event >= 128) 2289 return; 2290 2291 desired_event = (1 << (event % 32)); 2292 2293 if (event < 32) 2294 sc->event_masks[0] &= ~desired_event; 2295 else if (event < 64) 2296 sc->event_masks[1] &= ~desired_event; 2297 else if (event < 96) 2298 sc->event_masks[2] &= ~desired_event; 2299 else if (event < 128) 2300 sc->event_masks[3] &= ~desired_event; 2301 } 2302 2303 static void mpi3mr_set_events_mask(struct mpi3mr_softc *sc) 2304 { 2305 int i; 2306 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 2307 sc->event_masks[i] = -1; 2308 2309 mpi3mr_unmask_events(sc, MPI3_EVENT_DEVICE_ADDED); 2310 mpi3mr_unmask_events(sc, MPI3_EVENT_DEVICE_INFO_CHANGED); 2311 mpi3mr_unmask_events(sc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 2312 2313 mpi3mr_unmask_events(sc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 2314 2315 mpi3mr_unmask_events(sc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 2316 mpi3mr_unmask_events(sc, MPI3_EVENT_SAS_DISCOVERY); 2317 mpi3mr_unmask_events(sc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 2318 mpi3mr_unmask_events(sc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE); 2319 2320 mpi3mr_unmask_events(sc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 2321 mpi3mr_unmask_events(sc, MPI3_EVENT_PCIE_ENUMERATION); 2322 2323 mpi3mr_unmask_events(sc, MPI3_EVENT_PREPARE_FOR_RESET); 2324 mpi3mr_unmask_events(sc, MPI3_EVENT_CABLE_MGMT); 2325 mpi3mr_unmask_events(sc, MPI3_EVENT_ENERGY_PACK_CHANGE); 2326 } 2327 2328 /** 2329 * mpi3mr_issue_event_notification - Send event notification 2330 * @sc: Adapter instance reference 2331 * 2332 * Issue event notification MPI request through admin queue and 2333 * wait for the completion of it or time out. 2334 * 2335 * Return: 0 on success, non-zero on failures. 2336 */ 2337 int mpi3mr_issue_event_notification(struct mpi3mr_softc *sc) 2338 { 2339 Mpi3EventNotificationRequest_t evtnotify_req; 2340 int retval = 0; 2341 U8 i; 2342 2343 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 2344 mtx_lock(&sc->init_cmds.completion.lock); 2345 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 2346 retval = -1; 2347 printf(IOCNAME "Issue EvtNotify: Init command is in use\n", 2348 sc->name); 2349 mtx_unlock(&sc->init_cmds.completion.lock); 2350 goto out; 2351 } 2352 sc->init_cmds.state = MPI3MR_CMD_PENDING; 2353 sc->init_cmds.is_waiting = 1; 2354 sc->init_cmds.callback = NULL; 2355 evtnotify_req.HostTag = (MPI3MR_HOSTTAG_INITCMDS); 2356 evtnotify_req.Function = MPI3_FUNCTION_EVENT_NOTIFICATION; 2357 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 2358 evtnotify_req.EventMasks[i] = 2359 (sc->event_masks[i]); 2360 init_completion(&sc->init_cmds.completion); 2361 retval = mpi3mr_submit_admin_cmd(sc, &evtnotify_req, 2362 sizeof(evtnotify_req)); 2363 if (retval) { 2364 printf(IOCNAME "Issue EvtNotify: Admin Post failed\n", 2365 sc->name); 2366 goto out_unlock; 2367 } 2368 2369 poll_for_command_completion(sc, 2370 &sc->init_cmds, 2371 (MPI3MR_INTADMCMD_TIMEOUT)); 2372 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2373 printf(IOCNAME "Issue EvtNotify: command timed out\n", 2374 sc->name); 2375 mpi3mr_check_rh_fault_ioc(sc, 2376 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 2377 retval = -1; 2378 goto out_unlock; 2379 } 2380 2381 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2382 != MPI3_IOCSTATUS_SUCCESS ) { 2383 printf(IOCNAME "Issue EvtNotify: Failed IOCStatus(0x%04x) " 2384 " Loginfo(0x%08x) \n" , sc->name, 2385 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2386 sc->init_cmds.ioc_loginfo); 2387 retval = -1; 2388 goto out_unlock; 2389 } 2390 2391 out_unlock: 2392 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2393 mtx_unlock(&sc->init_cmds.completion.lock); 2394 2395 out: 2396 return retval; 2397 } 2398 2399 int 2400 mpi3mr_register_events(struct mpi3mr_softc *sc) 2401 { 2402 int error; 2403 2404 mpi3mr_set_events_mask(sc); 2405 2406 error = mpi3mr_issue_event_notification(sc); 2407 2408 if (error) { 2409 printf(IOCNAME "Failed to issue event notification %d\n", 2410 sc->name, error); 2411 } 2412 2413 return error; 2414 } 2415 2416 /** 2417 * mpi3mr_process_event_ack - Process event acknowledgment 2418 * @sc: Adapter instance reference 2419 * @event: MPI3 event ID 2420 * @event_ctx: Event context 2421 * 2422 * Send event acknowledgement through admin queue and wait for 2423 * it to complete. 2424 * 2425 * Return: 0 on success, non-zero on failures. 2426 */ 2427 int mpi3mr_process_event_ack(struct mpi3mr_softc *sc, U8 event, 2428 U32 event_ctx) 2429 { 2430 Mpi3EventAckRequest_t evtack_req; 2431 int retval = 0; 2432 2433 memset(&evtack_req, 0, sizeof(evtack_req)); 2434 mtx_lock(&sc->init_cmds.completion.lock); 2435 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 2436 retval = -1; 2437 printf(IOCNAME "Issue EvtAck: Init command is in use\n", 2438 sc->name); 2439 mtx_unlock(&sc->init_cmds.completion.lock); 2440 goto out; 2441 } 2442 sc->init_cmds.state = MPI3MR_CMD_PENDING; 2443 sc->init_cmds.is_waiting = 1; 2444 sc->init_cmds.callback = NULL; 2445 evtack_req.HostTag = htole16(MPI3MR_HOSTTAG_INITCMDS); 2446 evtack_req.Function = MPI3_FUNCTION_EVENT_ACK; 2447 evtack_req.Event = event; 2448 evtack_req.EventContext = htole32(event_ctx); 2449 2450 init_completion(&sc->init_cmds.completion); 2451 retval = mpi3mr_submit_admin_cmd(sc, &evtack_req, 2452 sizeof(evtack_req)); 2453 if (retval) { 2454 printf(IOCNAME "Issue EvtAck: Admin Post failed\n", 2455 sc->name); 2456 goto out_unlock; 2457 } 2458 2459 wait_for_completion_timeout(&sc->init_cmds.completion, 2460 (MPI3MR_INTADMCMD_TIMEOUT)); 2461 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2462 printf(IOCNAME "Issue EvtAck: command timed out\n", 2463 sc->name); 2464 retval = -1; 2465 goto out_unlock; 2466 } 2467 2468 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2469 != MPI3_IOCSTATUS_SUCCESS ) { 2470 printf(IOCNAME "Issue EvtAck: Failed IOCStatus(0x%04x) " 2471 " Loginfo(0x%08x) \n" , sc->name, 2472 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2473 sc->init_cmds.ioc_loginfo); 2474 retval = -1; 2475 goto out_unlock; 2476 } 2477 2478 out_unlock: 2479 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2480 mtx_unlock(&sc->init_cmds.completion.lock); 2481 2482 out: 2483 return retval; 2484 } 2485 2486 2487 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_softc *sc) 2488 { 2489 int retval = 0; 2490 U32 sz, i; 2491 U16 num_chains; 2492 2493 num_chains = sc->max_host_ios; 2494 2495 sc->chain_buf_count = num_chains; 2496 sz = sizeof(struct mpi3mr_chain) * num_chains; 2497 2498 sc->chain_sgl_list = malloc(sz, M_MPI3MR, M_NOWAIT | M_ZERO); 2499 2500 if (!sc->chain_sgl_list) { 2501 printf(IOCNAME "Cannot allocate memory for chain SGL list\n", 2502 sc->name); 2503 retval = -1; 2504 goto out_failed; 2505 } 2506 2507 sz = MPI3MR_CHAINSGE_SIZE; 2508 2509 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 2510 4096, 0, /* algnmnt, boundary */ 2511 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2512 BUS_SPACE_MAXADDR, /* highaddr */ 2513 NULL, NULL, /* filter, filterarg */ 2514 sz, /* maxsize */ 2515 1, /* nsegments */ 2516 sz, /* maxsegsize */ 2517 0, /* flags */ 2518 NULL, NULL, /* lockfunc, lockarg */ 2519 &sc->chain_sgl_list_tag)) { 2520 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate Chain buffer DMA tag\n"); 2521 return (ENOMEM); 2522 } 2523 2524 for (i = 0; i < num_chains; i++) { 2525 if (bus_dmamem_alloc(sc->chain_sgl_list_tag, (void **)&sc->chain_sgl_list[i].buf, 2526 BUS_DMA_NOWAIT, &sc->chain_sgl_list[i].buf_dmamap)) { 2527 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 2528 __func__, __LINE__); 2529 return (ENOMEM); 2530 } 2531 2532 bzero(sc->chain_sgl_list[i].buf, sz); 2533 bus_dmamap_load(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf_dmamap, sc->chain_sgl_list[i].buf, sz, 2534 mpi3mr_memaddr_cb, &sc->chain_sgl_list[i].buf_phys, 0); 2535 mpi3mr_dprint(sc, MPI3MR_XINFO, "Func: %s line: %d phys addr= %#016jx size= %d\n", 2536 __func__, __LINE__, (uintmax_t)sc->chain_sgl_list[i].buf_phys, sz); 2537 } 2538 2539 sc->chain_bitmap_sz = MPI3MR_DIV_ROUND_UP(num_chains, 8); 2540 2541 sc->chain_bitmap = malloc(sc->chain_bitmap_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 2542 if (!sc->chain_bitmap) { 2543 mpi3mr_dprint(sc, MPI3MR_INFO, "Cannot alloc memory for chain bitmap\n"); 2544 retval = -1; 2545 goto out_failed; 2546 } 2547 return retval; 2548 2549 out_failed: 2550 for (i = 0; i < num_chains; i++) { 2551 if (sc->chain_sgl_list[i].buf_phys != 0) 2552 bus_dmamap_unload(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf_dmamap); 2553 if (sc->chain_sgl_list[i].buf != NULL) 2554 bus_dmamem_free(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf, sc->chain_sgl_list[i].buf_dmamap); 2555 } 2556 if (sc->chain_sgl_list_tag != NULL) 2557 bus_dma_tag_destroy(sc->chain_sgl_list_tag); 2558 return retval; 2559 } 2560 2561 static int mpi3mr_pel_alloc(struct mpi3mr_softc *sc) 2562 { 2563 int retval = 0; 2564 2565 if (!sc->pel_cmds.reply) { 2566 sc->pel_cmds.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 2567 if (!sc->pel_cmds.reply) { 2568 printf(IOCNAME "Cannot allocate memory for pel_cmds.reply\n", 2569 sc->name); 2570 goto out_failed; 2571 } 2572 } 2573 2574 if (!sc->pel_abort_cmd.reply) { 2575 sc->pel_abort_cmd.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 2576 if (!sc->pel_abort_cmd.reply) { 2577 printf(IOCNAME "Cannot allocate memory for pel_abort_cmd.reply\n", 2578 sc->name); 2579 goto out_failed; 2580 } 2581 } 2582 2583 if (!sc->pel_seq_number) { 2584 sc->pel_seq_number_sz = sizeof(Mpi3PELSeq_t); 2585 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 2586 4, 0, /* alignment, boundary */ 2587 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2588 BUS_SPACE_MAXADDR, /* highaddr */ 2589 NULL, NULL, /* filter, filterarg */ 2590 sc->pel_seq_number_sz, /* maxsize */ 2591 1, /* nsegments */ 2592 sc->pel_seq_number_sz, /* maxsegsize */ 2593 0, /* flags */ 2594 NULL, NULL, /* lockfunc, lockarg */ 2595 &sc->pel_seq_num_dmatag)) { 2596 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot create PEL seq number dma memory tag\n"); 2597 retval = -ENOMEM; 2598 goto out_failed; 2599 } 2600 2601 if (bus_dmamem_alloc(sc->pel_seq_num_dmatag, (void **)&sc->pel_seq_number, 2602 BUS_DMA_NOWAIT, &sc->pel_seq_num_dmamap)) { 2603 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate PEL seq number kernel buffer dma memory\n"); 2604 retval = -ENOMEM; 2605 goto out_failed; 2606 } 2607 2608 bzero(sc->pel_seq_number, sc->pel_seq_number_sz); 2609 2610 bus_dmamap_load(sc->pel_seq_num_dmatag, sc->pel_seq_num_dmamap, sc->pel_seq_number, 2611 sc->pel_seq_number_sz, mpi3mr_memaddr_cb, &sc->pel_seq_number_dma, 0); 2612 2613 if (!sc->pel_seq_number) { 2614 printf(IOCNAME "%s:%d Cannot load PEL seq number dma memory for size: %d\n", sc->name, 2615 __func__, __LINE__, sc->pel_seq_number_sz); 2616 retval = -ENOMEM; 2617 goto out_failed; 2618 } 2619 } 2620 2621 out_failed: 2622 return retval; 2623 } 2624 2625 /** 2626 * mpi3mr_validate_fw_update - validate IOCFacts post adapter reset 2627 * @sc: Adapter instance reference 2628 * 2629 * Return zero if the new IOCFacts is compatible with previous values 2630 * else return appropriate error 2631 */ 2632 static int 2633 mpi3mr_validate_fw_update(struct mpi3mr_softc *sc) 2634 { 2635 U16 dev_handle_bitmap_sz; 2636 U8 *removepend_bitmap; 2637 2638 if (sc->facts.reply_sz > sc->reply_sz) { 2639 mpi3mr_dprint(sc, MPI3MR_ERROR, 2640 "Cannot increase reply size from %d to %d\n", 2641 sc->reply_sz, sc->reply_sz); 2642 return -EPERM; 2643 } 2644 2645 if (sc->num_io_throttle_group != sc->facts.max_io_throttle_group) { 2646 mpi3mr_dprint(sc, MPI3MR_ERROR, 2647 "max io throttle group doesn't match old(%d), new(%d)\n", 2648 sc->num_io_throttle_group, 2649 sc->facts.max_io_throttle_group); 2650 return -EPERM; 2651 } 2652 2653 if (sc->facts.max_op_reply_q < sc->num_queues) { 2654 mpi3mr_dprint(sc, MPI3MR_ERROR, 2655 "Cannot reduce number of operational reply queues from %d to %d\n", 2656 sc->num_queues, 2657 sc->facts.max_op_reply_q); 2658 return -EPERM; 2659 } 2660 2661 if (sc->facts.max_op_req_q < sc->num_queues) { 2662 mpi3mr_dprint(sc, MPI3MR_ERROR, 2663 "Cannot reduce number of operational request queues from %d to %d\n", 2664 sc->num_queues, sc->facts.max_op_req_q); 2665 return -EPERM; 2666 } 2667 2668 dev_handle_bitmap_sz = MPI3MR_DIV_ROUND_UP(sc->facts.max_devhandle, 8); 2669 2670 if (dev_handle_bitmap_sz > sc->dev_handle_bitmap_sz) { 2671 removepend_bitmap = realloc(sc->removepend_bitmap, 2672 dev_handle_bitmap_sz, M_MPI3MR, M_NOWAIT); 2673 2674 if (!removepend_bitmap) { 2675 mpi3mr_dprint(sc, MPI3MR_ERROR, 2676 "failed to increase removepend_bitmap sz from: %d to %d\n", 2677 sc->dev_handle_bitmap_sz, dev_handle_bitmap_sz); 2678 return -ENOMEM; 2679 } 2680 2681 memset(removepend_bitmap + sc->dev_handle_bitmap_sz, 0, 2682 dev_handle_bitmap_sz - sc->dev_handle_bitmap_sz); 2683 sc->removepend_bitmap = removepend_bitmap; 2684 mpi3mr_dprint(sc, MPI3MR_INFO, 2685 "increased dev_handle_bitmap_sz from %d to %d\n", 2686 sc->dev_handle_bitmap_sz, dev_handle_bitmap_sz); 2687 sc->dev_handle_bitmap_sz = dev_handle_bitmap_sz; 2688 } 2689 2690 return 0; 2691 } 2692 2693 /* 2694 * mpi3mr_initialize_ioc - Controller initialization 2695 * @dev: pointer to device struct 2696 * 2697 * This function allocates the controller wide resources and brings 2698 * the controller to operational state 2699 * 2700 * Return: 0 on success and proper error codes on failure 2701 */ 2702 int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) 2703 { 2704 int retval = 0; 2705 enum mpi3mr_iocstate ioc_state; 2706 U64 ioc_info; 2707 U32 ioc_status, ioc_control, i, timeout; 2708 Mpi3IOCFactsData_t facts_data; 2709 char str[32]; 2710 U32 size; 2711 2712 sc->cpu_count = mp_ncpus; 2713 2714 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 2715 ioc_control = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 2716 ioc_info = mpi3mr_regread64(sc, MPI3_SYSIF_IOC_INFO_LOW_OFFSET); 2717 2718 mpi3mr_dprint(sc, MPI3MR_INFO, "SOD ioc_status: 0x%x ioc_control: 0x%x " 2719 "ioc_info: 0x%lx\n", ioc_status, ioc_control, ioc_info); 2720 2721 /*The timeout value is in 2sec unit, changing it to seconds*/ 2722 sc->ready_timeout = 2723 ((ioc_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 2724 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 2725 2726 ioc_state = mpi3mr_get_iocstate(sc); 2727 2728 mpi3mr_dprint(sc, MPI3MR_INFO, "IOC state: %s IOC ready timeout: %d\n", 2729 mpi3mr_iocstate_name(ioc_state), sc->ready_timeout); 2730 2731 if (ioc_state == MRIOC_STATE_BECOMING_READY || 2732 ioc_state == MRIOC_STATE_RESET_REQUESTED) { 2733 timeout = sc->ready_timeout * 10; 2734 do { 2735 DELAY(1000 * 100); 2736 } while (--timeout); 2737 2738 ioc_state = mpi3mr_get_iocstate(sc); 2739 mpi3mr_dprint(sc, MPI3MR_INFO, 2740 "IOC in %s state after waiting for reset time\n", 2741 mpi3mr_iocstate_name(ioc_state)); 2742 } 2743 2744 if (ioc_state == MRIOC_STATE_READY) { 2745 retval = mpi3mr_mur_ioc(sc, MPI3MR_RESET_FROM_BRINGUP); 2746 if (retval) { 2747 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to MU reset IOC, error 0x%x\n", 2748 retval); 2749 } 2750 ioc_state = mpi3mr_get_iocstate(sc); 2751 } 2752 2753 if (ioc_state != MRIOC_STATE_RESET) { 2754 mpi3mr_print_fault_info(sc); 2755 mpi3mr_dprint(sc, MPI3MR_ERROR, "issuing soft reset to bring to reset state\n"); 2756 retval = mpi3mr_issue_reset(sc, 2757 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 2758 MPI3MR_RESET_FROM_BRINGUP); 2759 if (retval) { 2760 mpi3mr_dprint(sc, MPI3MR_ERROR, 2761 "%s :Failed to soft reset IOC, error 0x%d\n", 2762 __func__, retval); 2763 goto out_failed; 2764 } 2765 } 2766 2767 ioc_state = mpi3mr_get_iocstate(sc); 2768 2769 if (ioc_state != MRIOC_STATE_RESET) { 2770 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot bring IOC to reset state\n"); 2771 goto out_failed; 2772 } 2773 2774 retval = mpi3mr_setup_admin_qpair(sc); 2775 if (retval) { 2776 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to setup Admin queues, error 0x%x\n", 2777 retval); 2778 goto out_failed; 2779 } 2780 2781 retval = mpi3mr_bring_ioc_ready(sc); 2782 if (retval) { 2783 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to bring IOC ready, error 0x%x\n", 2784 retval); 2785 goto out_failed; 2786 } 2787 2788 if (init_type == MPI3MR_INIT_TYPE_INIT) { 2789 retval = mpi3mr_alloc_interrupts(sc, 1); 2790 if (retval) { 2791 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate interrupts, error 0x%x\n", 2792 retval); 2793 goto out_failed; 2794 } 2795 2796 retval = mpi3mr_setup_irqs(sc); 2797 if (retval) { 2798 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to setup ISR, error 0x%x\n", 2799 retval); 2800 goto out_failed; 2801 } 2802 } 2803 2804 mpi3mr_enable_interrupts(sc); 2805 2806 if (init_type == MPI3MR_INIT_TYPE_INIT) { 2807 mtx_init(&sc->mpi3mr_mtx, "SIM lock", NULL, MTX_DEF); 2808 mtx_init(&sc->io_lock, "IO lock", NULL, MTX_DEF); 2809 mtx_init(&sc->admin_req_lock, "Admin Request Queue lock", NULL, MTX_SPIN); 2810 mtx_init(&sc->reply_free_q_lock, "Reply free Queue lock", NULL, MTX_SPIN); 2811 mtx_init(&sc->sense_buf_q_lock, "Sense buffer Queue lock", NULL, MTX_SPIN); 2812 mtx_init(&sc->chain_buf_lock, "Chain buffer lock", NULL, MTX_SPIN); 2813 mtx_init(&sc->cmd_pool_lock, "Command pool lock", NULL, MTX_DEF); 2814 mtx_init(&sc->fwevt_lock, "Firmware Event lock", NULL, MTX_DEF); 2815 mtx_init(&sc->target_lock, "Target lock", NULL, MTX_SPIN); 2816 mtx_init(&sc->reset_mutex, "Reset lock", NULL, MTX_DEF); 2817 2818 mtx_init(&sc->init_cmds.completion.lock, "Init commands lock", NULL, MTX_DEF); 2819 sc->init_cmds.reply = NULL; 2820 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2821 sc->init_cmds.dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2822 sc->init_cmds.host_tag = MPI3MR_HOSTTAG_INITCMDS; 2823 2824 mtx_init(&sc->ioctl_cmds.completion.lock, "IOCTL commands lock", NULL, MTX_DEF); 2825 sc->ioctl_cmds.reply = NULL; 2826 sc->ioctl_cmds.state = MPI3MR_CMD_NOTUSED; 2827 sc->ioctl_cmds.dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2828 sc->ioctl_cmds.host_tag = MPI3MR_HOSTTAG_IOCTLCMDS; 2829 2830 mtx_init(&sc->pel_abort_cmd.completion.lock, "PEL Abort command lock", NULL, MTX_DEF); 2831 sc->pel_abort_cmd.reply = NULL; 2832 sc->pel_abort_cmd.state = MPI3MR_CMD_NOTUSED; 2833 sc->pel_abort_cmd.dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2834 sc->pel_abort_cmd.host_tag = MPI3MR_HOSTTAG_PELABORT; 2835 2836 mtx_init(&sc->host_tm_cmds.completion.lock, "TM commands lock", NULL, MTX_DEF); 2837 sc->host_tm_cmds.reply = NULL; 2838 sc->host_tm_cmds.state = MPI3MR_CMD_NOTUSED; 2839 sc->host_tm_cmds.dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2840 sc->host_tm_cmds.host_tag = MPI3MR_HOSTTAG_TMS; 2841 2842 TAILQ_INIT(&sc->cmd_list_head); 2843 TAILQ_INIT(&sc->event_list); 2844 TAILQ_INIT(&sc->delayed_rmhs_list); 2845 TAILQ_INIT(&sc->delayed_evtack_cmds_list); 2846 2847 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 2848 snprintf(str, 32, "Dev REMHS commands lock[%d]", i); 2849 mtx_init(&sc->dev_rmhs_cmds[i].completion.lock, str, NULL, MTX_DEF); 2850 sc->dev_rmhs_cmds[i].reply = NULL; 2851 sc->dev_rmhs_cmds[i].state = MPI3MR_CMD_NOTUSED; 2852 sc->dev_rmhs_cmds[i].dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2853 sc->dev_rmhs_cmds[i].host_tag = MPI3MR_HOSTTAG_DEVRMCMD_MIN 2854 + i; 2855 } 2856 } 2857 2858 retval = mpi3mr_issue_iocfacts(sc, &facts_data); 2859 if (retval) { 2860 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to Issue IOC Facts, retval: 0x%x\n", 2861 retval); 2862 goto out_failed; 2863 } 2864 2865 retval = mpi3mr_process_factsdata(sc, &facts_data); 2866 if (retval) { 2867 mpi3mr_dprint(sc, MPI3MR_ERROR, "IOC Facts data processing failedi, retval: 0x%x\n", 2868 retval); 2869 goto out_failed; 2870 } 2871 2872 sc->num_io_throttle_group = sc->facts.max_io_throttle_group; 2873 mpi3mr_atomic_set(&sc->pend_large_data_sz, 0); 2874 2875 if (init_type == MPI3MR_INIT_TYPE_RESET) { 2876 retval = mpi3mr_validate_fw_update(sc); 2877 if (retval) 2878 goto out_failed; 2879 } else { 2880 sc->reply_sz = sc->facts.reply_sz; 2881 } 2882 2883 2884 mpi3mr_display_ioc_info(sc); 2885 2886 retval = mpi3mr_reply_alloc(sc); 2887 if (retval) { 2888 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocated reply and sense buffers, retval: 0x%x\n", 2889 retval); 2890 goto out_failed; 2891 } 2892 2893 if (init_type == MPI3MR_INIT_TYPE_INIT) { 2894 retval = mpi3mr_alloc_chain_bufs(sc); 2895 if (retval) { 2896 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocated chain buffers, retval: 0x%x\n", 2897 retval); 2898 goto out_failed; 2899 } 2900 } 2901 2902 retval = mpi3mr_issue_iocinit(sc); 2903 if (retval) { 2904 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to Issue IOC Init, retval: 0x%x\n", 2905 retval); 2906 goto out_failed; 2907 } 2908 2909 mpi3mr_print_fw_pkg_ver(sc); 2910 2911 sc->reply_free_q_host_index = sc->num_reply_bufs; 2912 mpi3mr_regwrite(sc, MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET, 2913 sc->reply_free_q_host_index); 2914 2915 sc->sense_buf_q_host_index = sc->num_sense_bufs; 2916 2917 mpi3mr_regwrite(sc, MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET, 2918 sc->sense_buf_q_host_index); 2919 2920 if (init_type == MPI3MR_INIT_TYPE_INIT) { 2921 retval = mpi3mr_alloc_interrupts(sc, 0); 2922 if (retval) { 2923 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate interrupts, retval: 0x%x\n", 2924 retval); 2925 goto out_failed; 2926 } 2927 2928 retval = mpi3mr_setup_irqs(sc); 2929 if (retval) { 2930 printf(IOCNAME "Failed to setup ISR, error: 0x%x\n", 2931 sc->name, retval); 2932 goto out_failed; 2933 } 2934 2935 mpi3mr_enable_interrupts(sc); 2936 2937 } else 2938 mpi3mr_enable_interrupts(sc); 2939 2940 retval = mpi3mr_create_op_queues(sc); 2941 2942 if (retval) { 2943 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to create operational queues, error: %d\n", 2944 retval); 2945 goto out_failed; 2946 } 2947 2948 if (!sc->throttle_groups && sc->num_io_throttle_group) { 2949 mpi3mr_dprint(sc, MPI3MR_ERROR, "allocating memory for throttle groups\n"); 2950 size = sizeof(struct mpi3mr_throttle_group_info); 2951 sc->throttle_groups = (struct mpi3mr_throttle_group_info *) 2952 malloc(sc->num_io_throttle_group * 2953 size, M_MPI3MR, M_NOWAIT | M_ZERO); 2954 if (!sc->throttle_groups) 2955 goto out_failed; 2956 } 2957 2958 if (init_type == MPI3MR_INIT_TYPE_RESET) { 2959 mpi3mr_dprint(sc, MPI3MR_INFO, "Re-register events\n"); 2960 retval = mpi3mr_register_events(sc); 2961 if (retval) { 2962 mpi3mr_dprint(sc, MPI3MR_INFO, "Failed to re-register events, retval: 0x%x\n", 2963 retval); 2964 goto out_failed; 2965 } 2966 2967 mpi3mr_dprint(sc, MPI3MR_INFO, "Issuing Port Enable\n"); 2968 retval = mpi3mr_issue_port_enable(sc, 0); 2969 if (retval) { 2970 mpi3mr_dprint(sc, MPI3MR_INFO, "Failed to issue port enable, retval: 0x%x\n", 2971 retval); 2972 goto out_failed; 2973 } 2974 } 2975 retval = mpi3mr_pel_alloc(sc); 2976 if (retval) { 2977 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate memory for PEL, retval: 0x%x\n", 2978 retval); 2979 goto out_failed; 2980 } 2981 2982 return retval; 2983 2984 out_failed: 2985 retval = -1; 2986 return retval; 2987 } 2988 2989 static void mpi3mr_port_enable_complete(struct mpi3mr_softc *sc, 2990 struct mpi3mr_drvr_cmd *drvrcmd) 2991 { 2992 drvrcmd->state = MPI3MR_CMD_NOTUSED; 2993 drvrcmd->callback = NULL; 2994 printf(IOCNAME "Completing Port Enable Request\n", sc->name); 2995 sc->mpi3mr_flags |= MPI3MR_FLAGS_PORT_ENABLE_DONE; 2996 mpi3mr_startup_decrement(sc->cam_sc); 2997 } 2998 2999 int mpi3mr_issue_port_enable(struct mpi3mr_softc *sc, U8 async) 3000 { 3001 Mpi3PortEnableRequest_t pe_req; 3002 int retval = 0; 3003 3004 memset(&pe_req, 0, sizeof(pe_req)); 3005 mtx_lock(&sc->init_cmds.completion.lock); 3006 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 3007 retval = -1; 3008 printf(IOCNAME "Issue PortEnable: Init command is in use\n", sc->name); 3009 mtx_unlock(&sc->init_cmds.completion.lock); 3010 goto out; 3011 } 3012 3013 sc->init_cmds.state = MPI3MR_CMD_PENDING; 3014 3015 if (async) { 3016 sc->init_cmds.is_waiting = 0; 3017 sc->init_cmds.callback = mpi3mr_port_enable_complete; 3018 } else { 3019 sc->init_cmds.is_waiting = 1; 3020 sc->init_cmds.callback = NULL; 3021 init_completion(&sc->init_cmds.completion); 3022 } 3023 pe_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 3024 pe_req.Function = MPI3_FUNCTION_PORT_ENABLE; 3025 3026 printf(IOCNAME "Sending Port Enable Request\n", sc->name); 3027 retval = mpi3mr_submit_admin_cmd(sc, &pe_req, sizeof(pe_req)); 3028 if (retval) { 3029 printf(IOCNAME "Issue PortEnable: Admin Post failed\n", 3030 sc->name); 3031 goto out_unlock; 3032 } 3033 3034 if (!async) { 3035 wait_for_completion_timeout(&sc->init_cmds.completion, 3036 MPI3MR_PORTENABLE_TIMEOUT); 3037 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3038 printf(IOCNAME "Issue PortEnable: command timed out\n", 3039 sc->name); 3040 retval = -1; 3041 mpi3mr_check_rh_fault_ioc(sc, MPI3MR_RESET_FROM_PE_TIMEOUT); 3042 goto out_unlock; 3043 } 3044 mpi3mr_port_enable_complete(sc, &sc->init_cmds); 3045 } 3046 out_unlock: 3047 mtx_unlock(&sc->init_cmds.completion.lock); 3048 3049 out: 3050 return retval; 3051 } 3052 3053 void 3054 mpi3mr_watchdog_thread(void *arg) 3055 { 3056 struct mpi3mr_softc *sc; 3057 enum mpi3mr_iocstate ioc_state; 3058 U32 fault, host_diagnostic, ioc_status; 3059 3060 sc = (struct mpi3mr_softc *)arg; 3061 3062 mpi3mr_dprint(sc, MPI3MR_XINFO, "%s\n", __func__); 3063 3064 sc->watchdog_thread_active = 1; 3065 mtx_lock(&sc->reset_mutex); 3066 for (;;) { 3067 if (sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN || 3068 (sc->unrecoverable == 1)) { 3069 mpi3mr_dprint(sc, MPI3MR_INFO, 3070 "Exit due to %s from %s\n", 3071 sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN ? "Shutdown" : 3072 "Hardware critical error", __func__); 3073 break; 3074 } 3075 mtx_unlock(&sc->reset_mutex); 3076 3077 if ((sc->prepare_for_reset) && 3078 ((sc->prepare_for_reset_timeout_counter++) >= 3079 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) { 3080 mpi3mr_soft_reset_handler(sc, 3081 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1); 3082 goto sleep; 3083 } 3084 3085 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 3086 3087 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 3088 mpi3mr_soft_reset_handler(sc, MPI3MR_RESET_FROM_FIRMWARE, 0); 3089 goto sleep; 3090 } 3091 3092 ioc_state = mpi3mr_get_iocstate(sc); 3093 if (ioc_state == MRIOC_STATE_FAULT) { 3094 fault = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_OFFSET) & 3095 MPI3_SYSIF_FAULT_CODE_MASK; 3096 3097 host_diagnostic = mpi3mr_regread(sc, MPI3_SYSIF_HOST_DIAG_OFFSET); 3098 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 3099 if (!sc->diagsave_timeout) { 3100 mpi3mr_print_fault_info(sc); 3101 mpi3mr_dprint(sc, MPI3MR_INFO, 3102 "diag save in progress\n"); 3103 } 3104 if ((sc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 3105 goto sleep; 3106 } 3107 mpi3mr_print_fault_info(sc); 3108 sc->diagsave_timeout = 0; 3109 3110 if ((fault == MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED) || 3111 (fault == MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED)) { 3112 mpi3mr_dprint(sc, MPI3MR_INFO, 3113 "Controller requires system power cycle or complete reset is needed," 3114 "fault code: 0x%x. marking controller as unrecoverable\n", fault); 3115 sc->unrecoverable = 1; 3116 break; 3117 } 3118 if ((fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) 3119 || (fault == MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS) 3120 || (sc->reset_in_progress)) 3121 break; 3122 if (fault == MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET) 3123 mpi3mr_soft_reset_handler(sc, 3124 MPI3MR_RESET_FROM_CIACTIV_FAULT, 0); 3125 else 3126 mpi3mr_soft_reset_handler(sc, 3127 MPI3MR_RESET_FROM_FAULT_WATCH, 0); 3128 3129 } 3130 3131 if (sc->reset.type == MPI3MR_TRIGGER_SOFT_RESET) { 3132 mpi3mr_print_fault_info(sc); 3133 mpi3mr_soft_reset_handler(sc, sc->reset.reason, 1); 3134 } 3135 sleep: 3136 mtx_lock(&sc->reset_mutex); 3137 /* 3138 * Sleep for 1 second if we're not exiting, then loop to top 3139 * to poll exit status and hardware health. 3140 */ 3141 if ((sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN) == 0 && 3142 !sc->unrecoverable) { 3143 msleep(&sc->watchdog_chan, &sc->reset_mutex, PRIBIO, 3144 "mpi3mr_watchdog", 1 * hz); 3145 } 3146 } 3147 mtx_unlock(&sc->reset_mutex); 3148 sc->watchdog_thread_active = 0; 3149 mpi3mr_kproc_exit(0); 3150 } 3151 3152 static void mpi3mr_display_event_data(struct mpi3mr_softc *sc, 3153 Mpi3EventNotificationReply_t *event_rep) 3154 { 3155 char *desc = NULL; 3156 U16 event; 3157 3158 event = event_rep->Event; 3159 3160 switch (event) { 3161 case MPI3_EVENT_LOG_DATA: 3162 desc = "Log Data"; 3163 break; 3164 case MPI3_EVENT_CHANGE: 3165 desc = "Event Change"; 3166 break; 3167 case MPI3_EVENT_GPIO_INTERRUPT: 3168 desc = "GPIO Interrupt"; 3169 break; 3170 case MPI3_EVENT_CABLE_MGMT: 3171 desc = "Cable Management"; 3172 break; 3173 case MPI3_EVENT_ENERGY_PACK_CHANGE: 3174 desc = "Energy Pack Change"; 3175 break; 3176 case MPI3_EVENT_DEVICE_ADDED: 3177 { 3178 Mpi3DevicePage0_t *event_data = 3179 (Mpi3DevicePage0_t *)event_rep->EventData; 3180 mpi3mr_dprint(sc, MPI3MR_EVENT, "Device Added: Dev=0x%04x Form=0x%x Perst id: 0x%x\n", 3181 event_data->DevHandle, event_data->DeviceForm, event_data->PersistentID); 3182 return; 3183 } 3184 case MPI3_EVENT_DEVICE_INFO_CHANGED: 3185 { 3186 Mpi3DevicePage0_t *event_data = 3187 (Mpi3DevicePage0_t *)event_rep->EventData; 3188 mpi3mr_dprint(sc, MPI3MR_EVENT, "Device Info Changed: Dev=0x%04x Form=0x%x\n", 3189 event_data->DevHandle, event_data->DeviceForm); 3190 return; 3191 } 3192 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 3193 { 3194 Mpi3EventDataDeviceStatusChange_t *event_data = 3195 (Mpi3EventDataDeviceStatusChange_t *)event_rep->EventData; 3196 mpi3mr_dprint(sc, MPI3MR_EVENT, "Device Status Change: Dev=0x%04x RC=0x%x\n", 3197 event_data->DevHandle, event_data->ReasonCode); 3198 return; 3199 } 3200 case MPI3_EVENT_SAS_DISCOVERY: 3201 { 3202 Mpi3EventDataSasDiscovery_t *event_data = 3203 (Mpi3EventDataSasDiscovery_t *)event_rep->EventData; 3204 mpi3mr_dprint(sc, MPI3MR_EVENT, "SAS Discovery: (%s)", 3205 (event_data->ReasonCode == MPI3_EVENT_SAS_DISC_RC_STARTED) ? 3206 "start" : "stop"); 3207 if (event_data->DiscoveryStatus && 3208 (sc->mpi3mr_debug & MPI3MR_EVENT)) { 3209 printf("discovery_status(0x%08x)", 3210 event_data->DiscoveryStatus); 3211 3212 } 3213 3214 if (sc->mpi3mr_debug & MPI3MR_EVENT) 3215 printf("\n"); 3216 return; 3217 } 3218 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 3219 desc = "SAS Broadcast Primitive"; 3220 break; 3221 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE: 3222 desc = "SAS Notify Primitive"; 3223 break; 3224 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 3225 desc = "SAS Init Device Status Change"; 3226 break; 3227 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW: 3228 desc = "SAS Init Table Overflow"; 3229 break; 3230 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 3231 desc = "SAS Topology Change List"; 3232 break; 3233 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 3234 desc = "Enclosure Device Status Change"; 3235 break; 3236 case MPI3_EVENT_HARD_RESET_RECEIVED: 3237 desc = "Hard Reset Received"; 3238 break; 3239 case MPI3_EVENT_SAS_PHY_COUNTER: 3240 desc = "SAS PHY Counter"; 3241 break; 3242 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 3243 desc = "SAS Device Discovery Error"; 3244 break; 3245 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 3246 desc = "PCIE Topology Change List"; 3247 break; 3248 case MPI3_EVENT_PCIE_ENUMERATION: 3249 { 3250 Mpi3EventDataPcieEnumeration_t *event_data = 3251 (Mpi3EventDataPcieEnumeration_t *)event_rep->EventData; 3252 mpi3mr_dprint(sc, MPI3MR_EVENT, "PCIE Enumeration: (%s)", 3253 (event_data->ReasonCode == 3254 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : 3255 "stop"); 3256 if (event_data->EnumerationStatus) 3257 mpi3mr_dprint(sc, MPI3MR_EVENT, "enumeration_status(0x%08x)", 3258 event_data->EnumerationStatus); 3259 if (sc->mpi3mr_debug & MPI3MR_EVENT) 3260 printf("\n"); 3261 return; 3262 } 3263 case MPI3_EVENT_PREPARE_FOR_RESET: 3264 desc = "Prepare For Reset"; 3265 break; 3266 } 3267 3268 if (!desc) 3269 return; 3270 3271 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s\n", desc); 3272 } 3273 3274 struct mpi3mr_target * 3275 mpi3mr_find_target_by_per_id(struct mpi3mr_cam_softc *cam_sc, 3276 uint16_t per_id) 3277 { 3278 struct mpi3mr_target *target = NULL; 3279 3280 mtx_lock_spin(&cam_sc->sc->target_lock); 3281 TAILQ_FOREACH(target, &cam_sc->tgt_list, tgt_next) { 3282 if (target->per_id == per_id) 3283 break; 3284 } 3285 3286 mtx_unlock_spin(&cam_sc->sc->target_lock); 3287 return target; 3288 } 3289 3290 struct mpi3mr_target * 3291 mpi3mr_find_target_by_dev_handle(struct mpi3mr_cam_softc *cam_sc, 3292 uint16_t handle) 3293 { 3294 struct mpi3mr_target *target = NULL; 3295 3296 mtx_lock_spin(&cam_sc->sc->target_lock); 3297 TAILQ_FOREACH(target, &cam_sc->tgt_list, tgt_next) { 3298 if (target->dev_handle == handle) 3299 break; 3300 3301 } 3302 mtx_unlock_spin(&cam_sc->sc->target_lock); 3303 return target; 3304 } 3305 3306 void mpi3mr_update_device(struct mpi3mr_softc *sc, 3307 struct mpi3mr_target *tgtdev, Mpi3DevicePage0_t *dev_pg0, 3308 bool is_added) 3309 { 3310 U16 flags = 0; 3311 3312 tgtdev->per_id = (dev_pg0->PersistentID); 3313 tgtdev->dev_handle = (dev_pg0->DevHandle); 3314 tgtdev->dev_type = dev_pg0->DeviceForm; 3315 tgtdev->encl_handle = (dev_pg0->EnclosureHandle); 3316 tgtdev->parent_handle = (dev_pg0->ParentDevHandle); 3317 tgtdev->slot = (dev_pg0->Slot); 3318 tgtdev->qdepth = (dev_pg0->QueueDepth); 3319 tgtdev->wwid = (dev_pg0->WWID); 3320 3321 flags = (dev_pg0->Flags); 3322 tgtdev->is_hidden = (flags & MPI3_DEVICE0_FLAGS_HIDDEN); 3323 if (is_added == true) 3324 tgtdev->io_throttle_enabled = 3325 (flags & MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED) ? 1 : 0; 3326 3327 switch (dev_pg0->AccessStatus) { 3328 case MPI3_DEVICE0_ASTATUS_NO_ERRORS: 3329 case MPI3_DEVICE0_ASTATUS_PREPARE: 3330 case MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION: 3331 case MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY: 3332 break; 3333 default: 3334 tgtdev->is_hidden = 1; 3335 break; 3336 } 3337 3338 switch (tgtdev->dev_type) { 3339 case MPI3_DEVICE_DEVFORM_SAS_SATA: 3340 { 3341 Mpi3Device0SasSataFormat_t *sasinf = 3342 &dev_pg0->DeviceSpecific.SasSataFormat; 3343 U16 dev_info = (sasinf->DeviceInfo); 3344 tgtdev->dev_spec.sassata_inf.dev_info = dev_info; 3345 tgtdev->dev_spec.sassata_inf.sas_address = 3346 (sasinf->SASAddress); 3347 if ((dev_info & MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK) != 3348 MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE) 3349 tgtdev->is_hidden = 1; 3350 else if (!(dev_info & (MPI3_SAS_DEVICE_INFO_STP_SATA_TARGET | 3351 MPI3_SAS_DEVICE_INFO_SSP_TARGET))) 3352 tgtdev->is_hidden = 1; 3353 break; 3354 } 3355 case MPI3_DEVICE_DEVFORM_PCIE: 3356 { 3357 Mpi3Device0PcieFormat_t *pcieinf = 3358 &dev_pg0->DeviceSpecific.PcieFormat; 3359 U16 dev_info = (pcieinf->DeviceInfo); 3360 3361 tgtdev->q_depth = dev_pg0->QueueDepth; 3362 tgtdev->dev_spec.pcie_inf.dev_info = dev_info; 3363 tgtdev->dev_spec.pcie_inf.capb = 3364 (pcieinf->Capabilities); 3365 tgtdev->dev_spec.pcie_inf.mdts = MPI3MR_DEFAULT_MDTS; 3366 if (dev_pg0->AccessStatus == MPI3_DEVICE0_ASTATUS_NO_ERRORS) { 3367 tgtdev->dev_spec.pcie_inf.mdts = 3368 (pcieinf->MaximumDataTransferSize); 3369 tgtdev->dev_spec.pcie_inf.pgsz = pcieinf->PageSize; 3370 tgtdev->dev_spec.pcie_inf.reset_to = 3371 pcieinf->ControllerResetTO; 3372 tgtdev->dev_spec.pcie_inf.abort_to = 3373 pcieinf->NVMeAbortTO; 3374 } 3375 if (tgtdev->dev_spec.pcie_inf.mdts > (1024 * 1024)) 3376 tgtdev->dev_spec.pcie_inf.mdts = (1024 * 1024); 3377 3378 if (((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) != 3379 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE) && 3380 ((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) != 3381 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE)) 3382 tgtdev->is_hidden = 1; 3383 3384 break; 3385 } 3386 case MPI3_DEVICE_DEVFORM_VD: 3387 { 3388 Mpi3Device0VdFormat_t *vdinf = 3389 &dev_pg0->DeviceSpecific.VdFormat; 3390 struct mpi3mr_throttle_group_info *tg = NULL; 3391 3392 tgtdev->dev_spec.vol_inf.state = vdinf->VdState; 3393 if (vdinf->VdState == MPI3_DEVICE0_VD_STATE_OFFLINE) 3394 tgtdev->is_hidden = 1; 3395 tgtdev->dev_spec.vol_inf.tg_id = vdinf->IOThrottleGroup; 3396 tgtdev->dev_spec.vol_inf.tg_high = 3397 vdinf->IOThrottleGroupHigh * 2048; 3398 tgtdev->dev_spec.vol_inf.tg_low = 3399 vdinf->IOThrottleGroupLow * 2048; 3400 if (vdinf->IOThrottleGroup < sc->num_io_throttle_group) { 3401 tg = sc->throttle_groups + vdinf->IOThrottleGroup; 3402 tg->id = vdinf->IOThrottleGroup; 3403 tg->high = tgtdev->dev_spec.vol_inf.tg_high; 3404 tg->low = tgtdev->dev_spec.vol_inf.tg_low; 3405 if (is_added == true) 3406 tg->fw_qd = tgtdev->q_depth; 3407 tg->modified_qd = tgtdev->q_depth; 3408 } 3409 tgtdev->dev_spec.vol_inf.tg = tg; 3410 tgtdev->throttle_group = tg; 3411 break; 3412 } 3413 default: 3414 goto out; 3415 } 3416 3417 out: 3418 return; 3419 } 3420 3421 int mpi3mr_create_device(struct mpi3mr_softc *sc, 3422 Mpi3DevicePage0_t *dev_pg0) 3423 { 3424 int retval = 0; 3425 struct mpi3mr_target *target = NULL; 3426 U16 per_id = 0; 3427 3428 per_id = dev_pg0->PersistentID; 3429 3430 mtx_lock_spin(&sc->target_lock); 3431 TAILQ_FOREACH(target, &sc->cam_sc->tgt_list, tgt_next) { 3432 if (target->per_id == per_id) { 3433 target->state = MPI3MR_DEV_CREATED; 3434 break; 3435 } 3436 } 3437 mtx_unlock_spin(&sc->target_lock); 3438 3439 if (target) { 3440 mpi3mr_update_device(sc, target, dev_pg0, true); 3441 } else { 3442 target = malloc(sizeof(*target), M_MPI3MR, 3443 M_NOWAIT | M_ZERO); 3444 3445 if (target == NULL) { 3446 retval = -1; 3447 goto out; 3448 } 3449 3450 target->exposed_to_os = 0; 3451 mpi3mr_update_device(sc, target, dev_pg0, true); 3452 mtx_lock_spin(&sc->target_lock); 3453 TAILQ_INSERT_TAIL(&sc->cam_sc->tgt_list, target, tgt_next); 3454 target->state = MPI3MR_DEV_CREATED; 3455 mtx_unlock_spin(&sc->target_lock); 3456 } 3457 out: 3458 return retval; 3459 } 3460 3461 /** 3462 * mpi3mr_dev_rmhs_complete_iou - Device removal IOUC completion 3463 * @sc: Adapter instance reference 3464 * @drv_cmd: Internal command tracker 3465 * 3466 * Issues a target reset TM to the firmware from the device 3467 * removal TM pend list or retry the removal handshake sequence 3468 * based on the IOU control request IOC status. 3469 * 3470 * Return: Nothing 3471 */ 3472 static void mpi3mr_dev_rmhs_complete_iou(struct mpi3mr_softc *sc, 3473 struct mpi3mr_drvr_cmd *drv_cmd) 3474 { 3475 U16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 3476 struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL; 3477 3478 mpi3mr_dprint(sc, MPI3MR_EVENT, 3479 "%s :dev_rmhs_iouctrl_complete:handle(0x%04x), ioc_status(0x%04x), loginfo(0x%08x)\n", 3480 __func__, drv_cmd->dev_handle, drv_cmd->ioc_status, 3481 drv_cmd->ioc_loginfo); 3482 if (drv_cmd->ioc_status != MPI3_IOCSTATUS_SUCCESS) { 3483 if (drv_cmd->retry_count < MPI3MR_DEVRMHS_RETRYCOUNT) { 3484 drv_cmd->retry_count++; 3485 mpi3mr_dprint(sc, MPI3MR_EVENT, 3486 "%s :dev_rmhs_iouctrl_complete: handle(0x%04x)retrying handshake retry=%d\n", 3487 __func__, drv_cmd->dev_handle, 3488 drv_cmd->retry_count); 3489 mpi3mr_dev_rmhs_send_tm(sc, drv_cmd->dev_handle, 3490 drv_cmd, drv_cmd->iou_rc); 3491 return; 3492 } 3493 mpi3mr_dprint(sc, MPI3MR_ERROR, 3494 "%s :dev removal handshake failed after all retries: handle(0x%04x)\n", 3495 __func__, drv_cmd->dev_handle); 3496 } else { 3497 mpi3mr_dprint(sc, MPI3MR_INFO, 3498 "%s :dev removal handshake completed successfully: handle(0x%04x)\n", 3499 __func__, drv_cmd->dev_handle); 3500 mpi3mr_clear_bit(drv_cmd->dev_handle, sc->removepend_bitmap); 3501 } 3502 3503 if (!TAILQ_EMPTY(&sc->delayed_rmhs_list)) { 3504 delayed_dev_rmhs = TAILQ_FIRST(&sc->delayed_rmhs_list); 3505 drv_cmd->dev_handle = delayed_dev_rmhs->handle; 3506 drv_cmd->retry_count = 0; 3507 drv_cmd->iou_rc = delayed_dev_rmhs->iou_rc; 3508 mpi3mr_dprint(sc, MPI3MR_EVENT, 3509 "%s :dev_rmhs_iouctrl_complete: processing delayed TM: handle(0x%04x)\n", 3510 __func__, drv_cmd->dev_handle); 3511 mpi3mr_dev_rmhs_send_tm(sc, drv_cmd->dev_handle, drv_cmd, 3512 drv_cmd->iou_rc); 3513 TAILQ_REMOVE(&sc->delayed_rmhs_list, delayed_dev_rmhs, list); 3514 free(delayed_dev_rmhs, M_MPI3MR); 3515 return; 3516 } 3517 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3518 drv_cmd->callback = NULL; 3519 drv_cmd->retry_count = 0; 3520 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE; 3521 mpi3mr_clear_bit(cmd_idx, sc->devrem_bitmap); 3522 } 3523 3524 /** 3525 * mpi3mr_dev_rmhs_complete_tm - Device removal TM completion 3526 * @sc: Adapter instance reference 3527 * @drv_cmd: Internal command tracker 3528 * 3529 * Issues a target reset TM to the firmware from the device 3530 * removal TM pend list or issue IO Unit control request as 3531 * part of device removal or hidden acknowledgment handshake. 3532 * 3533 * Return: Nothing 3534 */ 3535 static void mpi3mr_dev_rmhs_complete_tm(struct mpi3mr_softc *sc, 3536 struct mpi3mr_drvr_cmd *drv_cmd) 3537 { 3538 Mpi3IoUnitControlRequest_t iou_ctrl; 3539 U16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 3540 Mpi3SCSITaskMgmtReply_t *tm_reply = NULL; 3541 int retval; 3542 3543 if (drv_cmd->state & MPI3MR_CMD_REPLYVALID) 3544 tm_reply = (Mpi3SCSITaskMgmtReply_t *)drv_cmd->reply; 3545 3546 if (tm_reply) 3547 printf(IOCNAME 3548 "dev_rmhs_tr_complete:handle(0x%04x), ioc_status(0x%04x), loginfo(0x%08x), term_count(%d)\n", 3549 sc->name, drv_cmd->dev_handle, drv_cmd->ioc_status, 3550 drv_cmd->ioc_loginfo, 3551 le32toh(tm_reply->TerminationCount)); 3552 3553 printf(IOCNAME "Issuing IOU CTL: handle(0x%04x) dev_rmhs idx(%d)\n", 3554 sc->name, drv_cmd->dev_handle, cmd_idx); 3555 3556 memset(&iou_ctrl, 0, sizeof(iou_ctrl)); 3557 3558 drv_cmd->state = MPI3MR_CMD_PENDING; 3559 drv_cmd->is_waiting = 0; 3560 drv_cmd->callback = mpi3mr_dev_rmhs_complete_iou; 3561 iou_ctrl.Operation = drv_cmd->iou_rc; 3562 iou_ctrl.Param16[0] = htole16(drv_cmd->dev_handle); 3563 iou_ctrl.HostTag = htole16(drv_cmd->host_tag); 3564 iou_ctrl.Function = MPI3_FUNCTION_IO_UNIT_CONTROL; 3565 3566 retval = mpi3mr_submit_admin_cmd(sc, &iou_ctrl, sizeof(iou_ctrl)); 3567 if (retval) { 3568 printf(IOCNAME "Issue DevRmHsTMIOUCTL: Admin post failed\n", 3569 sc->name); 3570 goto out_failed; 3571 } 3572 3573 return; 3574 out_failed: 3575 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3576 drv_cmd->callback = NULL; 3577 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE; 3578 drv_cmd->retry_count = 0; 3579 mpi3mr_clear_bit(cmd_idx, sc->devrem_bitmap); 3580 } 3581 3582 /** 3583 * mpi3mr_dev_rmhs_send_tm - Issue TM for device removal 3584 * @sc: Adapter instance reference 3585 * @handle: Device handle 3586 * @cmdparam: Internal command tracker 3587 * @iou_rc: IO Unit reason code 3588 * 3589 * Issues a target reset TM to the firmware or add it to a pend 3590 * list as part of device removal or hidden acknowledgment 3591 * handshake. 3592 * 3593 * Return: Nothing 3594 */ 3595 static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_softc *sc, U16 handle, 3596 struct mpi3mr_drvr_cmd *cmdparam, U8 iou_rc) 3597 { 3598 Mpi3SCSITaskMgmtRequest_t tm_req; 3599 int retval = 0; 3600 U16 cmd_idx = MPI3MR_NUM_DEVRMCMD; 3601 U8 retrycount = 5; 3602 struct mpi3mr_drvr_cmd *drv_cmd = cmdparam; 3603 struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL; 3604 struct mpi3mr_target *tgtdev = NULL; 3605 3606 mtx_lock_spin(&sc->target_lock); 3607 TAILQ_FOREACH(tgtdev, &sc->cam_sc->tgt_list, tgt_next) { 3608 if ((tgtdev->dev_handle == handle) && 3609 (iou_rc == MPI3_CTRL_OP_REMOVE_DEVICE)) { 3610 tgtdev->state = MPI3MR_DEV_REMOVE_HS_STARTED; 3611 break; 3612 } 3613 } 3614 mtx_unlock_spin(&sc->target_lock); 3615 3616 if (drv_cmd) 3617 goto issue_cmd; 3618 do { 3619 cmd_idx = mpi3mr_find_first_zero_bit(sc->devrem_bitmap, 3620 MPI3MR_NUM_DEVRMCMD); 3621 if (cmd_idx < MPI3MR_NUM_DEVRMCMD) { 3622 if (!mpi3mr_test_and_set_bit(cmd_idx, sc->devrem_bitmap)) 3623 break; 3624 cmd_idx = MPI3MR_NUM_DEVRMCMD; 3625 } 3626 } while (retrycount--); 3627 3628 if (cmd_idx >= MPI3MR_NUM_DEVRMCMD) { 3629 delayed_dev_rmhs = malloc(sizeof(*delayed_dev_rmhs),M_MPI3MR, 3630 M_ZERO|M_NOWAIT); 3631 3632 if (!delayed_dev_rmhs) 3633 return; 3634 delayed_dev_rmhs->handle = handle; 3635 delayed_dev_rmhs->iou_rc = iou_rc; 3636 TAILQ_INSERT_TAIL(&(sc->delayed_rmhs_list), delayed_dev_rmhs, list); 3637 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :DevRmHs: tr:handle(0x%04x) is postponed\n", 3638 __func__, handle); 3639 3640 3641 return; 3642 } 3643 drv_cmd = &sc->dev_rmhs_cmds[cmd_idx]; 3644 3645 issue_cmd: 3646 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 3647 mpi3mr_dprint(sc, MPI3MR_EVENT, 3648 "%s :Issuing TR TM: for devhandle 0x%04x with dev_rmhs %d\n", 3649 __func__, handle, cmd_idx); 3650 3651 memset(&tm_req, 0, sizeof(tm_req)); 3652 if (drv_cmd->state & MPI3MR_CMD_PENDING) { 3653 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :Issue TM: Command is in use\n", __func__); 3654 goto out; 3655 } 3656 drv_cmd->state = MPI3MR_CMD_PENDING; 3657 drv_cmd->is_waiting = 0; 3658 drv_cmd->callback = mpi3mr_dev_rmhs_complete_tm; 3659 drv_cmd->dev_handle = handle; 3660 drv_cmd->iou_rc = iou_rc; 3661 tm_req.DevHandle = htole16(handle); 3662 tm_req.TaskType = MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET; 3663 tm_req.HostTag = htole16(drv_cmd->host_tag); 3664 tm_req.TaskHostTag = htole16(MPI3MR_HOSTTAG_INVALID); 3665 tm_req.Function = MPI3_FUNCTION_SCSI_TASK_MGMT; 3666 3667 mpi3mr_set_bit(handle, sc->removepend_bitmap); 3668 retval = mpi3mr_submit_admin_cmd(sc, &tm_req, sizeof(tm_req)); 3669 if (retval) { 3670 mpi3mr_dprint(sc, MPI3MR_ERROR, "%s :Issue DevRmHsTM: Admin Post failed\n", 3671 __func__); 3672 goto out_failed; 3673 } 3674 out: 3675 return; 3676 out_failed: 3677 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3678 drv_cmd->callback = NULL; 3679 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE; 3680 drv_cmd->retry_count = 0; 3681 mpi3mr_clear_bit(cmd_idx, sc->devrem_bitmap); 3682 } 3683 3684 /** 3685 * mpi3mr_complete_evt_ack - Event ack request completion 3686 * @sc: Adapter instance reference 3687 * @drv_cmd: Internal command tracker 3688 * 3689 * This is the completion handler for non blocking event 3690 * acknowledgment sent to the firmware and this will issue any 3691 * pending event acknowledgment request. 3692 * 3693 * Return: Nothing 3694 */ 3695 static void mpi3mr_complete_evt_ack(struct mpi3mr_softc *sc, 3696 struct mpi3mr_drvr_cmd *drv_cmd) 3697 { 3698 U16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 3699 struct delayed_evtack_node *delayed_evtack = NULL; 3700 3701 if (drv_cmd->ioc_status != MPI3_IOCSTATUS_SUCCESS) { 3702 mpi3mr_dprint(sc, MPI3MR_EVENT, 3703 "%s: Failed IOCStatus(0x%04x) Loginfo(0x%08x)\n", __func__, 3704 (drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3705 drv_cmd->ioc_loginfo); 3706 } 3707 3708 if (!TAILQ_EMPTY(&sc->delayed_evtack_cmds_list)) { 3709 delayed_evtack = TAILQ_FIRST(&sc->delayed_evtack_cmds_list); 3710 mpi3mr_dprint(sc, MPI3MR_EVENT, 3711 "%s: processing delayed event ack for event %d\n", 3712 __func__, delayed_evtack->event); 3713 mpi3mr_send_evt_ack(sc, delayed_evtack->event, drv_cmd, 3714 delayed_evtack->event_ctx); 3715 TAILQ_REMOVE(&sc->delayed_evtack_cmds_list, delayed_evtack, list); 3716 free(delayed_evtack, M_MPI3MR); 3717 return; 3718 } 3719 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3720 drv_cmd->callback = NULL; 3721 mpi3mr_clear_bit(cmd_idx, sc->evtack_cmds_bitmap); 3722 } 3723 3724 /** 3725 * mpi3mr_send_evt_ack - Issue event acknwoledgment request 3726 * @sc: Adapter instance reference 3727 * @event: MPI3 event id 3728 * @cmdparam: Internal command tracker 3729 * @event_ctx: Event context 3730 * 3731 * Issues event acknowledgment request to the firmware if there 3732 * is a free command to send the event ack else it to a pend 3733 * list so that it will be processed on a completion of a prior 3734 * event acknowledgment . 3735 * 3736 * Return: Nothing 3737 */ 3738 static void mpi3mr_send_evt_ack(struct mpi3mr_softc *sc, U8 event, 3739 struct mpi3mr_drvr_cmd *cmdparam, U32 event_ctx) 3740 { 3741 Mpi3EventAckRequest_t evtack_req; 3742 int retval = 0; 3743 U8 retrycount = 5; 3744 U16 cmd_idx = MPI3MR_NUM_EVTACKCMD; 3745 struct mpi3mr_drvr_cmd *drv_cmd = cmdparam; 3746 struct delayed_evtack_node *delayed_evtack = NULL; 3747 3748 if (drv_cmd) 3749 goto issue_cmd; 3750 do { 3751 cmd_idx = mpi3mr_find_first_zero_bit(sc->evtack_cmds_bitmap, 3752 MPI3MR_NUM_EVTACKCMD); 3753 if (cmd_idx < MPI3MR_NUM_EVTACKCMD) { 3754 if (!mpi3mr_test_and_set_bit(cmd_idx, 3755 sc->evtack_cmds_bitmap)) 3756 break; 3757 cmd_idx = MPI3MR_NUM_EVTACKCMD; 3758 } 3759 } while (retrycount--); 3760 3761 if (cmd_idx >= MPI3MR_NUM_EVTACKCMD) { 3762 delayed_evtack = malloc(sizeof(*delayed_evtack),M_MPI3MR, 3763 M_ZERO | M_NOWAIT); 3764 if (!delayed_evtack) 3765 return; 3766 delayed_evtack->event = event; 3767 delayed_evtack->event_ctx = event_ctx; 3768 TAILQ_INSERT_TAIL(&(sc->delayed_evtack_cmds_list), delayed_evtack, list); 3769 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s : Event ack for event:%d is postponed\n", 3770 __func__, event); 3771 return; 3772 } 3773 drv_cmd = &sc->evtack_cmds[cmd_idx]; 3774 3775 issue_cmd: 3776 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 3777 3778 memset(&evtack_req, 0, sizeof(evtack_req)); 3779 if (drv_cmd->state & MPI3MR_CMD_PENDING) { 3780 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s: Command is in use\n", __func__); 3781 goto out; 3782 } 3783 drv_cmd->state = MPI3MR_CMD_PENDING; 3784 drv_cmd->is_waiting = 0; 3785 drv_cmd->callback = mpi3mr_complete_evt_ack; 3786 evtack_req.HostTag = htole16(drv_cmd->host_tag); 3787 evtack_req.Function = MPI3_FUNCTION_EVENT_ACK; 3788 evtack_req.Event = event; 3789 evtack_req.EventContext = htole32(event_ctx); 3790 retval = mpi3mr_submit_admin_cmd(sc, &evtack_req, 3791 sizeof(evtack_req)); 3792 3793 if (retval) { 3794 mpi3mr_dprint(sc, MPI3MR_ERROR, "%s: Admin Post failed\n", __func__); 3795 goto out_failed; 3796 } 3797 out: 3798 return; 3799 out_failed: 3800 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3801 drv_cmd->callback = NULL; 3802 mpi3mr_clear_bit(cmd_idx, sc->evtack_cmds_bitmap); 3803 } 3804 3805 /* 3806 * mpi3mr_pcietopochg_evt_th - PCIETopologyChange evt tophalf 3807 * @sc: Adapter instance reference 3808 * @event_reply: Event data 3809 * 3810 * Checks for the reason code and based on that either block I/O 3811 * to device, or unblock I/O to the device, or start the device 3812 * removal handshake with reason as remove with the firmware for 3813 * PCIe devices. 3814 * 3815 * Return: Nothing 3816 */ 3817 static void mpi3mr_pcietopochg_evt_th(struct mpi3mr_softc *sc, 3818 Mpi3EventNotificationReply_t *event_reply) 3819 { 3820 Mpi3EventDataPcieTopologyChangeList_t *topo_evt = 3821 (Mpi3EventDataPcieTopologyChangeList_t *) event_reply->EventData; 3822 int i; 3823 U16 handle; 3824 U8 reason_code; 3825 struct mpi3mr_target *tgtdev = NULL; 3826 3827 for (i = 0; i < topo_evt->NumEntries; i++) { 3828 handle = le16toh(topo_evt->PortEntry[i].AttachedDevHandle); 3829 if (!handle) 3830 continue; 3831 reason_code = topo_evt->PortEntry[i].PortStatus; 3832 tgtdev = mpi3mr_find_target_by_dev_handle(sc->cam_sc, handle); 3833 switch (reason_code) { 3834 case MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING: 3835 if (tgtdev) { 3836 tgtdev->dev_removed = 1; 3837 tgtdev->dev_removedelay = 0; 3838 mpi3mr_atomic_set(&tgtdev->block_io, 0); 3839 } 3840 mpi3mr_dev_rmhs_send_tm(sc, handle, NULL, 3841 MPI3_CTRL_OP_REMOVE_DEVICE); 3842 break; 3843 case MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING: 3844 if (tgtdev) { 3845 tgtdev->dev_removedelay = 1; 3846 mpi3mr_atomic_inc(&tgtdev->block_io); 3847 } 3848 break; 3849 case MPI3_EVENT_PCIE_TOPO_PS_RESPONDING: 3850 if (tgtdev && 3851 tgtdev->dev_removedelay) { 3852 tgtdev->dev_removedelay = 0; 3853 if (mpi3mr_atomic_read(&tgtdev->block_io) > 0) 3854 mpi3mr_atomic_dec(&tgtdev->block_io); 3855 } 3856 break; 3857 case MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED: 3858 default: 3859 break; 3860 } 3861 } 3862 } 3863 3864 /** 3865 * mpi3mr_sastopochg_evt_th - SASTopologyChange evt tophalf 3866 * @sc: Adapter instance reference 3867 * @event_reply: Event data 3868 * 3869 * Checks for the reason code and based on that either block I/O 3870 * to device, or unblock I/O to the device, or start the device 3871 * removal handshake with reason as remove with the firmware for 3872 * SAS/SATA devices. 3873 * 3874 * Return: Nothing 3875 */ 3876 static void mpi3mr_sastopochg_evt_th(struct mpi3mr_softc *sc, 3877 Mpi3EventNotificationReply_t *event_reply) 3878 { 3879 Mpi3EventDataSasTopologyChangeList_t *topo_evt = 3880 (Mpi3EventDataSasTopologyChangeList_t *)event_reply->EventData; 3881 int i; 3882 U16 handle; 3883 U8 reason_code; 3884 struct mpi3mr_target *tgtdev = NULL; 3885 3886 for (i = 0; i < topo_evt->NumEntries; i++) { 3887 handle = le16toh(topo_evt->PhyEntry[i].AttachedDevHandle); 3888 if (!handle) 3889 continue; 3890 reason_code = topo_evt->PhyEntry[i].Status & 3891 MPI3_EVENT_SAS_TOPO_PHY_RC_MASK; 3892 tgtdev = mpi3mr_find_target_by_dev_handle(sc->cam_sc, handle); 3893 switch (reason_code) { 3894 case MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING: 3895 if (tgtdev) { 3896 tgtdev->dev_removed = 1; 3897 tgtdev->dev_removedelay = 0; 3898 mpi3mr_atomic_set(&tgtdev->block_io, 0); 3899 } 3900 mpi3mr_dev_rmhs_send_tm(sc, handle, NULL, 3901 MPI3_CTRL_OP_REMOVE_DEVICE); 3902 break; 3903 case MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING: 3904 if (tgtdev) { 3905 tgtdev->dev_removedelay = 1; 3906 mpi3mr_atomic_inc(&tgtdev->block_io); 3907 } 3908 break; 3909 case MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING: 3910 if (tgtdev && 3911 tgtdev->dev_removedelay) { 3912 tgtdev->dev_removedelay = 0; 3913 if (mpi3mr_atomic_read(&tgtdev->block_io) > 0) 3914 mpi3mr_atomic_dec(&tgtdev->block_io); 3915 } 3916 case MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED: 3917 default: 3918 break; 3919 } 3920 } 3921 3922 } 3923 /** 3924 * mpi3mr_devstatuschg_evt_th - DeviceStatusChange evt tophalf 3925 * @sc: Adapter instance reference 3926 * @event_reply: Event data 3927 * 3928 * Checks for the reason code and based on that either block I/O 3929 * to device, or unblock I/O to the device, or start the device 3930 * removal handshake with reason as remove/hide acknowledgment 3931 * with the firmware. 3932 * 3933 * Return: Nothing 3934 */ 3935 static void mpi3mr_devstatuschg_evt_th(struct mpi3mr_softc *sc, 3936 Mpi3EventNotificationReply_t *event_reply) 3937 { 3938 U16 dev_handle = 0; 3939 U8 ublock = 0, block = 0, hide = 0, uhide = 0, delete = 0, remove = 0; 3940 struct mpi3mr_target *tgtdev = NULL; 3941 Mpi3EventDataDeviceStatusChange_t *evtdata = 3942 (Mpi3EventDataDeviceStatusChange_t *) event_reply->EventData; 3943 3944 dev_handle = le16toh(evtdata->DevHandle); 3945 3946 switch (evtdata->ReasonCode) { 3947 case MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT: 3948 case MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT: 3949 block = 1; 3950 break; 3951 case MPI3_EVENT_DEV_STAT_RC_HIDDEN: 3952 delete = 1; 3953 hide = 1; 3954 break; 3955 case MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN: 3956 uhide = 1; 3957 break; 3958 case MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING: 3959 delete = 1; 3960 remove = 1; 3961 break; 3962 case MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP: 3963 case MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP: 3964 ublock = 1; 3965 break; 3966 default: 3967 break; 3968 } 3969 3970 tgtdev = mpi3mr_find_target_by_dev_handle(sc->cam_sc, dev_handle); 3971 3972 if (!tgtdev) { 3973 mpi3mr_dprint(sc, MPI3MR_ERROR, "%s :target with dev_handle:0x%x not found\n", 3974 __func__, dev_handle); 3975 return; 3976 } 3977 3978 if (block) 3979 mpi3mr_atomic_inc(&tgtdev->block_io); 3980 3981 if (hide) 3982 tgtdev->is_hidden = hide; 3983 3984 if (uhide) { 3985 tgtdev->is_hidden = 0; 3986 tgtdev->dev_removed = 0; 3987 } 3988 3989 if (delete) 3990 tgtdev->dev_removed = 1; 3991 3992 if (ublock) { 3993 if (mpi3mr_atomic_read(&tgtdev->block_io) > 0) 3994 mpi3mr_atomic_dec(&tgtdev->block_io); 3995 } 3996 3997 if (remove) { 3998 mpi3mr_dev_rmhs_send_tm(sc, dev_handle, NULL, 3999 MPI3_CTRL_OP_REMOVE_DEVICE); 4000 } 4001 if (hide) 4002 mpi3mr_dev_rmhs_send_tm(sc, dev_handle, NULL, 4003 MPI3_CTRL_OP_HIDDEN_ACK); 4004 } 4005 4006 /** 4007 * mpi3mr_preparereset_evt_th - Prepareforreset evt tophalf 4008 * @sc: Adapter instance reference 4009 * @event_reply: Event data 4010 * 4011 * Blocks and unblocks host level I/O based on the reason code 4012 * 4013 * Return: Nothing 4014 */ 4015 static void mpi3mr_preparereset_evt_th(struct mpi3mr_softc *sc, 4016 Mpi3EventNotificationReply_t *event_reply) 4017 { 4018 Mpi3EventDataPrepareForReset_t *evtdata = 4019 (Mpi3EventDataPrepareForReset_t *)event_reply->EventData; 4020 4021 if (evtdata->ReasonCode == MPI3_EVENT_PREPARE_RESET_RC_START) { 4022 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :Recieved PrepForReset Event with RC=START\n", 4023 __func__); 4024 if (sc->prepare_for_reset) 4025 return; 4026 sc->prepare_for_reset = 1; 4027 sc->prepare_for_reset_timeout_counter = 0; 4028 } else if (evtdata->ReasonCode == MPI3_EVENT_PREPARE_RESET_RC_ABORT) { 4029 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :Recieved PrepForReset Event with RC=ABORT\n", 4030 __func__); 4031 sc->prepare_for_reset = 0; 4032 sc->prepare_for_reset_timeout_counter = 0; 4033 } 4034 if ((event_reply->MsgFlags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK) 4035 == MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED) 4036 mpi3mr_send_evt_ack(sc, event_reply->Event, NULL, 4037 le32toh(event_reply->EventContext)); 4038 } 4039 4040 /** 4041 * mpi3mr_energypackchg_evt_th - Energypackchange evt tophalf 4042 * @sc: Adapter instance reference 4043 * @event_reply: Event data 4044 * 4045 * Identifies the new shutdown timeout value and update. 4046 * 4047 * Return: Nothing 4048 */ 4049 static void mpi3mr_energypackchg_evt_th(struct mpi3mr_softc *sc, 4050 Mpi3EventNotificationReply_t *event_reply) 4051 { 4052 Mpi3EventDataEnergyPackChange_t *evtdata = 4053 (Mpi3EventDataEnergyPackChange_t *)event_reply->EventData; 4054 U16 shutdown_timeout = le16toh(evtdata->ShutdownTimeout); 4055 4056 if (shutdown_timeout <= 0) { 4057 mpi3mr_dprint(sc, MPI3MR_ERROR, 4058 "%s :Invalid Shutdown Timeout received = %d\n", 4059 __func__, shutdown_timeout); 4060 return; 4061 } 4062 4063 mpi3mr_dprint(sc, MPI3MR_EVENT, 4064 "%s :Previous Shutdown Timeout Value = %d New Shutdown Timeout Value = %d\n", 4065 __func__, sc->facts.shutdown_timeout, shutdown_timeout); 4066 sc->facts.shutdown_timeout = shutdown_timeout; 4067 } 4068 4069 /** 4070 * mpi3mr_cablemgmt_evt_th - Cable mgmt evt tophalf 4071 * @sc: Adapter instance reference 4072 * @event_reply: Event data 4073 * 4074 * Displays Cable manegemt event details. 4075 * 4076 * Return: Nothing 4077 */ 4078 static void mpi3mr_cablemgmt_evt_th(struct mpi3mr_softc *sc, 4079 Mpi3EventNotificationReply_t *event_reply) 4080 { 4081 Mpi3EventDataCableManagement_t *evtdata = 4082 (Mpi3EventDataCableManagement_t *)event_reply->EventData; 4083 4084 switch (evtdata->Status) { 4085 case MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER: 4086 { 4087 mpi3mr_dprint(sc, MPI3MR_INFO, "An active cable with ReceptacleID %d cannot be powered.\n" 4088 "Devices connected to this cable are not detected.\n" 4089 "This cable requires %d mW of power.\n", 4090 evtdata->ReceptacleID, 4091 le32toh(evtdata->ActiveCablePowerRequirement)); 4092 break; 4093 } 4094 case MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED: 4095 { 4096 mpi3mr_dprint(sc, MPI3MR_INFO, "A cable with ReceptacleID %d is not running at optimal speed\n", 4097 evtdata->ReceptacleID); 4098 break; 4099 } 4100 default: 4101 break; 4102 } 4103 } 4104 4105 /** 4106 * mpi3mr_process_events - Event's toph-half handler 4107 * @sc: Adapter instance reference 4108 * @event_reply: Event data 4109 * 4110 * Top half of event processing. 4111 * 4112 * Return: Nothing 4113 */ 4114 static void mpi3mr_process_events(struct mpi3mr_softc *sc, 4115 uintptr_t data, Mpi3EventNotificationReply_t *event_reply) 4116 { 4117 U16 evt_type; 4118 bool ack_req = 0, process_evt_bh = 0; 4119 struct mpi3mr_fw_event_work *fw_event; 4120 U16 sz; 4121 4122 if (sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN) 4123 goto out; 4124 4125 if ((event_reply->MsgFlags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK) 4126 == MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED) 4127 ack_req = 1; 4128 4129 evt_type = event_reply->Event; 4130 4131 switch (evt_type) { 4132 case MPI3_EVENT_DEVICE_ADDED: 4133 { 4134 Mpi3DevicePage0_t *dev_pg0 = 4135 (Mpi3DevicePage0_t *) event_reply->EventData; 4136 if (mpi3mr_create_device(sc, dev_pg0)) 4137 mpi3mr_dprint(sc, MPI3MR_ERROR, 4138 "%s :Failed to add device in the device add event\n", 4139 __func__); 4140 else 4141 process_evt_bh = 1; 4142 break; 4143 } 4144 4145 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 4146 { 4147 process_evt_bh = 1; 4148 mpi3mr_devstatuschg_evt_th(sc, event_reply); 4149 break; 4150 } 4151 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 4152 { 4153 process_evt_bh = 1; 4154 mpi3mr_sastopochg_evt_th(sc, event_reply); 4155 break; 4156 } 4157 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 4158 { 4159 process_evt_bh = 1; 4160 mpi3mr_pcietopochg_evt_th(sc, event_reply); 4161 break; 4162 } 4163 case MPI3_EVENT_PREPARE_FOR_RESET: 4164 { 4165 mpi3mr_preparereset_evt_th(sc, event_reply); 4166 ack_req = 0; 4167 break; 4168 } 4169 case MPI3_EVENT_DEVICE_INFO_CHANGED: 4170 case MPI3_EVENT_LOG_DATA: 4171 { 4172 process_evt_bh = 1; 4173 break; 4174 } 4175 case MPI3_EVENT_ENERGY_PACK_CHANGE: 4176 { 4177 mpi3mr_energypackchg_evt_th(sc, event_reply); 4178 break; 4179 } 4180 case MPI3_EVENT_CABLE_MGMT: 4181 { 4182 mpi3mr_cablemgmt_evt_th(sc, event_reply); 4183 break; 4184 } 4185 4186 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 4187 case MPI3_EVENT_SAS_DISCOVERY: 4188 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 4189 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 4190 case MPI3_EVENT_PCIE_ENUMERATION: 4191 break; 4192 default: 4193 mpi3mr_dprint(sc, MPI3MR_INFO, "%s :Event 0x%02x is not handled by driver\n", 4194 __func__, evt_type); 4195 break; 4196 } 4197 4198 if (process_evt_bh || ack_req) { 4199 fw_event = malloc(sizeof(struct mpi3mr_fw_event_work), M_MPI3MR, 4200 M_ZERO|M_NOWAIT); 4201 4202 if (!fw_event) { 4203 printf("%s: allocate failed for fw_event\n", __func__); 4204 return; 4205 } 4206 4207 sz = le16toh(event_reply->EventDataLength) * 4; 4208 fw_event->event_data = malloc(sz, M_MPI3MR, M_ZERO|M_NOWAIT); 4209 4210 if (!fw_event->event_data) { 4211 printf("%s: allocate failed for event_data\n", __func__); 4212 free(fw_event, M_MPI3MR); 4213 return; 4214 } 4215 4216 bcopy(event_reply->EventData, fw_event->event_data, sz); 4217 fw_event->event = event_reply->Event; 4218 if ((event_reply->Event == MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST || 4219 event_reply->Event == MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST || 4220 event_reply->Event == MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE ) && 4221 sc->track_mapping_events) 4222 sc->pending_map_events++; 4223 4224 /* 4225 * Events should be processed after Port enable is completed. 4226 */ 4227 if ((event_reply->Event == MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST || 4228 event_reply->Event == MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST ) && 4229 !(sc->mpi3mr_flags & MPI3MR_FLAGS_PORT_ENABLE_DONE)) 4230 mpi3mr_startup_increment(sc->cam_sc); 4231 4232 fw_event->send_ack = ack_req; 4233 fw_event->event_context = le32toh(event_reply->EventContext); 4234 fw_event->event_data_size = sz; 4235 fw_event->process_event = process_evt_bh; 4236 4237 mtx_lock(&sc->fwevt_lock); 4238 TAILQ_INSERT_TAIL(&sc->cam_sc->ev_queue, fw_event, ev_link); 4239 taskqueue_enqueue(sc->cam_sc->ev_tq, &sc->cam_sc->ev_task); 4240 mtx_unlock(&sc->fwevt_lock); 4241 4242 } 4243 out: 4244 return; 4245 } 4246 4247 static void mpi3mr_handle_events(struct mpi3mr_softc *sc, uintptr_t data, 4248 Mpi3DefaultReply_t *def_reply) 4249 { 4250 Mpi3EventNotificationReply_t *event_reply = 4251 (Mpi3EventNotificationReply_t *)def_reply; 4252 4253 sc->change_count = event_reply->IOCChangeCount; 4254 mpi3mr_display_event_data(sc, event_reply); 4255 4256 mpi3mr_process_events(sc, data, event_reply); 4257 } 4258 4259 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_softc *sc, 4260 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma) 4261 { 4262 U16 reply_desc_type, host_tag = 0, idx; 4263 U16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 4264 U32 ioc_loginfo = 0; 4265 Mpi3StatusReplyDescriptor_t *status_desc; 4266 Mpi3AddressReplyDescriptor_t *addr_desc; 4267 Mpi3SuccessReplyDescriptor_t *success_desc; 4268 Mpi3DefaultReply_t *def_reply = NULL; 4269 struct mpi3mr_drvr_cmd *cmdptr = NULL; 4270 Mpi3SCSIIOReply_t *scsi_reply; 4271 U8 *sense_buf = NULL; 4272 4273 *reply_dma = 0; 4274 reply_desc_type = reply_desc->ReplyFlags & 4275 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 4276 switch (reply_desc_type) { 4277 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 4278 status_desc = (Mpi3StatusReplyDescriptor_t *)reply_desc; 4279 host_tag = status_desc->HostTag; 4280 ioc_status = status_desc->IOCStatus; 4281 if (ioc_status & 4282 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 4283 ioc_loginfo = status_desc->IOCLogInfo; 4284 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 4285 break; 4286 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 4287 addr_desc = (Mpi3AddressReplyDescriptor_t *)reply_desc; 4288 *reply_dma = addr_desc->ReplyFrameAddress; 4289 def_reply = mpi3mr_get_reply_virt_addr(sc, *reply_dma); 4290 if (def_reply == NULL) 4291 goto out; 4292 host_tag = def_reply->HostTag; 4293 ioc_status = def_reply->IOCStatus; 4294 if (ioc_status & 4295 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 4296 ioc_loginfo = def_reply->IOCLogInfo; 4297 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 4298 if (def_reply->Function == MPI3_FUNCTION_SCSI_IO) { 4299 scsi_reply = (Mpi3SCSIIOReply_t *)def_reply; 4300 sense_buf = mpi3mr_get_sensebuf_virt_addr(sc, 4301 scsi_reply->SenseDataBufferAddress); 4302 } 4303 break; 4304 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 4305 success_desc = (Mpi3SuccessReplyDescriptor_t *)reply_desc; 4306 host_tag = success_desc->HostTag; 4307 break; 4308 default: 4309 break; 4310 } 4311 switch (host_tag) { 4312 case MPI3MR_HOSTTAG_INITCMDS: 4313 cmdptr = &sc->init_cmds; 4314 break; 4315 case MPI3MR_HOSTTAG_IOCTLCMDS: 4316 cmdptr = &sc->ioctl_cmds; 4317 break; 4318 case MPI3MR_HOSTTAG_TMS: 4319 cmdptr = &sc->host_tm_cmds; 4320 wakeup((void *)&sc->tm_chan); 4321 break; 4322 case MPI3MR_HOSTTAG_PELABORT: 4323 cmdptr = &sc->pel_abort_cmd; 4324 break; 4325 case MPI3MR_HOSTTAG_PELWAIT: 4326 cmdptr = &sc->pel_cmds; 4327 break; 4328 case MPI3MR_HOSTTAG_INVALID: 4329 if (def_reply && def_reply->Function == 4330 MPI3_FUNCTION_EVENT_NOTIFICATION) 4331 mpi3mr_handle_events(sc, *reply_dma ,def_reply); 4332 default: 4333 break; 4334 } 4335 4336 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 4337 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX ) { 4338 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 4339 cmdptr = &sc->dev_rmhs_cmds[idx]; 4340 } 4341 4342 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN && 4343 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) { 4344 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 4345 cmdptr = &sc->evtack_cmds[idx]; 4346 } 4347 4348 if (cmdptr) { 4349 if (cmdptr->state & MPI3MR_CMD_PENDING) { 4350 cmdptr->state |= MPI3MR_CMD_COMPLETE; 4351 cmdptr->ioc_loginfo = ioc_loginfo; 4352 cmdptr->ioc_status = ioc_status; 4353 cmdptr->state &= ~MPI3MR_CMD_PENDING; 4354 if (def_reply) { 4355 cmdptr->state |= MPI3MR_CMD_REPLYVALID; 4356 memcpy((U8 *)cmdptr->reply, (U8 *)def_reply, 4357 sc->reply_sz); 4358 } 4359 if (sense_buf && cmdptr->sensebuf) { 4360 cmdptr->is_senseprst = 1; 4361 memcpy(cmdptr->sensebuf, sense_buf, 4362 MPI3MR_SENSEBUF_SZ); 4363 } 4364 if (cmdptr->is_waiting) { 4365 complete(&cmdptr->completion); 4366 cmdptr->is_waiting = 0; 4367 } else if (cmdptr->callback) 4368 cmdptr->callback(sc, cmdptr); 4369 } 4370 } 4371 out: 4372 if (sense_buf != NULL) 4373 mpi3mr_repost_sense_buf(sc, 4374 scsi_reply->SenseDataBufferAddress); 4375 return; 4376 } 4377 4378 /* 4379 * mpi3mr_complete_admin_cmd: ISR routine for admin commands 4380 * @sc: Adapter's soft instance 4381 * 4382 * This function processes admin command completions. 4383 */ 4384 static int mpi3mr_complete_admin_cmd(struct mpi3mr_softc *sc) 4385 { 4386 U32 exp_phase = sc->admin_reply_ephase; 4387 U32 adm_reply_ci = sc->admin_reply_ci; 4388 U32 num_adm_reply = 0; 4389 U64 reply_dma = 0; 4390 Mpi3DefaultReplyDescriptor_t *reply_desc; 4391 4392 mtx_lock_spin(&sc->admin_reply_lock); 4393 if (sc->admin_in_use == false) { 4394 sc->admin_in_use = true; 4395 mtx_unlock_spin(&sc->admin_reply_lock); 4396 } else { 4397 mtx_unlock_spin(&sc->admin_reply_lock); 4398 return 0; 4399 } 4400 4401 reply_desc = (Mpi3DefaultReplyDescriptor_t *)sc->admin_reply + 4402 adm_reply_ci; 4403 4404 if ((reply_desc->ReplyFlags & 4405 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 4406 mtx_lock_spin(&sc->admin_reply_lock); 4407 sc->admin_in_use = false; 4408 mtx_unlock_spin(&sc->admin_reply_lock); 4409 return 0; 4410 } 4411 4412 do { 4413 sc->admin_req_ci = reply_desc->RequestQueueCI; 4414 mpi3mr_process_admin_reply_desc(sc, reply_desc, &reply_dma); 4415 if (reply_dma) 4416 mpi3mr_repost_reply_buf(sc, reply_dma); 4417 num_adm_reply++; 4418 if (++adm_reply_ci == sc->num_admin_replies) { 4419 adm_reply_ci = 0; 4420 exp_phase ^= 1; 4421 } 4422 reply_desc = 4423 (Mpi3DefaultReplyDescriptor_t *)sc->admin_reply + 4424 adm_reply_ci; 4425 if ((reply_desc->ReplyFlags & 4426 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 4427 break; 4428 } while (1); 4429 4430 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET, adm_reply_ci); 4431 sc->admin_reply_ci = adm_reply_ci; 4432 sc->admin_reply_ephase = exp_phase; 4433 mtx_lock_spin(&sc->admin_reply_lock); 4434 sc->admin_in_use = false; 4435 mtx_unlock_spin(&sc->admin_reply_lock); 4436 return num_adm_reply; 4437 } 4438 4439 static void 4440 mpi3mr_cmd_done(struct mpi3mr_softc *sc, struct mpi3mr_cmd *cmd) 4441 { 4442 mpi3mr_unmap_request(sc, cmd); 4443 4444 mtx_lock(&sc->mpi3mr_mtx); 4445 if (cmd->callout_owner) { 4446 callout_stop(&cmd->callout); 4447 cmd->callout_owner = false; 4448 } 4449 4450 if (sc->unrecoverable) 4451 mpi3mr_set_ccbstatus(cmd->ccb, CAM_DEV_NOT_THERE); 4452 4453 xpt_done(cmd->ccb); 4454 cmd->ccb = NULL; 4455 mtx_unlock(&sc->mpi3mr_mtx); 4456 mpi3mr_release_command(cmd); 4457 } 4458 4459 void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, 4460 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma) 4461 { 4462 U16 reply_desc_type, host_tag = 0; 4463 U16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 4464 U32 ioc_loginfo = 0; 4465 Mpi3StatusReplyDescriptor_t *status_desc = NULL; 4466 Mpi3AddressReplyDescriptor_t *addr_desc = NULL; 4467 Mpi3SuccessReplyDescriptor_t *success_desc = NULL; 4468 Mpi3SCSIIOReply_t *scsi_reply = NULL; 4469 U8 *sense_buf = NULL; 4470 U8 scsi_state = 0, scsi_status = 0, sense_state = 0; 4471 U32 xfer_count = 0, sense_count =0, resp_data = 0; 4472 struct mpi3mr_cmd *cm = NULL; 4473 union ccb *ccb; 4474 struct ccb_scsiio *csio; 4475 struct mpi3mr_cam_softc *cam_sc; 4476 U32 target_id; 4477 U8 *scsi_cdb; 4478 struct mpi3mr_target *target = NULL; 4479 U32 ioc_pend_data_len = 0, tg_pend_data_len = 0, data_len_blks = 0; 4480 struct mpi3mr_throttle_group_info *tg = NULL; 4481 U8 throttle_enabled_dev = 0; 4482 static int ratelimit; 4483 4484 *reply_dma = 0; 4485 reply_desc_type = reply_desc->ReplyFlags & 4486 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 4487 switch (reply_desc_type) { 4488 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 4489 status_desc = (Mpi3StatusReplyDescriptor_t *)reply_desc; 4490 host_tag = status_desc->HostTag; 4491 ioc_status = status_desc->IOCStatus; 4492 if (ioc_status & 4493 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 4494 ioc_loginfo = status_desc->IOCLogInfo; 4495 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 4496 break; 4497 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 4498 addr_desc = (Mpi3AddressReplyDescriptor_t *)reply_desc; 4499 *reply_dma = addr_desc->ReplyFrameAddress; 4500 scsi_reply = mpi3mr_get_reply_virt_addr(sc, 4501 *reply_dma); 4502 if (scsi_reply == NULL) { 4503 mpi3mr_dprint(sc, MPI3MR_ERROR, "scsi_reply is NULL, " 4504 "this shouldn't happen, reply_desc: %p\n", 4505 reply_desc); 4506 goto out; 4507 } 4508 4509 host_tag = scsi_reply->HostTag; 4510 ioc_status = scsi_reply->IOCStatus; 4511 scsi_status = scsi_reply->SCSIStatus; 4512 scsi_state = scsi_reply->SCSIState; 4513 sense_state = (scsi_state & MPI3_SCSI_STATE_SENSE_MASK); 4514 xfer_count = scsi_reply->TransferCount; 4515 sense_count = scsi_reply->SenseCount; 4516 resp_data = scsi_reply->ResponseData; 4517 sense_buf = mpi3mr_get_sensebuf_virt_addr(sc, 4518 scsi_reply->SenseDataBufferAddress); 4519 if (ioc_status & 4520 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 4521 ioc_loginfo = scsi_reply->IOCLogInfo; 4522 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 4523 if (sense_state == MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY) 4524 mpi3mr_dprint(sc, MPI3MR_ERROR, "Ran out of sense buffers\n"); 4525 4526 break; 4527 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 4528 success_desc = (Mpi3SuccessReplyDescriptor_t *)reply_desc; 4529 host_tag = success_desc->HostTag; 4530 4531 default: 4532 break; 4533 } 4534 4535 cm = sc->cmd_list[host_tag]; 4536 4537 if (cm->state == MPI3MR_CMD_STATE_FREE) 4538 goto out; 4539 4540 cam_sc = sc->cam_sc; 4541 ccb = cm->ccb; 4542 csio = &ccb->csio; 4543 target_id = csio->ccb_h.target_id; 4544 4545 scsi_cdb = scsiio_cdb_ptr(csio); 4546 4547 target = mpi3mr_find_target_by_per_id(cam_sc, target_id); 4548 if (sc->iot_enable) { 4549 data_len_blks = csio->dxfer_len >> 9; 4550 4551 if (target) { 4552 tg = target->throttle_group; 4553 throttle_enabled_dev = 4554 target->io_throttle_enabled; 4555 } 4556 4557 if ((data_len_blks >= sc->io_throttle_data_length) && 4558 throttle_enabled_dev) { 4559 mpi3mr_atomic_sub(&sc->pend_large_data_sz, data_len_blks); 4560 ioc_pend_data_len = mpi3mr_atomic_read( 4561 &sc->pend_large_data_sz); 4562 if (tg) { 4563 mpi3mr_atomic_sub(&tg->pend_large_data_sz, 4564 data_len_blks); 4565 tg_pend_data_len = mpi3mr_atomic_read(&tg->pend_large_data_sz); 4566 if (ratelimit % 1000) { 4567 mpi3mr_dprint(sc, MPI3MR_IOT, 4568 "large vd_io completion persist_id(%d), handle(0x%04x), data_len(%d)," 4569 "ioc_pending(%d), tg_pending(%d), ioc_low(%d), tg_low(%d)\n", 4570 target->per_id, 4571 target->dev_handle, 4572 data_len_blks, ioc_pend_data_len, 4573 tg_pend_data_len, 4574 sc->io_throttle_low, 4575 tg->low); 4576 ratelimit++; 4577 } 4578 if (tg->io_divert && ((ioc_pend_data_len <= 4579 sc->io_throttle_low) && 4580 (tg_pend_data_len <= tg->low))) { 4581 tg->io_divert = 0; 4582 mpi3mr_dprint(sc, MPI3MR_IOT, 4583 "VD: Coming out of divert perst_id(%d) tg_id(%d)\n", 4584 target->per_id, tg->id); 4585 mpi3mr_set_io_divert_for_all_vd_in_tg( 4586 sc, tg, 0); 4587 } 4588 } else { 4589 if (ratelimit % 1000) { 4590 mpi3mr_dprint(sc, MPI3MR_IOT, 4591 "large pd_io completion persist_id(%d), handle(0x%04x), data_len(%d), ioc_pending(%d), ioc_low(%d)\n", 4592 target->per_id, 4593 target->dev_handle, 4594 data_len_blks, ioc_pend_data_len, 4595 sc->io_throttle_low); 4596 ratelimit++; 4597 } 4598 4599 if (ioc_pend_data_len <= sc->io_throttle_low) { 4600 target->io_divert = 0; 4601 mpi3mr_dprint(sc, MPI3MR_IOT, 4602 "PD: Coming out of divert perst_id(%d)\n", 4603 target->per_id); 4604 } 4605 } 4606 4607 } else if (target->io_divert) { 4608 ioc_pend_data_len = mpi3mr_atomic_read(&sc->pend_large_data_sz); 4609 if (!tg) { 4610 if (ratelimit % 1000) { 4611 mpi3mr_dprint(sc, MPI3MR_IOT, 4612 "pd_io completion persist_id(%d), handle(0x%04x), data_len(%d), ioc_pending(%d), ioc_low(%d)\n", 4613 target->per_id, 4614 target->dev_handle, 4615 data_len_blks, ioc_pend_data_len, 4616 sc->io_throttle_low); 4617 ratelimit++; 4618 } 4619 4620 if ( ioc_pend_data_len <= sc->io_throttle_low) { 4621 mpi3mr_dprint(sc, MPI3MR_IOT, 4622 "PD: Coming out of divert perst_id(%d)\n", 4623 target->per_id); 4624 target->io_divert = 0; 4625 } 4626 4627 } else if (ioc_pend_data_len <= sc->io_throttle_low) { 4628 tg_pend_data_len = mpi3mr_atomic_read(&tg->pend_large_data_sz); 4629 if (ratelimit % 1000) { 4630 mpi3mr_dprint(sc, MPI3MR_IOT, 4631 "vd_io completion persist_id(%d), handle(0x%04x), data_len(%d)," 4632 "ioc_pending(%d), tg_pending(%d), ioc_low(%d), tg_low(%d)\n", 4633 target->per_id, 4634 target->dev_handle, 4635 data_len_blks, ioc_pend_data_len, 4636 tg_pend_data_len, 4637 sc->io_throttle_low, 4638 tg->low); 4639 ratelimit++; 4640 } 4641 if (tg->io_divert && (tg_pend_data_len <= tg->low)) { 4642 tg->io_divert = 0; 4643 mpi3mr_dprint(sc, MPI3MR_IOT, 4644 "VD: Coming out of divert perst_id(%d) tg_id(%d)\n", 4645 target->per_id, tg->id); 4646 mpi3mr_set_io_divert_for_all_vd_in_tg( 4647 sc, tg, 0); 4648 } 4649 4650 } 4651 } 4652 } 4653 4654 if (success_desc) { 4655 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP); 4656 goto out_success; 4657 } 4658 4659 if (ioc_status == MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN 4660 && xfer_count == 0 && (scsi_status == MPI3_SCSI_STATUS_BUSY || 4661 scsi_status == MPI3_SCSI_STATUS_RESERVATION_CONFLICT || 4662 scsi_status == MPI3_SCSI_STATUS_TASK_SET_FULL)) 4663 ioc_status = MPI3_IOCSTATUS_SUCCESS; 4664 4665 if ((sense_state == MPI3_SCSI_STATE_SENSE_VALID) && sense_count 4666 && sense_buf) { 4667 int sense_len, returned_sense_len; 4668 4669 returned_sense_len = min(le32toh(sense_count), 4670 sizeof(struct scsi_sense_data)); 4671 if (returned_sense_len < csio->sense_len) 4672 csio->sense_resid = csio->sense_len - 4673 returned_sense_len; 4674 else 4675 csio->sense_resid = 0; 4676 4677 sense_len = min(returned_sense_len, 4678 csio->sense_len - csio->sense_resid); 4679 bzero(&csio->sense_data, sizeof(csio->sense_data)); 4680 bcopy(sense_buf, &csio->sense_data, sense_len); 4681 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 4682 } 4683 4684 switch (ioc_status) { 4685 case MPI3_IOCSTATUS_BUSY: 4686 case MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES: 4687 mpi3mr_set_ccbstatus(ccb, CAM_REQUEUE_REQ); 4688 break; 4689 case MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 4690 /* 4691 * If devinfo is 0 this will be a volume. In that case don't 4692 * tell CAM that the volume is not there. We want volumes to 4693 * be enumerated until they are deleted/removed, not just 4694 * failed. 4695 */ 4696 if (cm->targ->devinfo == 0) 4697 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP); 4698 else 4699 mpi3mr_set_ccbstatus(ccb, CAM_DEV_NOT_THERE); 4700 break; 4701 case MPI3_IOCSTATUS_SCSI_TASK_TERMINATED: 4702 case MPI3_IOCSTATUS_SCSI_IOC_TERMINATED: 4703 case MPI3_IOCSTATUS_SCSI_EXT_TERMINATED: 4704 mpi3mr_set_ccbstatus(ccb, CAM_SCSI_BUSY); 4705 mpi3mr_dprint(sc, MPI3MR_TRACE, 4706 "func: %s line:%d tgt %u Hosttag %u loginfo %x\n", 4707 __func__, __LINE__, 4708 target_id, cm->hosttag, 4709 le32toh(scsi_reply->IOCLogInfo)); 4710 mpi3mr_dprint(sc, MPI3MR_TRACE, 4711 "SCSIStatus %x SCSIState %x xfercount %u\n", 4712 scsi_reply->SCSIStatus, scsi_reply->SCSIState, 4713 le32toh(xfer_count)); 4714 break; 4715 case MPI3_IOCSTATUS_SCSI_DATA_OVERRUN: 4716 /* resid is ignored for this condition */ 4717 csio->resid = 0; 4718 mpi3mr_set_ccbstatus(ccb, CAM_DATA_RUN_ERR); 4719 break; 4720 case MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN: 4721 csio->resid = cm->length - le32toh(xfer_count); 4722 case MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR: 4723 case MPI3_IOCSTATUS_SUCCESS: 4724 if ((scsi_reply->IOCStatus & MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK) == 4725 MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR) 4726 mpi3mr_dprint(sc, MPI3MR_XINFO, "func: %s line: %d recovered error\n", __func__, __LINE__); 4727 4728 /* Completion failed at the transport level. */ 4729 if (scsi_reply->SCSIState & (MPI3_SCSI_STATE_NO_SCSI_STATUS | 4730 MPI3_SCSI_STATE_TERMINATED)) { 4731 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP_ERR); 4732 break; 4733 } 4734 4735 /* In a modern packetized environment, an autosense failure 4736 * implies that there's not much else that can be done to 4737 * recover the command. 4738 */ 4739 if (scsi_reply->SCSIState & MPI3_SCSI_STATE_SENSE_VALID) { 4740 mpi3mr_set_ccbstatus(ccb, CAM_AUTOSENSE_FAIL); 4741 break; 4742 } 4743 4744 /* 4745 * Intentionally override the normal SCSI status reporting 4746 * for these two cases. These are likely to happen in a 4747 * multi-initiator environment, and we want to make sure that 4748 * CAM retries these commands rather than fail them. 4749 */ 4750 if ((scsi_reply->SCSIStatus == MPI3_SCSI_STATUS_COMMAND_TERMINATED) || 4751 (scsi_reply->SCSIStatus == MPI3_SCSI_STATUS_TASK_ABORTED)) { 4752 mpi3mr_set_ccbstatus(ccb, CAM_REQ_ABORTED); 4753 break; 4754 } 4755 4756 /* Handle normal status and sense */ 4757 csio->scsi_status = scsi_reply->SCSIStatus; 4758 if (scsi_reply->SCSIStatus == MPI3_SCSI_STATUS_GOOD) 4759 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP); 4760 else 4761 mpi3mr_set_ccbstatus(ccb, CAM_SCSI_STATUS_ERROR); 4762 4763 if (scsi_reply->SCSIState & MPI3_SCSI_STATE_SENSE_VALID) { 4764 int sense_len, returned_sense_len; 4765 4766 returned_sense_len = min(le32toh(scsi_reply->SenseCount), 4767 sizeof(struct scsi_sense_data)); 4768 if (returned_sense_len < csio->sense_len) 4769 csio->sense_resid = csio->sense_len - 4770 returned_sense_len; 4771 else 4772 csio->sense_resid = 0; 4773 4774 sense_len = min(returned_sense_len, 4775 csio->sense_len - csio->sense_resid); 4776 bzero(&csio->sense_data, sizeof(csio->sense_data)); 4777 bcopy(cm->sense, &csio->sense_data, sense_len); 4778 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 4779 } 4780 4781 break; 4782 case MPI3_IOCSTATUS_INVALID_SGL: 4783 mpi3mr_set_ccbstatus(ccb, CAM_UNREC_HBA_ERROR); 4784 break; 4785 case MPI3_IOCSTATUS_EEDP_GUARD_ERROR: 4786 case MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR: 4787 case MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR: 4788 case MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR: 4789 case MPI3_IOCSTATUS_INVALID_FUNCTION: 4790 case MPI3_IOCSTATUS_INTERNAL_ERROR: 4791 case MPI3_IOCSTATUS_INVALID_FIELD: 4792 case MPI3_IOCSTATUS_INVALID_STATE: 4793 case MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR: 4794 case MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 4795 case MPI3_IOCSTATUS_INSUFFICIENT_POWER: 4796 case MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 4797 default: 4798 csio->resid = cm->length; 4799 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP_ERR); 4800 break; 4801 } 4802 4803 out_success: 4804 if (mpi3mr_get_ccbstatus(ccb) != CAM_REQ_CMP) { 4805 ccb->ccb_h.status |= CAM_DEV_QFRZN; 4806 xpt_freeze_devq(ccb->ccb_h.path, /*count*/ 1); 4807 } 4808 4809 mpi3mr_atomic_dec(&cm->targ->outstanding); 4810 mpi3mr_cmd_done(sc, cm); 4811 mpi3mr_dprint(sc, MPI3MR_TRACE, "Completion IO path :" 4812 " cdb[0]: %x targetid: 0x%x SMID: %x ioc_status: 0x%x ioc_loginfo: 0x%x scsi_status: 0x%x " 4813 "scsi_state: 0x%x response_data: 0x%x\n", scsi_cdb[0], target_id, host_tag, 4814 ioc_status, ioc_loginfo, scsi_status, scsi_state, resp_data); 4815 mpi3mr_atomic_dec(&sc->fw_outstanding); 4816 out: 4817 4818 if (sense_buf) 4819 mpi3mr_repost_sense_buf(sc, 4820 scsi_reply->SenseDataBufferAddress); 4821 return; 4822 } 4823 4824 /* 4825 * mpi3mr_complete_io_cmd: ISR routine for IO commands 4826 * @sc: Adapter's soft instance 4827 * @irq_ctx: Driver's internal per IRQ structure 4828 * 4829 * This function processes IO command completions. 4830 */ 4831 int mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc, 4832 struct mpi3mr_irq_context *irq_ctx) 4833 { 4834 struct mpi3mr_op_reply_queue *op_reply_q = irq_ctx->op_reply_q; 4835 U32 exp_phase = op_reply_q->ephase; 4836 U32 reply_ci = op_reply_q->ci; 4837 U32 num_op_replies = 0; 4838 U64 reply_dma = 0; 4839 Mpi3DefaultReplyDescriptor_t *reply_desc; 4840 U16 req_qid = 0; 4841 4842 mtx_lock_spin(&op_reply_q->q_lock); 4843 if (op_reply_q->in_use == false) { 4844 op_reply_q->in_use = true; 4845 mtx_unlock_spin(&op_reply_q->q_lock); 4846 } else { 4847 mtx_unlock_spin(&op_reply_q->q_lock); 4848 return 0; 4849 } 4850 4851 reply_desc = (Mpi3DefaultReplyDescriptor_t *)op_reply_q->q_base + reply_ci; 4852 mpi3mr_dprint(sc, MPI3MR_TRACE, "[QID:%d]:reply_desc: (%pa) reply_ci: %x" 4853 " reply_desc->ReplyFlags: 0x%x\n" 4854 "reply_q_base_phys: %#016jx reply_q_base: (%pa) exp_phase: %x\n", 4855 op_reply_q->qid, reply_desc, reply_ci, reply_desc->ReplyFlags, op_reply_q->q_base_phys, 4856 op_reply_q->q_base, exp_phase); 4857 4858 if (((reply_desc->ReplyFlags & 4859 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) || !op_reply_q->qid) { 4860 mtx_lock_spin(&op_reply_q->q_lock); 4861 op_reply_q->in_use = false; 4862 mtx_unlock_spin(&op_reply_q->q_lock); 4863 return 0; 4864 } 4865 4866 do { 4867 req_qid = reply_desc->RequestQueueID; 4868 sc->op_req_q[req_qid - 1].ci = 4869 reply_desc->RequestQueueCI; 4870 4871 mpi3mr_process_op_reply_desc(sc, reply_desc, &reply_dma); 4872 mpi3mr_atomic_dec(&op_reply_q->pend_ios); 4873 if (reply_dma) 4874 mpi3mr_repost_reply_buf(sc, reply_dma); 4875 num_op_replies++; 4876 if (++reply_ci == op_reply_q->num_replies) { 4877 reply_ci = 0; 4878 exp_phase ^= 1; 4879 } 4880 reply_desc = 4881 (Mpi3DefaultReplyDescriptor_t *)op_reply_q->q_base + reply_ci; 4882 if ((reply_desc->ReplyFlags & 4883 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 4884 break; 4885 } while (1); 4886 4887 4888 mpi3mr_regwrite(sc, MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(op_reply_q->qid), reply_ci); 4889 op_reply_q->ci = reply_ci; 4890 op_reply_q->ephase = exp_phase; 4891 mtx_lock_spin(&op_reply_q->q_lock); 4892 op_reply_q->in_use = false; 4893 mtx_unlock_spin(&op_reply_q->q_lock); 4894 return num_op_replies; 4895 } 4896 4897 /* 4898 * mpi3mr_isr: Primary ISR function 4899 * privdata: Driver's internal per IRQ structure 4900 * 4901 * This is driver's primary ISR function which is being called whenever any admin/IO 4902 * command completion. 4903 */ 4904 void mpi3mr_isr(void *privdata) 4905 { 4906 struct mpi3mr_irq_context *irq_ctx = (struct mpi3mr_irq_context *)privdata; 4907 struct mpi3mr_softc *sc = irq_ctx->sc; 4908 U16 msi_idx; 4909 4910 if (!irq_ctx) 4911 return; 4912 4913 msi_idx = irq_ctx->msix_index; 4914 4915 if (!sc->intr_enabled) 4916 return; 4917 4918 if (!msi_idx) 4919 mpi3mr_complete_admin_cmd(sc); 4920 4921 if (irq_ctx->op_reply_q && irq_ctx->op_reply_q->qid) { 4922 mpi3mr_complete_io_cmd(sc, irq_ctx); 4923 } 4924 } 4925 4926 /* 4927 * mpi3mr_alloc_requests - Allocates host commands 4928 * @sc: Adapter reference 4929 * 4930 * This function allocates controller supported host commands 4931 * 4932 * Return: 0 on success and proper error codes on failure 4933 */ 4934 int 4935 mpi3mr_alloc_requests(struct mpi3mr_softc *sc) 4936 { 4937 struct mpi3mr_cmd *cmd; 4938 int i, j, nsegs, ret; 4939 4940 nsegs = MPI3MR_SG_DEPTH; 4941 ret = bus_dma_tag_create( sc->mpi3mr_parent_dmat, /* parent */ 4942 1, 0, /* algnmnt, boundary */ 4943 BUS_SPACE_MAXADDR, /* lowaddr */ 4944 BUS_SPACE_MAXADDR, /* highaddr */ 4945 NULL, NULL, /* filter, filterarg */ 4946 MAXPHYS,/* maxsize */ 4947 nsegs, /* nsegments */ 4948 MAXPHYS,/* maxsegsize */ 4949 BUS_DMA_ALLOCNOW, /* flags */ 4950 busdma_lock_mutex, /* lockfunc */ 4951 &sc->io_lock, /* lockarg */ 4952 &sc->buffer_dmat); 4953 if (ret) { 4954 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate buffer DMA tag ret: %d\n", ret); 4955 return (ENOMEM); 4956 } 4957 4958 /* 4959 * sc->cmd_list is an array of struct mpi3mr_cmd pointers. 4960 * Allocate the dynamic array first and then allocate individual 4961 * commands. 4962 */ 4963 sc->cmd_list = malloc(sizeof(struct mpi3mr_cmd *) * sc->max_host_ios, 4964 M_MPI3MR, M_NOWAIT | M_ZERO); 4965 4966 if (!sc->cmd_list) { 4967 device_printf(sc->mpi3mr_dev, "Cannot alloc memory for mpt_cmd_list.\n"); 4968 return (ENOMEM); 4969 } 4970 4971 for (i = 0; i < sc->max_host_ios; i++) { 4972 sc->cmd_list[i] = malloc(sizeof(struct mpi3mr_cmd), 4973 M_MPI3MR, M_NOWAIT | M_ZERO); 4974 if (!sc->cmd_list[i]) { 4975 for (j = 0; j < i; j++) 4976 free(sc->cmd_list[j], M_MPI3MR); 4977 free(sc->cmd_list, M_MPI3MR); 4978 sc->cmd_list = NULL; 4979 return (ENOMEM); 4980 } 4981 } 4982 4983 for (i = 1; i < sc->max_host_ios; i++) { 4984 cmd = sc->cmd_list[i]; 4985 cmd->hosttag = i; 4986 cmd->sc = sc; 4987 cmd->state = MPI3MR_CMD_STATE_BUSY; 4988 callout_init_mtx(&cmd->callout, &sc->mpi3mr_mtx, 0); 4989 cmd->ccb = NULL; 4990 TAILQ_INSERT_TAIL(&(sc->cmd_list_head), cmd, next); 4991 if (bus_dmamap_create(sc->buffer_dmat, 0, &cmd->dmamap)) 4992 return ENOMEM; 4993 } 4994 return (0); 4995 } 4996 4997 /* 4998 * mpi3mr_get_command: Get a coomand structure from free command pool 4999 * @sc: Adapter soft instance 5000 * Return: MPT command reference 5001 * 5002 * This function returns an MPT command to the caller. 5003 */ 5004 struct mpi3mr_cmd * 5005 mpi3mr_get_command(struct mpi3mr_softc *sc) 5006 { 5007 struct mpi3mr_cmd *cmd = NULL; 5008 5009 mtx_lock(&sc->cmd_pool_lock); 5010 if (!TAILQ_EMPTY(&sc->cmd_list_head)) { 5011 cmd = TAILQ_FIRST(&sc->cmd_list_head); 5012 TAILQ_REMOVE(&sc->cmd_list_head, cmd, next); 5013 } else { 5014 goto out; 5015 } 5016 5017 mpi3mr_dprint(sc, MPI3MR_TRACE, "Get command SMID: 0x%x\n", cmd->hosttag); 5018 5019 memset((uint8_t *)&cmd->io_request, 0, MPI3MR_AREQ_FRAME_SZ); 5020 cmd->data_dir = 0; 5021 cmd->ccb = NULL; 5022 cmd->targ = NULL; 5023 cmd->state = MPI3MR_CMD_STATE_BUSY; 5024 cmd->data = NULL; 5025 cmd->length = 0; 5026 out: 5027 mtx_unlock(&sc->cmd_pool_lock); 5028 return cmd; 5029 } 5030 5031 /* 5032 * mpi3mr_release_command: Return a cmd to free command pool 5033 * input: Command packet for return to free command pool 5034 * 5035 * This function returns an MPT command to the free command list. 5036 */ 5037 void 5038 mpi3mr_release_command(struct mpi3mr_cmd *cmd) 5039 { 5040 struct mpi3mr_softc *sc = cmd->sc; 5041 5042 mtx_lock(&sc->cmd_pool_lock); 5043 TAILQ_INSERT_HEAD(&(sc->cmd_list_head), cmd, next); 5044 cmd->state = MPI3MR_CMD_STATE_FREE; 5045 cmd->req_qidx = 0; 5046 mpi3mr_dprint(sc, MPI3MR_TRACE, "Release command SMID: 0x%x\n", cmd->hosttag); 5047 mtx_unlock(&sc->cmd_pool_lock); 5048 5049 return; 5050 } 5051 5052 /** 5053 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma 5054 * @sc: Adapter instance reference 5055 * 5056 * Free the DMA memory allocated for IOCTL handling purpose. 5057 * 5058 * Return: None 5059 */ 5060 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_softc *sc) 5061 { 5062 U16 i; 5063 struct dma_memory_desc *mem_desc; 5064 5065 for (i=0; i<MPI3MR_NUM_IOCTL_SGE; i++) { 5066 mem_desc = &sc->ioctl_sge[i]; 5067 if (mem_desc->addr && mem_desc->dma_addr) { 5068 bus_dmamap_unload(mem_desc->tag, mem_desc->dmamap); 5069 bus_dmamem_free(mem_desc->tag, mem_desc->addr, mem_desc->dmamap); 5070 mem_desc->addr = NULL; 5071 if (mem_desc->tag != NULL) 5072 bus_dma_tag_destroy(mem_desc->tag); 5073 } 5074 } 5075 5076 mem_desc = &sc->ioctl_chain_sge; 5077 if (mem_desc->addr && mem_desc->dma_addr) { 5078 bus_dmamap_unload(mem_desc->tag, mem_desc->dmamap); 5079 bus_dmamem_free(mem_desc->tag, mem_desc->addr, mem_desc->dmamap); 5080 mem_desc->addr = NULL; 5081 if (mem_desc->tag != NULL) 5082 bus_dma_tag_destroy(mem_desc->tag); 5083 } 5084 5085 mem_desc = &sc->ioctl_resp_sge; 5086 if (mem_desc->addr && mem_desc->dma_addr) { 5087 bus_dmamap_unload(mem_desc->tag, mem_desc->dmamap); 5088 bus_dmamem_free(mem_desc->tag, mem_desc->addr, mem_desc->dmamap); 5089 mem_desc->addr = NULL; 5090 if (mem_desc->tag != NULL) 5091 bus_dma_tag_destroy(mem_desc->tag); 5092 } 5093 5094 sc->ioctl_sges_allocated = false; 5095 } 5096 5097 /** 5098 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma 5099 * @sc: Adapter instance reference 5100 * 5101 * This function allocates dmaable memory required to handle the 5102 * application issued MPI3 IOCTL requests. 5103 * 5104 * Return: None 5105 */ 5106 void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc) 5107 { 5108 struct dma_memory_desc *mem_desc; 5109 U16 i; 5110 5111 for (i=0; i<MPI3MR_NUM_IOCTL_SGE; i++) { 5112 mem_desc = &sc->ioctl_sge[i]; 5113 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE; 5114 5115 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 5116 4, 0, /* algnmnt, boundary */ 5117 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 5118 BUS_SPACE_MAXADDR, /* highaddr */ 5119 NULL, NULL, /* filter, filterarg */ 5120 mem_desc->size, /* maxsize */ 5121 1, /* nsegments */ 5122 mem_desc->size, /* maxsegsize */ 5123 0, /* flags */ 5124 NULL, NULL, /* lockfunc, lockarg */ 5125 &mem_desc->tag)) { 5126 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 5127 goto out_failed; 5128 } 5129 5130 if (bus_dmamem_alloc(mem_desc->tag, (void **)&mem_desc->addr, 5131 BUS_DMA_NOWAIT, &mem_desc->dmamap)) { 5132 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 5133 goto out_failed; 5134 } 5135 bzero(mem_desc->addr, mem_desc->size); 5136 bus_dmamap_load(mem_desc->tag, mem_desc->dmamap, mem_desc->addr, mem_desc->size, 5137 mpi3mr_memaddr_cb, &mem_desc->dma_addr, 0); 5138 5139 if (!mem_desc->addr) 5140 goto out_failed; 5141 } 5142 5143 mem_desc = &sc->ioctl_chain_sge; 5144 mem_desc->size = MPI3MR_4K_PGSZ; 5145 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 5146 4, 0, /* algnmnt, boundary */ 5147 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 5148 BUS_SPACE_MAXADDR, /* highaddr */ 5149 NULL, NULL, /* filter, filterarg */ 5150 mem_desc->size, /* maxsize */ 5151 1, /* nsegments */ 5152 mem_desc->size, /* maxsegsize */ 5153 0, /* flags */ 5154 NULL, NULL, /* lockfunc, lockarg */ 5155 &mem_desc->tag)) { 5156 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 5157 goto out_failed; 5158 } 5159 5160 if (bus_dmamem_alloc(mem_desc->tag, (void **)&mem_desc->addr, 5161 BUS_DMA_NOWAIT, &mem_desc->dmamap)) { 5162 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 5163 goto out_failed; 5164 } 5165 bzero(mem_desc->addr, mem_desc->size); 5166 bus_dmamap_load(mem_desc->tag, mem_desc->dmamap, mem_desc->addr, mem_desc->size, 5167 mpi3mr_memaddr_cb, &mem_desc->dma_addr, 0); 5168 5169 if (!mem_desc->addr) 5170 goto out_failed; 5171 5172 mem_desc = &sc->ioctl_resp_sge; 5173 mem_desc->size = MPI3MR_4K_PGSZ; 5174 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 5175 4, 0, /* algnmnt, boundary */ 5176 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 5177 BUS_SPACE_MAXADDR, /* highaddr */ 5178 NULL, NULL, /* filter, filterarg */ 5179 mem_desc->size, /* maxsize */ 5180 1, /* nsegments */ 5181 mem_desc->size, /* maxsegsize */ 5182 0, /* flags */ 5183 NULL, NULL, /* lockfunc, lockarg */ 5184 &mem_desc->tag)) { 5185 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 5186 goto out_failed; 5187 } 5188 5189 if (bus_dmamem_alloc(mem_desc->tag, (void **)&mem_desc->addr, 5190 BUS_DMA_NOWAIT, &mem_desc->dmamap)) { 5191 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 5192 goto out_failed; 5193 } 5194 bzero(mem_desc->addr, mem_desc->size); 5195 bus_dmamap_load(mem_desc->tag, mem_desc->dmamap, mem_desc->addr, mem_desc->size, 5196 mpi3mr_memaddr_cb, &mem_desc->dma_addr, 0); 5197 5198 if (!mem_desc->addr) 5199 goto out_failed; 5200 5201 sc->ioctl_sges_allocated = true; 5202 5203 return; 5204 out_failed: 5205 printf("cannot allocate DMA memory for the mpt commands" 5206 " from the applications, application interface for MPT command is disabled\n"); 5207 mpi3mr_free_ioctl_dma_memory(sc); 5208 } 5209 5210 void 5211 mpi3mr_destory_mtx(struct mpi3mr_softc *sc) 5212 { 5213 int i; 5214 struct mpi3mr_op_req_queue *op_req_q; 5215 struct mpi3mr_op_reply_queue *op_reply_q; 5216 5217 if (sc->admin_reply) { 5218 if (mtx_initialized(&sc->admin_reply_lock)) 5219 mtx_destroy(&sc->admin_reply_lock); 5220 } 5221 5222 if (sc->op_reply_q) { 5223 for(i = 0; i < sc->num_queues; i++) { 5224 op_reply_q = sc->op_reply_q + i; 5225 if (mtx_initialized(&op_reply_q->q_lock)) 5226 mtx_destroy(&op_reply_q->q_lock); 5227 } 5228 } 5229 5230 if (sc->op_req_q) { 5231 for(i = 0; i < sc->num_queues; i++) { 5232 op_req_q = sc->op_req_q + i; 5233 if (mtx_initialized(&op_req_q->q_lock)) 5234 mtx_destroy(&op_req_q->q_lock); 5235 } 5236 } 5237 5238 if (mtx_initialized(&sc->init_cmds.completion.lock)) 5239 mtx_destroy(&sc->init_cmds.completion.lock); 5240 5241 if (mtx_initialized(&sc->ioctl_cmds.completion.lock)) 5242 mtx_destroy(&sc->ioctl_cmds.completion.lock); 5243 5244 if (mtx_initialized(&sc->host_tm_cmds.completion.lock)) 5245 mtx_destroy(&sc->host_tm_cmds.completion.lock); 5246 5247 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 5248 if (mtx_initialized(&sc->dev_rmhs_cmds[i].completion.lock)) 5249 mtx_destroy(&sc->dev_rmhs_cmds[i].completion.lock); 5250 } 5251 5252 if (mtx_initialized(&sc->reset_mutex)) 5253 mtx_destroy(&sc->reset_mutex); 5254 5255 if (mtx_initialized(&sc->target_lock)) 5256 mtx_destroy(&sc->target_lock); 5257 5258 if (mtx_initialized(&sc->fwevt_lock)) 5259 mtx_destroy(&sc->fwevt_lock); 5260 5261 if (mtx_initialized(&sc->cmd_pool_lock)) 5262 mtx_destroy(&sc->cmd_pool_lock); 5263 5264 if (mtx_initialized(&sc->reply_free_q_lock)) 5265 mtx_destroy(&sc->reply_free_q_lock); 5266 5267 if (mtx_initialized(&sc->sense_buf_q_lock)) 5268 mtx_destroy(&sc->sense_buf_q_lock); 5269 5270 if (mtx_initialized(&sc->chain_buf_lock)) 5271 mtx_destroy(&sc->chain_buf_lock); 5272 5273 if (mtx_initialized(&sc->admin_req_lock)) 5274 mtx_destroy(&sc->admin_req_lock); 5275 5276 if (mtx_initialized(&sc->mpi3mr_mtx)) 5277 mtx_destroy(&sc->mpi3mr_mtx); 5278 } 5279 5280 /** 5281 * mpi3mr_free_mem - Freeup adapter level data structures 5282 * @sc: Adapter reference 5283 * 5284 * Return: Nothing. 5285 */ 5286 void 5287 mpi3mr_free_mem(struct mpi3mr_softc *sc) 5288 { 5289 int i; 5290 struct mpi3mr_op_req_queue *op_req_q; 5291 struct mpi3mr_op_reply_queue *op_reply_q; 5292 struct mpi3mr_irq_context *irq_ctx; 5293 5294 if (sc->cmd_list) { 5295 for (i = 0; i < sc->max_host_ios; i++) { 5296 free(sc->cmd_list[i], M_MPI3MR); 5297 } 5298 free(sc->cmd_list, M_MPI3MR); 5299 sc->cmd_list = NULL; 5300 } 5301 5302 if (sc->pel_seq_number && sc->pel_seq_number_dma) { 5303 bus_dmamap_unload(sc->pel_seq_num_dmatag, sc->pel_seq_num_dmamap); 5304 bus_dmamem_free(sc->pel_seq_num_dmatag, sc->pel_seq_number, sc->pel_seq_num_dmamap); 5305 sc->pel_seq_number = NULL; 5306 if (sc->pel_seq_num_dmatag != NULL) 5307 bus_dma_tag_destroy(sc->pel_seq_num_dmatag); 5308 } 5309 5310 if (sc->throttle_groups) { 5311 free(sc->throttle_groups, M_MPI3MR); 5312 sc->throttle_groups = NULL; 5313 } 5314 5315 /* Free up operational queues*/ 5316 if (sc->op_req_q) { 5317 for (i = 0; i < sc->num_queues; i++) { 5318 op_req_q = sc->op_req_q + i; 5319 if (op_req_q->q_base && op_req_q->q_base_phys) { 5320 bus_dmamap_unload(op_req_q->q_base_tag, op_req_q->q_base_dmamap); 5321 bus_dmamem_free(op_req_q->q_base_tag, op_req_q->q_base, op_req_q->q_base_dmamap); 5322 op_req_q->q_base = NULL; 5323 if (op_req_q->q_base_tag != NULL) 5324 bus_dma_tag_destroy(op_req_q->q_base_tag); 5325 } 5326 } 5327 free(sc->op_req_q, M_MPI3MR); 5328 sc->op_req_q = NULL; 5329 } 5330 5331 if (sc->op_reply_q) { 5332 for (i = 0; i < sc->num_queues; i++) { 5333 op_reply_q = sc->op_reply_q + i; 5334 if (op_reply_q->q_base && op_reply_q->q_base_phys) { 5335 bus_dmamap_unload(op_reply_q->q_base_tag, op_reply_q->q_base_dmamap); 5336 bus_dmamem_free(op_reply_q->q_base_tag, op_reply_q->q_base, op_reply_q->q_base_dmamap); 5337 op_reply_q->q_base = NULL; 5338 if (op_reply_q->q_base_tag != NULL) 5339 bus_dma_tag_destroy(op_reply_q->q_base_tag); 5340 } 5341 } 5342 free(sc->op_reply_q, M_MPI3MR); 5343 sc->op_reply_q = NULL; 5344 } 5345 5346 /* Free up chain buffers*/ 5347 if (sc->chain_sgl_list) { 5348 for (i = 0; i < sc->chain_buf_count; i++) { 5349 if (sc->chain_sgl_list[i].buf && sc->chain_sgl_list[i].buf_phys) { 5350 bus_dmamap_unload(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf_dmamap); 5351 bus_dmamem_free(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf, 5352 sc->chain_sgl_list[i].buf_dmamap); 5353 sc->chain_sgl_list[i].buf = NULL; 5354 } 5355 } 5356 if (sc->chain_sgl_list_tag != NULL) 5357 bus_dma_tag_destroy(sc->chain_sgl_list_tag); 5358 free(sc->chain_sgl_list, M_MPI3MR); 5359 sc->chain_sgl_list = NULL; 5360 } 5361 5362 if (sc->chain_bitmap) { 5363 free(sc->chain_bitmap, M_MPI3MR); 5364 sc->chain_bitmap = NULL; 5365 } 5366 5367 for (i = 0; i < sc->msix_count; i++) { 5368 irq_ctx = sc->irq_ctx + i; 5369 if (irq_ctx) 5370 irq_ctx->op_reply_q = NULL; 5371 } 5372 5373 /* Free reply_buf_tag */ 5374 if (sc->reply_buf && sc->reply_buf_phys) { 5375 bus_dmamap_unload(sc->reply_buf_tag, sc->reply_buf_dmamap); 5376 bus_dmamem_free(sc->reply_buf_tag, sc->reply_buf, 5377 sc->reply_buf_dmamap); 5378 sc->reply_buf = NULL; 5379 if (sc->reply_buf_tag != NULL) 5380 bus_dma_tag_destroy(sc->reply_buf_tag); 5381 } 5382 5383 /* Free reply_free_q_tag */ 5384 if (sc->reply_free_q && sc->reply_free_q_phys) { 5385 bus_dmamap_unload(sc->reply_free_q_tag, sc->reply_free_q_dmamap); 5386 bus_dmamem_free(sc->reply_free_q_tag, sc->reply_free_q, 5387 sc->reply_free_q_dmamap); 5388 sc->reply_free_q = NULL; 5389 if (sc->reply_free_q_tag != NULL) 5390 bus_dma_tag_destroy(sc->reply_free_q_tag); 5391 } 5392 5393 /* Free sense_buf_tag */ 5394 if (sc->sense_buf && sc->sense_buf_phys) { 5395 bus_dmamap_unload(sc->sense_buf_tag, sc->sense_buf_dmamap); 5396 bus_dmamem_free(sc->sense_buf_tag, sc->sense_buf, 5397 sc->sense_buf_dmamap); 5398 sc->sense_buf = NULL; 5399 if (sc->sense_buf_tag != NULL) 5400 bus_dma_tag_destroy(sc->sense_buf_tag); 5401 } 5402 5403 /* Free sense_buf_q_tag */ 5404 if (sc->sense_buf_q && sc->sense_buf_q_phys) { 5405 bus_dmamap_unload(sc->sense_buf_q_tag, sc->sense_buf_q_dmamap); 5406 bus_dmamem_free(sc->sense_buf_q_tag, sc->sense_buf_q, 5407 sc->sense_buf_q_dmamap); 5408 sc->sense_buf_q = NULL; 5409 if (sc->sense_buf_q_tag != NULL) 5410 bus_dma_tag_destroy(sc->sense_buf_q_tag); 5411 } 5412 5413 /* Free up internal(non-IO) commands*/ 5414 if (sc->init_cmds.reply) { 5415 free(sc->init_cmds.reply, M_MPI3MR); 5416 sc->init_cmds.reply = NULL; 5417 } 5418 5419 if (sc->ioctl_cmds.reply) { 5420 free(sc->ioctl_cmds.reply, M_MPI3MR); 5421 sc->ioctl_cmds.reply = NULL; 5422 } 5423 5424 if (sc->pel_cmds.reply) { 5425 free(sc->pel_cmds.reply, M_MPI3MR); 5426 sc->pel_cmds.reply = NULL; 5427 } 5428 5429 if (sc->pel_abort_cmd.reply) { 5430 free(sc->pel_abort_cmd.reply, M_MPI3MR); 5431 sc->pel_abort_cmd.reply = NULL; 5432 } 5433 5434 if (sc->host_tm_cmds.reply) { 5435 free(sc->host_tm_cmds.reply, M_MPI3MR); 5436 sc->host_tm_cmds.reply = NULL; 5437 } 5438 5439 if (sc->log_data_buffer) { 5440 free(sc->log_data_buffer, M_MPI3MR); 5441 sc->log_data_buffer = NULL; 5442 } 5443 5444 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 5445 if (sc->dev_rmhs_cmds[i].reply) { 5446 free(sc->dev_rmhs_cmds[i].reply, M_MPI3MR); 5447 sc->dev_rmhs_cmds[i].reply = NULL; 5448 } 5449 } 5450 5451 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 5452 if (sc->evtack_cmds[i].reply) { 5453 free(sc->evtack_cmds[i].reply, M_MPI3MR); 5454 sc->evtack_cmds[i].reply = NULL; 5455 } 5456 } 5457 5458 if (sc->removepend_bitmap) { 5459 free(sc->removepend_bitmap, M_MPI3MR); 5460 sc->removepend_bitmap = NULL; 5461 } 5462 5463 if (sc->devrem_bitmap) { 5464 free(sc->devrem_bitmap, M_MPI3MR); 5465 sc->devrem_bitmap = NULL; 5466 } 5467 5468 if (sc->evtack_cmds_bitmap) { 5469 free(sc->evtack_cmds_bitmap, M_MPI3MR); 5470 sc->evtack_cmds_bitmap = NULL; 5471 } 5472 5473 /* Free Admin reply*/ 5474 if (sc->admin_reply && sc->admin_reply_phys) { 5475 bus_dmamap_unload(sc->admin_reply_tag, sc->admin_reply_dmamap); 5476 bus_dmamem_free(sc->admin_reply_tag, sc->admin_reply, 5477 sc->admin_reply_dmamap); 5478 sc->admin_reply = NULL; 5479 if (sc->admin_reply_tag != NULL) 5480 bus_dma_tag_destroy(sc->admin_reply_tag); 5481 } 5482 5483 /* Free Admin request*/ 5484 if (sc->admin_req && sc->admin_req_phys) { 5485 bus_dmamap_unload(sc->admin_req_tag, sc->admin_req_dmamap); 5486 bus_dmamem_free(sc->admin_req_tag, sc->admin_req, 5487 sc->admin_req_dmamap); 5488 sc->admin_req = NULL; 5489 if (sc->admin_req_tag != NULL) 5490 bus_dma_tag_destroy(sc->admin_req_tag); 5491 } 5492 mpi3mr_free_ioctl_dma_memory(sc); 5493 5494 } 5495 5496 /** 5497 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command 5498 * @sc: Adapter instance reference 5499 * @cmdptr: Internal command tracker 5500 * 5501 * Complete an internal driver commands with state indicating it 5502 * is completed due to reset. 5503 * 5504 * Return: Nothing. 5505 */ 5506 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_softc *sc, 5507 struct mpi3mr_drvr_cmd *cmdptr) 5508 { 5509 if (cmdptr->state & MPI3MR_CMD_PENDING) { 5510 cmdptr->state |= MPI3MR_CMD_RESET; 5511 cmdptr->state &= ~MPI3MR_CMD_PENDING; 5512 if (cmdptr->is_waiting) { 5513 complete(&cmdptr->completion); 5514 cmdptr->is_waiting = 0; 5515 } else if (cmdptr->callback) 5516 cmdptr->callback(sc, cmdptr); 5517 } 5518 } 5519 5520 /** 5521 * mpi3mr_flush_drv_cmds - Flush internal driver commands 5522 * @sc: Adapter instance reference 5523 * 5524 * Flush all internal driver commands post reset 5525 * 5526 * Return: Nothing. 5527 */ 5528 static void mpi3mr_flush_drv_cmds(struct mpi3mr_softc *sc) 5529 { 5530 int i = 0; 5531 struct mpi3mr_drvr_cmd *cmdptr; 5532 5533 cmdptr = &sc->init_cmds; 5534 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5535 5536 cmdptr = &sc->ioctl_cmds; 5537 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5538 5539 cmdptr = &sc->host_tm_cmds; 5540 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5541 5542 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 5543 cmdptr = &sc->dev_rmhs_cmds[i]; 5544 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5545 } 5546 5547 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 5548 cmdptr = &sc->evtack_cmds[i]; 5549 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5550 } 5551 5552 cmdptr = &sc->pel_cmds; 5553 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5554 5555 cmdptr = &sc->pel_abort_cmd; 5556 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5557 } 5558 5559 5560 /** 5561 * mpi3mr_memset_buffers - memset memory for a controller 5562 * @sc: Adapter instance reference 5563 * 5564 * clear all the memory allocated for a controller, typically 5565 * called post reset to reuse the memory allocated during the 5566 * controller init. 5567 * 5568 * Return: Nothing. 5569 */ 5570 static void mpi3mr_memset_buffers(struct mpi3mr_softc *sc) 5571 { 5572 U16 i; 5573 struct mpi3mr_throttle_group_info *tg; 5574 5575 memset(sc->admin_req, 0, sc->admin_req_q_sz); 5576 memset(sc->admin_reply, 0, sc->admin_reply_q_sz); 5577 5578 memset(sc->init_cmds.reply, 0, sc->reply_sz); 5579 memset(sc->ioctl_cmds.reply, 0, sc->reply_sz); 5580 memset(sc->host_tm_cmds.reply, 0, sc->reply_sz); 5581 memset(sc->pel_cmds.reply, 0, sc->reply_sz); 5582 memset(sc->pel_abort_cmd.reply, 0, sc->reply_sz); 5583 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) 5584 memset(sc->dev_rmhs_cmds[i].reply, 0, sc->reply_sz); 5585 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) 5586 memset(sc->evtack_cmds[i].reply, 0, sc->reply_sz); 5587 memset(sc->removepend_bitmap, 0, sc->dev_handle_bitmap_sz); 5588 memset(sc->devrem_bitmap, 0, sc->devrem_bitmap_sz); 5589 memset(sc->evtack_cmds_bitmap, 0, sc->evtack_cmds_bitmap_sz); 5590 5591 for (i = 0; i < sc->num_queues; i++) { 5592 sc->op_reply_q[i].qid = 0; 5593 sc->op_reply_q[i].ci = 0; 5594 sc->op_reply_q[i].num_replies = 0; 5595 sc->op_reply_q[i].ephase = 0; 5596 mpi3mr_atomic_set(&sc->op_reply_q[i].pend_ios, 0); 5597 memset(sc->op_reply_q[i].q_base, 0, sc->op_reply_q[i].qsz); 5598 5599 sc->op_req_q[i].ci = 0; 5600 sc->op_req_q[i].pi = 0; 5601 sc->op_req_q[i].num_reqs = 0; 5602 sc->op_req_q[i].qid = 0; 5603 sc->op_req_q[i].reply_qid = 0; 5604 memset(sc->op_req_q[i].q_base, 0, sc->op_req_q[i].qsz); 5605 } 5606 5607 mpi3mr_atomic_set(&sc->pend_large_data_sz, 0); 5608 if (sc->throttle_groups) { 5609 tg = sc->throttle_groups; 5610 for (i = 0; i < sc->num_io_throttle_group; i++, tg++) { 5611 tg->id = 0; 5612 tg->fw_qd = 0; 5613 tg->modified_qd = 0; 5614 tg->io_divert= 0; 5615 tg->high = 0; 5616 tg->low = 0; 5617 mpi3mr_atomic_set(&tg->pend_large_data_sz, 0); 5618 } 5619 } 5620 } 5621 5622 /** 5623 * mpi3mr_invalidate_devhandles -Invalidate device handles 5624 * @sc: Adapter instance reference 5625 * 5626 * Invalidate the device handles in the target device structures 5627 * . Called post reset prior to reinitializing the controller. 5628 * 5629 * Return: Nothing. 5630 */ 5631 static void mpi3mr_invalidate_devhandles(struct mpi3mr_softc *sc) 5632 { 5633 struct mpi3mr_target *target = NULL; 5634 5635 mtx_lock_spin(&sc->target_lock); 5636 TAILQ_FOREACH(target, &sc->cam_sc->tgt_list, tgt_next) { 5637 if (target) { 5638 target->dev_handle = MPI3MR_INVALID_DEV_HANDLE; 5639 target->io_throttle_enabled = 0; 5640 target->io_divert = 0; 5641 target->throttle_group = NULL; 5642 } 5643 } 5644 mtx_unlock_spin(&sc->target_lock); 5645 } 5646 5647 /** 5648 * mpi3mr_rfresh_tgtdevs - Refresh target device exposure 5649 * @sc: Adapter instance reference 5650 * 5651 * This is executed post controller reset to identify any 5652 * missing devices during reset and remove from the upper layers 5653 * or expose any newly detected device to the upper layers. 5654 * 5655 * Return: Nothing. 5656 */ 5657 5658 static void mpi3mr_rfresh_tgtdevs(struct mpi3mr_softc *sc) 5659 { 5660 struct mpi3mr_target *target = NULL; 5661 struct mpi3mr_target *target_temp = NULL; 5662 5663 TAILQ_FOREACH_SAFE(target, &sc->cam_sc->tgt_list, tgt_next, target_temp) { 5664 if (target->dev_handle == MPI3MR_INVALID_DEV_HANDLE) { 5665 if (target->exposed_to_os) 5666 mpi3mr_remove_device_from_os(sc, target->dev_handle); 5667 mpi3mr_remove_device_from_list(sc, target, true); 5668 } 5669 } 5670 5671 TAILQ_FOREACH(target, &sc->cam_sc->tgt_list, tgt_next) { 5672 if ((target->dev_handle != MPI3MR_INVALID_DEV_HANDLE) && 5673 !target->is_hidden && !target->exposed_to_os) { 5674 mpi3mr_add_device(sc, target->per_id); 5675 } 5676 } 5677 5678 } 5679 5680 static void mpi3mr_flush_io(struct mpi3mr_softc *sc) 5681 { 5682 int i; 5683 struct mpi3mr_cmd *cmd = NULL; 5684 union ccb *ccb = NULL; 5685 5686 for (i = 0; i < sc->max_host_ios; i++) { 5687 cmd = sc->cmd_list[i]; 5688 5689 if (cmd && cmd->ccb) { 5690 if (cmd->callout_owner) { 5691 ccb = (union ccb *)(cmd->ccb); 5692 ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 5693 mpi3mr_cmd_done(sc, cmd); 5694 } else { 5695 cmd->ccb = NULL; 5696 mpi3mr_release_command(cmd); 5697 } 5698 } 5699 } 5700 } 5701 /** 5702 * mpi3mr_clear_reset_history - Clear reset history 5703 * @sc: Adapter instance reference 5704 * 5705 * Write the reset history bit in IOC Status to clear the bit, 5706 * if it is already set. 5707 * 5708 * Return: Nothing. 5709 */ 5710 static inline void mpi3mr_clear_reset_history(struct mpi3mr_softc *sc) 5711 { 5712 U32 ioc_status; 5713 5714 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 5715 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 5716 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_STATUS_OFFSET, ioc_status); 5717 } 5718 5719 /** 5720 * mpi3mr_set_diagsave - Set diag save bit for snapdump 5721 * @sc: Adapter reference 5722 * 5723 * Set diag save bit in IOC configuration register to enable 5724 * snapdump. 5725 * 5726 * Return: Nothing. 5727 */ 5728 static inline void mpi3mr_set_diagsave(struct mpi3mr_softc *sc) 5729 { 5730 U32 ioc_config; 5731 5732 ioc_config = 5733 mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 5734 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 5735 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 5736 } 5737 5738 /** 5739 * mpi3mr_issue_reset - Issue reset to the controller 5740 * @sc: Adapter reference 5741 * @reset_type: Reset type 5742 * @reset_reason: Reset reason code 5743 * 5744 * Unlock the host diagnostic registers and write the specific 5745 * reset type to that, wait for reset acknowledgement from the 5746 * controller, if the reset is not successful retry for the 5747 * predefined number of times. 5748 * 5749 * Return: 0 on success, non-zero on failure. 5750 */ 5751 static int mpi3mr_issue_reset(struct mpi3mr_softc *sc, U16 reset_type, 5752 U32 reset_reason) 5753 { 5754 int retval = -1; 5755 U8 unlock_retry_count = 0; 5756 U32 host_diagnostic, ioc_status, ioc_config; 5757 U32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 5758 5759 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && 5760 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)) 5761 return retval; 5762 if (sc->unrecoverable) 5763 return retval; 5764 5765 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) { 5766 retval = 0; 5767 return retval; 5768 } 5769 5770 mpi3mr_dprint(sc, MPI3MR_INFO, "%s reset due to %s(0x%x)\n", 5771 mpi3mr_reset_type_name(reset_type), 5772 mpi3mr_reset_rc_name(reset_reason), reset_reason); 5773 5774 mpi3mr_clear_reset_history(sc); 5775 do { 5776 mpi3mr_dprint(sc, MPI3MR_INFO, 5777 "Write magic sequence to unlock host diag register (retry=%d)\n", 5778 ++unlock_retry_count); 5779 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) { 5780 mpi3mr_dprint(sc, MPI3MR_ERROR, 5781 "%s reset failed! due to host diag register unlock failure" 5782 "host_diagnostic(0x%08x)\n", mpi3mr_reset_type_name(reset_type), 5783 host_diagnostic); 5784 sc->unrecoverable = 1; 5785 return retval; 5786 } 5787 5788 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5789 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH); 5790 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5791 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST); 5792 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5793 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND); 5794 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5795 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD); 5796 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5797 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH); 5798 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5799 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH); 5800 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5801 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH); 5802 5803 DELAY(1000); /* delay in usec */ 5804 host_diagnostic = mpi3mr_regread(sc, MPI3_SYSIF_HOST_DIAG_OFFSET); 5805 mpi3mr_dprint(sc, MPI3MR_INFO, 5806 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n", 5807 unlock_retry_count, host_diagnostic); 5808 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); 5809 5810 mpi3mr_regwrite(sc, MPI3_SYSIF_SCRATCHPAD0_OFFSET, reset_reason); 5811 mpi3mr_regwrite(sc, MPI3_SYSIF_HOST_DIAG_OFFSET, host_diagnostic | reset_type); 5812 5813 if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) { 5814 do { 5815 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 5816 if (ioc_status & 5817 MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 5818 ioc_config = 5819 mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 5820 if (mpi3mr_soft_reset_success(ioc_status, 5821 ioc_config)) { 5822 mpi3mr_clear_reset_history(sc); 5823 retval = 0; 5824 break; 5825 } 5826 } 5827 DELAY(100 * 1000); 5828 } while (--timeout); 5829 } else if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT) { 5830 do { 5831 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 5832 if (mpi3mr_diagfault_success(sc, ioc_status)) { 5833 retval = 0; 5834 break; 5835 } 5836 DELAY(100 * 1000); 5837 } while (--timeout); 5838 } 5839 5840 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5841 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND); 5842 5843 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 5844 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 5845 5846 mpi3mr_dprint(sc, MPI3MR_INFO, 5847 "IOC Status/Config after %s reset is (0x%x)/(0x%x)\n", 5848 !retval ? "successful":"failed", ioc_status, 5849 ioc_config); 5850 5851 if (retval) 5852 sc->unrecoverable = 1; 5853 5854 return retval; 5855 } 5856 5857 inline void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc) 5858 { 5859 /* 5860 * Block the taskqueue before draining. This means any new tasks won't 5861 * be queued to a worker thread. But it doesn't stop the current workers 5862 * that are running. taskqueue_drain waits for those correctly in the 5863 * case of thread backed taskqueues. 5864 */ 5865 taskqueue_block(sc->cam_sc->ev_tq); 5866 taskqueue_drain(sc->cam_sc->ev_tq, &sc->cam_sc->ev_task); 5867 } 5868 5869 /** 5870 * mpi3mr_soft_reset_handler - Reset the controller 5871 * @sc: Adapter instance reference 5872 * @reset_reason: Reset reason code 5873 * @snapdump: snapdump enable/disbale bit 5874 * 5875 * This is an handler for recovering controller by issuing soft 5876 * reset or diag fault reset. This is a blocking function and 5877 * when one reset is executed if any other resets they will be 5878 * blocked. All IOCTLs/IO will be blocked during the reset. If 5879 * controller reset is successful then the controller will be 5880 * reinitalized, otherwise the controller will be marked as not 5881 * recoverable 5882 * 5883 * Return: 0 on success, non-zero on failure. 5884 */ 5885 int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, 5886 U32 reset_reason, bool snapdump) 5887 { 5888 int retval = 0, i = 0; 5889 enum mpi3mr_iocstate ioc_state; 5890 5891 mpi3mr_dprint(sc, MPI3MR_INFO, "soft reset invoked: reason code: %s\n", 5892 mpi3mr_reset_rc_name(reset_reason)); 5893 5894 if ((reset_reason == MPI3MR_RESET_FROM_IOCTL) && 5895 (sc->reset.ioctl_reset_snapdump != true)) 5896 snapdump = false; 5897 5898 mpi3mr_dprint(sc, MPI3MR_INFO, 5899 "soft_reset_handler: wait if diag save is in progress\n"); 5900 while (sc->diagsave_timeout) 5901 DELAY(1000 * 1000); 5902 5903 ioc_state = mpi3mr_get_iocstate(sc); 5904 if (ioc_state == MRIOC_STATE_UNRECOVERABLE) { 5905 mpi3mr_dprint(sc, MPI3MR_ERROR, "controller is in unrecoverable state, exit\n"); 5906 sc->reset.type = MPI3MR_NO_RESET; 5907 sc->reset.reason = MPI3MR_DEFAULT_RESET_REASON; 5908 sc->reset.status = -1; 5909 sc->reset.ioctl_reset_snapdump = false; 5910 return -1; 5911 } 5912 5913 if (sc->reset_in_progress) { 5914 mpi3mr_dprint(sc, MPI3MR_INFO, "reset is already in progress, exit\n"); 5915 return -1; 5916 } 5917 5918 /* Pause IOs, drain and block the event taskqueue */ 5919 xpt_freeze_simq(sc->cam_sc->sim, 1); 5920 5921 mpi3mr_cleanup_event_taskq(sc); 5922 5923 sc->reset_in_progress = 1; 5924 sc->block_ioctls = 1; 5925 5926 while (mpi3mr_atomic_read(&sc->pend_ioctls) && (i < PEND_IOCTLS_COMP_WAIT_TIME)) { 5927 ioc_state = mpi3mr_get_iocstate(sc); 5928 if (ioc_state == MRIOC_STATE_FAULT) 5929 break; 5930 i++; 5931 if (!(i % 5)) { 5932 mpi3mr_dprint(sc, MPI3MR_INFO, 5933 "[%2ds]waiting for IOCTL to be finished from %s\n", i, __func__); 5934 } 5935 DELAY(1000 * 1000); 5936 } 5937 5938 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) && 5939 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) && 5940 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) { 5941 5942 mpi3mr_dprint(sc, MPI3MR_INFO, "Turn off events prior to reset\n"); 5943 5944 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 5945 sc->event_masks[i] = -1; 5946 mpi3mr_issue_event_notification(sc); 5947 } 5948 5949 mpi3mr_disable_interrupts(sc); 5950 5951 if (snapdump) 5952 mpi3mr_trigger_snapdump(sc, reset_reason); 5953 5954 retval = mpi3mr_issue_reset(sc, 5955 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason); 5956 if (retval) { 5957 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to issue soft reset to the ioc\n"); 5958 goto out; 5959 } 5960 5961 mpi3mr_flush_drv_cmds(sc); 5962 mpi3mr_flush_io(sc); 5963 mpi3mr_invalidate_devhandles(sc); 5964 mpi3mr_memset_buffers(sc); 5965 5966 if (sc->prepare_for_reset) { 5967 sc->prepare_for_reset = 0; 5968 sc->prepare_for_reset_timeout_counter = 0; 5969 } 5970 5971 retval = mpi3mr_initialize_ioc(sc, MPI3MR_INIT_TYPE_RESET); 5972 if (retval) { 5973 mpi3mr_dprint(sc, MPI3MR_ERROR, "reinit after soft reset failed: reason %d\n", 5974 reset_reason); 5975 goto out; 5976 } 5977 5978 DELAY((1000 * 1000) * 10); 5979 out: 5980 if (!retval) { 5981 sc->diagsave_timeout = 0; 5982 sc->reset_in_progress = 0; 5983 mpi3mr_rfresh_tgtdevs(sc); 5984 sc->ts_update_counter = 0; 5985 sc->block_ioctls = 0; 5986 sc->pel_abort_requested = 0; 5987 if (sc->pel_wait_pend) { 5988 sc->pel_cmds.retry_count = 0; 5989 mpi3mr_issue_pel_wait(sc, &sc->pel_cmds); 5990 mpi3mr_app_send_aen(sc); 5991 } 5992 } else { 5993 mpi3mr_issue_reset(sc, 5994 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 5995 sc->unrecoverable = 1; 5996 sc->reset_in_progress = 0; 5997 } 5998 5999 mpi3mr_dprint(sc, MPI3MR_INFO, "Soft Reset: %s\n", ((retval == 0) ? "SUCCESS" : "FAILED")); 6000 6001 taskqueue_unblock(sc->cam_sc->ev_tq); 6002 xpt_release_simq(sc->cam_sc->sim, 1); 6003 6004 sc->reset.type = MPI3MR_NO_RESET; 6005 sc->reset.reason = MPI3MR_DEFAULT_RESET_REASON; 6006 sc->reset.status = retval; 6007 sc->reset.ioctl_reset_snapdump = false; 6008 6009 return retval; 6010 } 6011 6012 /** 6013 * mpi3mr_issue_ioc_shutdown - shutdown controller 6014 * @sc: Adapter instance reference 6015 * 6016 * Send shutodwn notification to the controller and wait for the 6017 * shutdown_timeout for it to be completed. 6018 * 6019 * Return: Nothing. 6020 */ 6021 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_softc *sc) 6022 { 6023 U32 ioc_config, ioc_status; 6024 U8 retval = 1, retry = 0; 6025 U32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 6026 6027 mpi3mr_dprint(sc, MPI3MR_INFO, "sending shutdown notification\n"); 6028 if (sc->unrecoverable) { 6029 mpi3mr_dprint(sc, MPI3MR_ERROR, 6030 "controller is unrecoverable, shutdown not issued\n"); 6031 return; 6032 } 6033 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 6034 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 6035 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 6036 mpi3mr_dprint(sc, MPI3MR_ERROR, "shutdown already in progress\n"); 6037 return; 6038 } 6039 6040 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 6041 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 6042 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 6043 6044 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 6045 6046 if (sc->facts.shutdown_timeout) 6047 timeout = sc->facts.shutdown_timeout * 10; 6048 6049 do { 6050 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 6051 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 6052 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 6053 retval = 0; 6054 break; 6055 } 6056 6057 if (sc->unrecoverable) 6058 break; 6059 6060 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 6061 mpi3mr_print_fault_info(sc); 6062 6063 if (retry >= MPI3MR_MAX_SHUTDOWN_RETRY_COUNT) 6064 break; 6065 6066 if (mpi3mr_issue_reset(sc, 6067 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 6068 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 6069 break; 6070 6071 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 6072 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 6073 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 6074 6075 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 6076 6077 if (sc->facts.shutdown_timeout) 6078 timeout = sc->facts.shutdown_timeout * 10; 6079 6080 retry++; 6081 } 6082 6083 DELAY(100 * 1000); 6084 6085 } while (--timeout); 6086 6087 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 6088 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 6089 6090 if (retval) { 6091 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 6092 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 6093 mpi3mr_dprint(sc, MPI3MR_ERROR, 6094 "shutdown still in progress after timeout\n"); 6095 } 6096 6097 mpi3mr_dprint(sc, MPI3MR_INFO, 6098 "ioc_status/ioc_config after %s shutdown is (0x%x)/(0x%x)\n", 6099 (!retval)?"successful":"failed", ioc_status, 6100 ioc_config); 6101 } 6102 6103 /** 6104 * mpi3mr_cleanup_ioc - Cleanup controller 6105 * @sc: Adapter instance reference 6106 6107 * controller cleanup handler, Message unit reset or soft reset 6108 * and shutdown notification is issued to the controller. 6109 * 6110 * Return: Nothing. 6111 */ 6112 void mpi3mr_cleanup_ioc(struct mpi3mr_softc *sc) 6113 { 6114 enum mpi3mr_iocstate ioc_state; 6115 6116 mpi3mr_dprint(sc, MPI3MR_INFO, "cleaning up the controller\n"); 6117 mpi3mr_disable_interrupts(sc); 6118 6119 ioc_state = mpi3mr_get_iocstate(sc); 6120 6121 if ((!sc->unrecoverable) && (!sc->reset_in_progress) && 6122 (ioc_state == MRIOC_STATE_READY)) { 6123 if (mpi3mr_mur_ioc(sc, 6124 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 6125 mpi3mr_issue_reset(sc, 6126 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 6127 MPI3MR_RESET_FROM_MUR_FAILURE); 6128 mpi3mr_issue_ioc_shutdown(sc); 6129 } 6130 6131 mpi3mr_dprint(sc, MPI3MR_INFO, "controller cleanup completed\n"); 6132 } 6133