1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved. 3 * Copyright (c) 2022 NVIDIA corporation & affiliates. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include "opt_rss.h" 28 #include "opt_ratelimit.h" 29 30 #include <linux/kmod.h> 31 #include <linux/module.h> 32 #include <linux/errno.h> 33 #include <linux/pci.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/slab.h> 36 #include <linux/io-mapping.h> 37 #include <linux/interrupt.h> 38 #include <linux/hardirq.h> 39 #include <dev/mlx5/driver.h> 40 #include <dev/mlx5/cq.h> 41 #include <dev/mlx5/qp.h> 42 #include <dev/mlx5/srq.h> 43 #include <dev/mlx5/mpfs.h> 44 #include <dev/mlx5/vport.h> 45 #include <linux/delay.h> 46 #include <dev/mlx5/mlx5_ifc.h> 47 #include <dev/mlx5/mlx5_fpga/core.h> 48 #include <dev/mlx5/mlx5_lib/mlx5.h> 49 #include <dev/mlx5/mlx5_core/mlx5_core.h> 50 #include <dev/mlx5/mlx5_core/eswitch.h> 51 #include <dev/mlx5/mlx5_core/fs_core.h> 52 #include <dev/mlx5/mlx5_core/diag_cnt.h> 53 #ifdef PCI_IOV 54 #include <sys/nv.h> 55 #include <dev/pci/pci_iov.h> 56 #include <sys/iov_schema.h> 57 #endif 58 59 static const char mlx5_version[] = "Mellanox Core driver " 60 DRIVER_VERSION " (" DRIVER_RELDATE ")"; 61 MODULE_DESCRIPTION("Mellanox ConnectX-4 and onwards core driver"); 62 MODULE_LICENSE("Dual BSD/GPL"); 63 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 64 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1); 65 MODULE_DEPEND(mlx5, firmware, 1, 1, 1); 66 MODULE_VERSION(mlx5, 1); 67 68 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 69 "mlx5 hardware controls"); 70 71 int mlx5_core_debug_mask; 72 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN, 73 &mlx5_core_debug_mask, 0, 74 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 75 76 #define MLX5_DEFAULT_PROF 2 77 static int mlx5_prof_sel = MLX5_DEFAULT_PROF; 78 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN, 79 &mlx5_prof_sel, 0, 80 "profile selector. Valid range 0 - 2"); 81 82 static int mlx5_fast_unload_enabled = 1; 83 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN, 84 &mlx5_fast_unload_enabled, 0, 85 "Set to enable fast unload. Clear to disable."); 86 87 static int mlx5_core_comp_eq_size = 1024; 88 SYSCTL_INT(_hw_mlx5, OID_AUTO, comp_eq_size, CTLFLAG_RDTUN | CTLFLAG_MPSAFE, 89 &mlx5_core_comp_eq_size, 0, 90 "Set default completion EQ size between 1024 and 16384 inclusivly. Value should be power of two."); 91 92 static LIST_HEAD(intf_list); 93 static LIST_HEAD(dev_list); 94 static DEFINE_MUTEX(intf_mutex); 95 96 struct mlx5_device_context { 97 struct list_head list; 98 struct mlx5_interface *intf; 99 void *context; 100 }; 101 102 enum { 103 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 104 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 105 }; 106 107 static struct mlx5_profile profiles[] = { 108 [0] = { 109 .mask = 0, 110 }, 111 [1] = { 112 .mask = MLX5_PROF_MASK_QP_SIZE, 113 .log_max_qp = 12, 114 }, 115 [2] = { 116 .mask = MLX5_PROF_MASK_QP_SIZE | 117 MLX5_PROF_MASK_MR_CACHE, 118 .log_max_qp = 17, 119 .mr_cache[0] = { 120 .size = 500, 121 .limit = 250 122 }, 123 .mr_cache[1] = { 124 .size = 500, 125 .limit = 250 126 }, 127 .mr_cache[2] = { 128 .size = 500, 129 .limit = 250 130 }, 131 .mr_cache[3] = { 132 .size = 500, 133 .limit = 250 134 }, 135 .mr_cache[4] = { 136 .size = 500, 137 .limit = 250 138 }, 139 .mr_cache[5] = { 140 .size = 500, 141 .limit = 250 142 }, 143 .mr_cache[6] = { 144 .size = 500, 145 .limit = 250 146 }, 147 .mr_cache[7] = { 148 .size = 500, 149 .limit = 250 150 }, 151 .mr_cache[8] = { 152 .size = 500, 153 .limit = 250 154 }, 155 .mr_cache[9] = { 156 .size = 500, 157 .limit = 250 158 }, 159 .mr_cache[10] = { 160 .size = 500, 161 .limit = 250 162 }, 163 .mr_cache[11] = { 164 .size = 500, 165 .limit = 250 166 }, 167 .mr_cache[12] = { 168 .size = 64, 169 .limit = 32 170 }, 171 .mr_cache[13] = { 172 .size = 32, 173 .limit = 16 174 }, 175 .mr_cache[14] = { 176 .size = 16, 177 .limit = 8 178 }, 179 }, 180 [3] = { 181 .mask = MLX5_PROF_MASK_QP_SIZE, 182 .log_max_qp = 17, 183 }, 184 }; 185 186 static int 187 mlx5_core_get_comp_eq_size(void) 188 { 189 int value = mlx5_core_comp_eq_size; 190 191 if (value < 1024) 192 value = 1024; 193 else if (value > 16384) 194 value = 16384; 195 196 /* make value power of two, rounded down */ 197 while (value & (value - 1)) 198 value &= (value - 1); 199 return (value); 200 } 201 202 static void mlx5_set_driver_version(struct mlx5_core_dev *dev) 203 { 204 const size_t driver_ver_sz = 205 MLX5_FLD_SZ_BYTES(set_driver_version_in, driver_version); 206 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {}; 207 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {}; 208 char *string; 209 210 if (!MLX5_CAP_GEN(dev, driver_version)) 211 return; 212 213 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version); 214 215 snprintf(string, driver_ver_sz, "FreeBSD,mlx5_core,%u.%u.%u," DRIVER_VERSION, 216 __FreeBSD_version / 100000, (__FreeBSD_version / 1000) % 100, 217 __FreeBSD_version % 1000); 218 219 /* Send the command */ 220 MLX5_SET(set_driver_version_in, in, opcode, 221 MLX5_CMD_OP_SET_DRIVER_VERSION); 222 223 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 224 } 225 226 #ifdef PCI_IOV 227 static const char iov_mac_addr_name[] = "mac-addr"; 228 static const char iov_node_guid_name[] = "node-guid"; 229 static const char iov_port_guid_name[] = "port-guid"; 230 #endif 231 232 static int set_dma_caps(struct pci_dev *pdev) 233 { 234 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 235 int err; 236 237 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 238 if (err) { 239 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n"); 240 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 241 if (err) { 242 mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n"); 243 return err; 244 } 245 } 246 247 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 248 if (err) { 249 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n"); 250 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 251 if (err) { 252 mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n"); 253 return err; 254 } 255 } 256 257 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 258 return err; 259 } 260 261 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev, 262 u16 *p_power, u8 *p_status) 263 { 264 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; 265 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; 266 int err; 267 268 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 269 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0); 270 271 *p_status = MLX5_GET(mpein_reg, out, pwr_status); 272 *p_power = MLX5_GET(mpein_reg, out, pci_power); 273 return err; 274 } 275 276 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 277 { 278 struct pci_dev *pdev = dev->pdev; 279 int err = 0; 280 281 mutex_lock(&dev->pci_status_mutex); 282 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 283 err = pci_enable_device(pdev); 284 if (!err) 285 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 286 } 287 mutex_unlock(&dev->pci_status_mutex); 288 289 return err; 290 } 291 292 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 293 { 294 struct pci_dev *pdev = dev->pdev; 295 296 mutex_lock(&dev->pci_status_mutex); 297 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 298 pci_disable_device(pdev); 299 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 300 } 301 mutex_unlock(&dev->pci_status_mutex); 302 } 303 304 static int request_bar(struct pci_dev *pdev) 305 { 306 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 307 int err = 0; 308 309 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 310 mlx5_core_err(dev, "Missing registers BAR, aborting\n"); 311 return -ENODEV; 312 } 313 314 err = pci_request_regions(pdev, DRIVER_NAME); 315 if (err) 316 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n"); 317 318 return err; 319 } 320 321 static void release_bar(struct pci_dev *pdev) 322 { 323 pci_release_regions(pdev); 324 } 325 326 static int mlx5_enable_msix(struct mlx5_core_dev *dev) 327 { 328 struct mlx5_priv *priv = &dev->priv; 329 struct mlx5_eq_table *table = &priv->eq_table; 330 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 331 int limit = dev->msix_eqvec; 332 int nvec = MLX5_EQ_VEC_COMP_BASE; 333 int i; 334 335 if (limit > 0) 336 nvec += limit; 337 else 338 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 339 340 if (nvec > num_eqs) 341 nvec = num_eqs; 342 if (nvec > 256) 343 nvec = 256; /* limit of firmware API */ 344 if (nvec <= MLX5_EQ_VEC_COMP_BASE) 345 return -ENOMEM; 346 347 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 348 349 for (i = 0; i < nvec; i++) 350 priv->msix_arr[i].entry = i; 351 352 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 353 MLX5_EQ_VEC_COMP_BASE + 1, nvec); 354 if (nvec < 0) 355 return nvec; 356 357 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 358 return 0; 359 } 360 361 static void mlx5_disable_msix(struct mlx5_core_dev *dev) 362 { 363 struct mlx5_priv *priv = &dev->priv; 364 365 pci_disable_msix(dev->pdev); 366 kfree(priv->msix_arr); 367 } 368 369 struct mlx5_reg_host_endianess { 370 u8 he; 371 u8 rsvd[15]; 372 }; 373 374 375 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 376 377 enum { 378 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 379 MLX5_DEV_CAP_FLAG_DCT | 380 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 381 }; 382 383 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 384 { 385 switch (size) { 386 case 128: 387 return 0; 388 case 256: 389 return 1; 390 case 512: 391 return 2; 392 case 1024: 393 return 3; 394 case 2048: 395 return 4; 396 case 4096: 397 return 5; 398 default: 399 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 400 return 0; 401 } 402 } 403 404 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 405 enum mlx5_cap_type cap_type, 406 enum mlx5_cap_mode cap_mode) 407 { 408 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 409 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 410 void *out, *hca_caps; 411 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 412 int err; 413 414 memset(in, 0, sizeof(in)); 415 out = kzalloc(out_sz, GFP_KERNEL); 416 417 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 418 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 419 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 420 if (err) { 421 mlx5_core_warn(dev, 422 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 423 cap_type, cap_mode, err); 424 goto query_ex; 425 } 426 427 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 428 429 switch (cap_mode) { 430 case HCA_CAP_OPMOD_GET_MAX: 431 memcpy(dev->hca_caps_max[cap_type], hca_caps, 432 MLX5_UN_SZ_BYTES(hca_cap_union)); 433 break; 434 case HCA_CAP_OPMOD_GET_CUR: 435 memcpy(dev->hca_caps_cur[cap_type], hca_caps, 436 MLX5_UN_SZ_BYTES(hca_cap_union)); 437 break; 438 default: 439 mlx5_core_warn(dev, 440 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 441 cap_type, cap_mode); 442 err = -EINVAL; 443 break; 444 } 445 query_ex: 446 kfree(out); 447 return err; 448 } 449 450 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 451 { 452 int ret; 453 454 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 455 if (ret) 456 return ret; 457 458 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 459 } 460 461 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 462 { 463 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 464 465 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 466 467 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 468 } 469 470 static int handle_hca_cap(struct mlx5_core_dev *dev) 471 { 472 void *set_ctx = NULL; 473 struct mlx5_profile *prof = dev->profile; 474 int err = -ENOMEM; 475 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 476 void *set_hca_cap; 477 478 set_ctx = kzalloc(set_sz, GFP_KERNEL); 479 480 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 481 if (err) 482 goto query_ex; 483 484 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 485 capability); 486 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 487 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 488 489 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 490 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 491 128); 492 /* we limit the size of the pkey table to 128 entries for now */ 493 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 494 to_fw_pkey_sz(dev, 128)); 495 496 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 497 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 498 prof->log_max_qp); 499 500 /* disable cmdif checksum */ 501 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 502 503 /* Enable 4K UAR only when HCA supports it and page size is bigger 504 * than 4K. 505 */ 506 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 507 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 508 509 /* enable drain sigerr */ 510 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 511 512 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 513 514 err = set_caps(dev, set_ctx, set_sz); 515 516 query_ex: 517 kfree(set_ctx); 518 return err; 519 } 520 521 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 522 { 523 void *set_ctx; 524 void *set_hca_cap; 525 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 526 int req_endianness; 527 int err; 528 529 if (MLX5_CAP_GEN(dev, atomic)) { 530 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 531 if (err) 532 return err; 533 } else { 534 return 0; 535 } 536 537 req_endianness = 538 MLX5_CAP_ATOMIC(dev, 539 supported_atomic_req_8B_endianess_mode_1); 540 541 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 542 return 0; 543 544 set_ctx = kzalloc(set_sz, GFP_KERNEL); 545 if (!set_ctx) 546 return -ENOMEM; 547 548 MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 549 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 550 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 551 552 /* Set requestor to host endianness */ 553 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 554 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 555 556 err = set_caps(dev, set_ctx, set_sz); 557 558 kfree(set_ctx); 559 return err; 560 } 561 562 static int set_hca_ctrl(struct mlx5_core_dev *dev) 563 { 564 struct mlx5_reg_host_endianess he_in; 565 struct mlx5_reg_host_endianess he_out; 566 int err; 567 568 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 569 !MLX5_CAP_GEN(dev, roce)) 570 return 0; 571 572 memset(&he_in, 0, sizeof(he_in)); 573 he_in.he = MLX5_SET_HOST_ENDIANNESS; 574 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 575 &he_out, sizeof(he_out), 576 MLX5_REG_HOST_ENDIANNESS, 0, 1); 577 return err; 578 } 579 580 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev) 581 { 582 int ret = 0; 583 584 /* Disable local_lb by default */ 585 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) 586 ret = mlx5_nic_vport_update_local_lb(dev, false); 587 588 return ret; 589 } 590 591 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 592 { 593 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 594 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 595 596 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 597 MLX5_SET(enable_hca_in, in, function_id, func_id); 598 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 599 } 600 601 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 602 { 603 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 604 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 605 606 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 607 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 608 } 609 610 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 611 { 612 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 613 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 614 u32 sup_issi; 615 int err; 616 617 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 618 619 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 620 if (err) { 621 u32 syndrome; 622 u8 status; 623 624 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 625 if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 626 mlx5_core_dbg(dev, "Only ISSI 0 is supported\n"); 627 return 0; 628 } 629 630 mlx5_core_err(dev, "failed to query ISSI\n"); 631 return err; 632 } 633 634 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 635 636 if (sup_issi & (1 << 1)) { 637 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 638 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 639 640 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 641 MLX5_SET(set_issi_in, set_in, current_issi, 1); 642 643 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 644 if (err) { 645 mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err); 646 return err; 647 } 648 649 dev->issi = 1; 650 651 return 0; 652 } else if (sup_issi & (1 << 0)) { 653 return 0; 654 } 655 656 return -ENOTSUPP; 657 } 658 659 660 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 661 { 662 struct mlx5_eq_table *table = &dev->priv.eq_table; 663 struct mlx5_eq *eq; 664 int err = -ENOENT; 665 666 spin_lock(&table->lock); 667 list_for_each_entry(eq, &table->comp_eqs_list, list) { 668 if (eq->index == vector) { 669 *eqn = eq->eqn; 670 *irqn = eq->irqn; 671 err = 0; 672 break; 673 } 674 } 675 spin_unlock(&table->lock); 676 677 return err; 678 } 679 EXPORT_SYMBOL(mlx5_vector2eqn); 680 681 static void free_comp_eqs(struct mlx5_core_dev *dev) 682 { 683 struct mlx5_eq_table *table = &dev->priv.eq_table; 684 struct mlx5_eq *eq, *n; 685 686 spin_lock(&table->lock); 687 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 688 list_del(&eq->list); 689 spin_unlock(&table->lock); 690 if (mlx5_destroy_unmap_eq(dev, eq)) 691 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 692 eq->eqn); 693 kfree(eq); 694 spin_lock(&table->lock); 695 } 696 spin_unlock(&table->lock); 697 } 698 699 static int alloc_comp_eqs(struct mlx5_core_dev *dev) 700 { 701 struct mlx5_eq_table *table = &dev->priv.eq_table; 702 struct mlx5_eq *eq; 703 int ncomp_vec; 704 int nent; 705 int err; 706 int i; 707 708 INIT_LIST_HEAD(&table->comp_eqs_list); 709 ncomp_vec = table->num_comp_vectors; 710 nent = mlx5_core_get_comp_eq_size(); 711 for (i = 0; i < ncomp_vec; i++) { 712 eq = kzalloc_node(sizeof(*eq), GFP_KERNEL, dev->priv.numa_node); 713 714 err = mlx5_create_map_eq(dev, eq, 715 i + MLX5_EQ_VEC_COMP_BASE, nent, 0); 716 if (err) { 717 kfree(eq); 718 goto clean; 719 } 720 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 721 eq->index = i; 722 spin_lock(&table->lock); 723 list_add_tail(&eq->list, &table->comp_eqs_list); 724 spin_unlock(&table->lock); 725 } 726 727 return 0; 728 729 clean: 730 free_comp_eqs(dev); 731 return err; 732 } 733 734 static inline int fw_initializing(struct mlx5_core_dev *dev) 735 { 736 return ioread32be(&dev->iseg->initializing) >> 31; 737 } 738 739 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 740 u32 warn_time_mili) 741 { 742 int warn = jiffies + msecs_to_jiffies(warn_time_mili); 743 int end = jiffies + msecs_to_jiffies(max_wait_mili); 744 int err = 0; 745 746 MPASS(max_wait_mili > warn_time_mili); 747 748 while (fw_initializing(dev) == 1) { 749 if (time_after(jiffies, end)) { 750 err = -EBUSY; 751 break; 752 } 753 if (warn_time_mili && time_after(jiffies, warn)) { 754 mlx5_core_warn(dev, 755 "Waiting for FW initialization, timeout abort in %u s\n", 756 (unsigned)(jiffies_to_msecs(end - warn) / 1000)); 757 warn = jiffies + msecs_to_jiffies(warn_time_mili); 758 } 759 msleep(FW_INIT_WAIT_MS); 760 } 761 762 if (err != 0) 763 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n", 764 ioread32be(&dev->iseg->initializing)); 765 766 return err; 767 } 768 769 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 770 { 771 struct mlx5_device_context *dev_ctx; 772 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 773 774 dev_ctx = kzalloc_node(sizeof(*dev_ctx), GFP_KERNEL, priv->numa_node); 775 if (!dev_ctx) 776 return; 777 778 dev_ctx->intf = intf; 779 CURVNET_SET_QUIET(vnet0); 780 dev_ctx->context = intf->add(dev); 781 CURVNET_RESTORE(); 782 783 if (dev_ctx->context) { 784 spin_lock_irq(&priv->ctx_lock); 785 list_add_tail(&dev_ctx->list, &priv->ctx_list); 786 spin_unlock_irq(&priv->ctx_lock); 787 } else { 788 kfree(dev_ctx); 789 } 790 } 791 792 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 793 { 794 struct mlx5_device_context *dev_ctx; 795 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 796 797 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 798 if (dev_ctx->intf == intf) { 799 spin_lock_irq(&priv->ctx_lock); 800 list_del(&dev_ctx->list); 801 spin_unlock_irq(&priv->ctx_lock); 802 803 intf->remove(dev, dev_ctx->context); 804 kfree(dev_ctx); 805 return; 806 } 807 } 808 809 int 810 mlx5_register_device(struct mlx5_core_dev *dev) 811 { 812 struct mlx5_priv *priv = &dev->priv; 813 struct mlx5_interface *intf; 814 815 mutex_lock(&intf_mutex); 816 list_add_tail(&priv->dev_list, &dev_list); 817 list_for_each_entry(intf, &intf_list, list) 818 mlx5_add_device(intf, priv); 819 mutex_unlock(&intf_mutex); 820 821 return 0; 822 } 823 824 void 825 mlx5_unregister_device(struct mlx5_core_dev *dev) 826 { 827 struct mlx5_priv *priv = &dev->priv; 828 struct mlx5_interface *intf; 829 830 mutex_lock(&intf_mutex); 831 list_for_each_entry(intf, &intf_list, list) 832 mlx5_remove_device(intf, priv); 833 list_del(&priv->dev_list); 834 mutex_unlock(&intf_mutex); 835 } 836 837 int mlx5_register_interface(struct mlx5_interface *intf) 838 { 839 struct mlx5_priv *priv; 840 841 if (!intf->add || !intf->remove) 842 return -EINVAL; 843 844 mutex_lock(&intf_mutex); 845 list_add_tail(&intf->list, &intf_list); 846 list_for_each_entry(priv, &dev_list, dev_list) 847 mlx5_add_device(intf, priv); 848 mutex_unlock(&intf_mutex); 849 850 return 0; 851 } 852 EXPORT_SYMBOL(mlx5_register_interface); 853 854 void mlx5_unregister_interface(struct mlx5_interface *intf) 855 { 856 struct mlx5_priv *priv; 857 858 mutex_lock(&intf_mutex); 859 list_for_each_entry(priv, &dev_list, dev_list) 860 mlx5_remove_device(intf, priv); 861 list_del(&intf->list); 862 mutex_unlock(&intf_mutex); 863 } 864 EXPORT_SYMBOL(mlx5_unregister_interface); 865 866 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 867 { 868 struct mlx5_priv *priv = &mdev->priv; 869 struct mlx5_device_context *dev_ctx; 870 unsigned long flags; 871 void *result = NULL; 872 873 spin_lock_irqsave(&priv->ctx_lock, flags); 874 875 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 876 if ((dev_ctx->intf->protocol == protocol) && 877 dev_ctx->intf->get_dev) { 878 result = dev_ctx->intf->get_dev(dev_ctx->context); 879 break; 880 } 881 882 spin_unlock_irqrestore(&priv->ctx_lock, flags); 883 884 return result; 885 } 886 EXPORT_SYMBOL(mlx5_get_protocol_dev); 887 888 static int mlx5_auto_fw_update; 889 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 890 &mlx5_auto_fw_update, 0, 891 "Allow automatic firmware update on driver start"); 892 static int 893 mlx5_firmware_update(struct mlx5_core_dev *dev) 894 { 895 const struct firmware *fw; 896 int err; 897 898 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update); 899 if (!mlx5_auto_fw_update) 900 return (0); 901 fw = firmware_get("mlx5fw_mfa"); 902 if (fw) { 903 err = mlx5_firmware_flash(dev, fw); 904 firmware_put(fw, FIRMWARE_UNLOAD); 905 } 906 else 907 return (-ENOENT); 908 909 return err; 910 } 911 912 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 913 { 914 struct pci_dev *pdev = dev->pdev; 915 int err; 916 917 pdev = dev->pdev; 918 pci_set_drvdata(dev->pdev, dev); 919 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 920 priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 921 922 mutex_init(&priv->pgdir_mutex); 923 INIT_LIST_HEAD(&priv->pgdir_list); 924 spin_lock_init(&priv->mkey_lock); 925 926 err = mlx5_pci_enable_device(dev); 927 if (err) { 928 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 929 goto err_dbg; 930 } 931 932 err = request_bar(pdev); 933 if (err) { 934 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 935 goto err_disable; 936 } 937 938 pci_set_master(pdev); 939 940 err = set_dma_caps(pdev); 941 if (err) { 942 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 943 goto err_clr_master; 944 } 945 946 dev->iseg_base = pci_resource_start(dev->pdev, 0); 947 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 948 if (!dev->iseg) { 949 err = -ENOMEM; 950 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 951 goto err_clr_master; 952 } 953 954 return 0; 955 956 err_clr_master: 957 release_bar(dev->pdev); 958 err_disable: 959 mlx5_pci_disable_device(dev); 960 err_dbg: 961 return err; 962 } 963 964 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 965 { 966 #ifdef PCI_IOV 967 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) 968 pci_iov_detach(dev->pdev->dev.bsddev); 969 #endif 970 iounmap(dev->iseg); 971 release_bar(dev->pdev); 972 mlx5_pci_disable_device(dev); 973 } 974 975 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 976 { 977 int err; 978 979 err = mlx5_vsc_find_cap(dev); 980 if (err) 981 mlx5_core_warn(dev, "Unable to find vendor specific capabilities\n"); 982 983 err = mlx5_query_hca_caps(dev); 984 if (err) { 985 mlx5_core_err(dev, "query hca failed\n"); 986 goto out; 987 } 988 989 err = mlx5_query_board_id(dev); 990 if (err) { 991 mlx5_core_err(dev, "query board id failed\n"); 992 goto out; 993 } 994 995 err = mlx5_eq_init(dev); 996 if (err) { 997 mlx5_core_err(dev, "failed to initialize eq\n"); 998 goto out; 999 } 1000 1001 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 1002 1003 err = mlx5_init_cq_table(dev); 1004 if (err) { 1005 mlx5_core_err(dev, "failed to initialize cq table\n"); 1006 goto err_eq_cleanup; 1007 } 1008 1009 mlx5_init_qp_table(dev); 1010 mlx5_init_srq_table(dev); 1011 mlx5_init_mr_table(dev); 1012 1013 mlx5_init_reserved_gids(dev); 1014 mlx5_fpga_init(dev); 1015 1016 #ifdef RATELIMIT 1017 err = mlx5_init_rl_table(dev); 1018 if (err) { 1019 mlx5_core_err(dev, "Failed to init rate limiting\n"); 1020 goto err_tables_cleanup; 1021 } 1022 #endif 1023 return 0; 1024 1025 #ifdef RATELIMIT 1026 err_tables_cleanup: 1027 mlx5_cleanup_mr_table(dev); 1028 mlx5_cleanup_srq_table(dev); 1029 mlx5_cleanup_qp_table(dev); 1030 mlx5_cleanup_cq_table(dev); 1031 #endif 1032 1033 err_eq_cleanup: 1034 mlx5_eq_cleanup(dev); 1035 1036 out: 1037 return err; 1038 } 1039 1040 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 1041 { 1042 #ifdef RATELIMIT 1043 mlx5_cleanup_rl_table(dev); 1044 #endif 1045 mlx5_fpga_cleanup(dev); 1046 mlx5_cleanup_reserved_gids(dev); 1047 mlx5_cleanup_mr_table(dev); 1048 mlx5_cleanup_srq_table(dev); 1049 mlx5_cleanup_qp_table(dev); 1050 mlx5_cleanup_cq_table(dev); 1051 mlx5_eq_cleanup(dev); 1052 } 1053 1054 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1055 bool boot) 1056 { 1057 int err; 1058 1059 mutex_lock(&dev->intf_state_mutex); 1060 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1061 mlx5_core_warn(dev, "interface is up, NOP\n"); 1062 goto out; 1063 } 1064 1065 mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n", 1066 fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 1067 1068 /* 1069 * On load removing any previous indication of internal error, 1070 * device is up 1071 */ 1072 dev->state = MLX5_DEVICE_STATE_UP; 1073 1074 /* wait for firmware to accept initialization segments configurations 1075 */ 1076 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, 1077 FW_INIT_WARN_MESSAGE_INTERVAL); 1078 if (err) { 1079 dev_err(&dev->pdev->dev, 1080 "Firmware over %d MS in pre-initializing state, aborting\n", 1081 FW_PRE_INIT_TIMEOUT_MILI); 1082 goto out_err; 1083 } 1084 1085 err = mlx5_cmd_init(dev); 1086 if (err) { 1087 mlx5_core_err(dev, 1088 "Failed initializing command interface, aborting\n"); 1089 goto out_err; 1090 } 1091 1092 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 1093 if (err) { 1094 mlx5_core_err(dev, 1095 "Firmware over %d MS in initializing state, aborting\n", 1096 FW_INIT_TIMEOUT_MILI); 1097 goto err_cmd_cleanup; 1098 } 1099 1100 err = mlx5_core_enable_hca(dev, 0); 1101 if (err) { 1102 mlx5_core_err(dev, "enable hca failed\n"); 1103 goto err_cmd_cleanup; 1104 } 1105 1106 err = mlx5_core_set_issi(dev); 1107 if (err) { 1108 mlx5_core_err(dev, "failed to set issi\n"); 1109 goto err_disable_hca; 1110 } 1111 1112 err = mlx5_pagealloc_start(dev); 1113 if (err) { 1114 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n"); 1115 goto err_disable_hca; 1116 } 1117 1118 err = mlx5_satisfy_startup_pages(dev, 1); 1119 if (err) { 1120 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1121 goto err_pagealloc_stop; 1122 } 1123 1124 err = set_hca_ctrl(dev); 1125 if (err) { 1126 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1127 goto reclaim_boot_pages; 1128 } 1129 1130 err = handle_hca_cap(dev); 1131 if (err) { 1132 mlx5_core_err(dev, "handle_hca_cap failed\n"); 1133 goto reclaim_boot_pages; 1134 } 1135 1136 err = handle_hca_cap_atomic(dev); 1137 if (err) { 1138 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 1139 goto reclaim_boot_pages; 1140 } 1141 1142 err = mlx5_satisfy_startup_pages(dev, 0); 1143 if (err) { 1144 mlx5_core_err(dev, "failed to allocate init pages\n"); 1145 goto reclaim_boot_pages; 1146 } 1147 1148 err = mlx5_cmd_init_hca(dev); 1149 if (err) { 1150 mlx5_core_err(dev, "init hca failed\n"); 1151 goto reclaim_boot_pages; 1152 } 1153 1154 mlx5_set_driver_version(dev); 1155 1156 mlx5_start_health_poll(dev); 1157 1158 if (boot && (err = mlx5_init_once(dev, priv))) { 1159 mlx5_core_err(dev, "sw objs init failed\n"); 1160 goto err_stop_poll; 1161 } 1162 1163 dev->priv.uar = mlx5_get_uars_page(dev); 1164 if (IS_ERR(dev->priv.uar)) { 1165 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1166 err = PTR_ERR(dev->priv.uar); 1167 goto err_cleanup_once; 1168 } 1169 1170 err = mlx5_enable_msix(dev); 1171 if (err) { 1172 mlx5_core_err(dev, "enable msix failed\n"); 1173 goto err_cleanup_uar; 1174 } 1175 1176 err = mlx5_start_eqs(dev); 1177 if (err) { 1178 mlx5_core_err(dev, "Failed to start pages and async EQs\n"); 1179 goto err_disable_msix; 1180 } 1181 1182 err = alloc_comp_eqs(dev); 1183 if (err) { 1184 mlx5_core_err(dev, "Failed to alloc completion EQs\n"); 1185 goto err_stop_eqs; 1186 } 1187 1188 err = mlx5_init_fs(dev); 1189 if (err) { 1190 mlx5_core_err(dev, "flow steering init %d\n", err); 1191 goto err_free_comp_eqs; 1192 } 1193 1194 err = mlx5_core_set_hca_defaults(dev); 1195 if (err) { 1196 mlx5_core_err(dev, "Failed to set HCA defaults %d\n", err); 1197 goto err_free_comp_eqs; 1198 } 1199 1200 err = mlx5_mpfs_init(dev); 1201 if (err) { 1202 mlx5_core_err(dev, "mpfs init failed %d\n", err); 1203 goto err_fs; 1204 } 1205 1206 err = mlx5_fpga_device_start(dev); 1207 if (err) { 1208 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1209 goto err_mpfs; 1210 } 1211 1212 err = mlx5_diag_cnt_init(dev); 1213 if (err) { 1214 mlx5_core_err(dev, "diag cnt init failed %d\n", err); 1215 goto err_fpga; 1216 } 1217 1218 err = mlx5_register_device(dev); 1219 if (err) { 1220 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err); 1221 goto err_diag_cnt; 1222 } 1223 1224 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1225 1226 out: 1227 mutex_unlock(&dev->intf_state_mutex); 1228 return 0; 1229 1230 err_diag_cnt: 1231 mlx5_diag_cnt_cleanup(dev); 1232 1233 err_fpga: 1234 mlx5_fpga_device_stop(dev); 1235 1236 err_mpfs: 1237 mlx5_mpfs_destroy(dev); 1238 1239 err_fs: 1240 mlx5_cleanup_fs(dev); 1241 1242 err_free_comp_eqs: 1243 free_comp_eqs(dev); 1244 1245 err_stop_eqs: 1246 mlx5_stop_eqs(dev); 1247 1248 err_disable_msix: 1249 mlx5_disable_msix(dev); 1250 1251 err_cleanup_uar: 1252 mlx5_put_uars_page(dev, dev->priv.uar); 1253 1254 err_cleanup_once: 1255 if (boot) 1256 mlx5_cleanup_once(dev); 1257 1258 err_stop_poll: 1259 mlx5_stop_health_poll(dev, boot); 1260 if (mlx5_cmd_teardown_hca(dev)) { 1261 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1262 goto out_err; 1263 } 1264 1265 reclaim_boot_pages: 1266 mlx5_reclaim_startup_pages(dev); 1267 1268 err_pagealloc_stop: 1269 mlx5_pagealloc_stop(dev); 1270 1271 err_disable_hca: 1272 mlx5_core_disable_hca(dev); 1273 1274 err_cmd_cleanup: 1275 mlx5_cmd_cleanup(dev); 1276 1277 out_err: 1278 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1279 mutex_unlock(&dev->intf_state_mutex); 1280 1281 return err; 1282 } 1283 1284 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1285 bool cleanup) 1286 { 1287 int err = 0; 1288 1289 if (cleanup) 1290 mlx5_drain_health_recovery(dev); 1291 1292 mutex_lock(&dev->intf_state_mutex); 1293 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1294 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__); 1295 if (cleanup) 1296 mlx5_cleanup_once(dev); 1297 goto out; 1298 } 1299 1300 mlx5_unregister_device(dev); 1301 1302 mlx5_eswitch_cleanup(dev->priv.eswitch); 1303 mlx5_diag_cnt_cleanup(dev); 1304 mlx5_fpga_device_stop(dev); 1305 mlx5_mpfs_destroy(dev); 1306 mlx5_cleanup_fs(dev); 1307 mlx5_wait_for_reclaim_vfs_pages(dev); 1308 free_comp_eqs(dev); 1309 mlx5_stop_eqs(dev); 1310 mlx5_disable_msix(dev); 1311 mlx5_put_uars_page(dev, dev->priv.uar); 1312 if (cleanup) 1313 mlx5_cleanup_once(dev); 1314 mlx5_stop_health_poll(dev, cleanup); 1315 err = mlx5_cmd_teardown_hca(dev); 1316 if (err) { 1317 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1318 goto out; 1319 } 1320 mlx5_pagealloc_stop(dev); 1321 mlx5_reclaim_startup_pages(dev); 1322 mlx5_core_disable_hca(dev); 1323 mlx5_cmd_cleanup(dev); 1324 1325 out: 1326 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1327 mutex_unlock(&dev->intf_state_mutex); 1328 return err; 1329 } 1330 1331 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1332 unsigned long param) 1333 { 1334 struct mlx5_priv *priv = &dev->priv; 1335 struct mlx5_device_context *dev_ctx; 1336 unsigned long flags; 1337 1338 spin_lock_irqsave(&priv->ctx_lock, flags); 1339 1340 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1341 if (dev_ctx->intf->event) 1342 dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1343 1344 spin_unlock_irqrestore(&priv->ctx_lock, flags); 1345 } 1346 1347 struct mlx5_core_event_handler { 1348 void (*event)(struct mlx5_core_dev *dev, 1349 enum mlx5_dev_event event, 1350 void *data); 1351 }; 1352 1353 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e, 1354 1355 #define MLX5_PORT_MODULE_ERROR_STATS(m) \ 1356 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \ 1357 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \ 1358 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \ 1359 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \ 1360 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \ 1361 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \ 1362 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \ 1363 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") \ 1364 m(+1, u64, pmd_type_not_enabled, "pmd_type_not_enabled", "PMD type is not enabled") \ 1365 m(+1, u64, laster_tec_failure, "laster_tec_failure", "Laster TEC failure") \ 1366 m(+1, u64, high_current, "high_current", "High current") \ 1367 m(+1, u64, high_voltage, "high_voltage", "High voltage") \ 1368 m(+1, u64, pcie_sys_power_slot_exceeded, "pcie_sys_power_slot_exceeded", "PCIe system power slot Exceeded") \ 1369 m(+1, u64, high_power, "high_power", "High power") \ 1370 m(+1, u64, module_state_machine_fault, "module_state_machine_fault", "Module State Machine fault") 1371 1372 static const char *mlx5_pme_err_desc[] = { 1373 MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC) 1374 }; 1375 1376 static int init_one(struct pci_dev *pdev, 1377 const struct pci_device_id *id) 1378 { 1379 struct mlx5_core_dev *dev; 1380 struct mlx5_priv *priv; 1381 device_t bsddev = pdev->dev.bsddev; 1382 #ifdef PCI_IOV 1383 nvlist_t *pf_schema, *vf_schema; 1384 int num_vfs, sriov_pos; 1385 #endif 1386 int i,err; 1387 int numa_node; 1388 struct sysctl_oid *pme_sysctl_node; 1389 struct sysctl_oid *pme_err_sysctl_node; 1390 struct sysctl_oid *cap_sysctl_node; 1391 struct sysctl_oid *current_cap_sysctl_node; 1392 struct sysctl_oid *max_cap_sysctl_node; 1393 1394 printk_once("mlx5: %s", mlx5_version); 1395 1396 numa_node = dev_to_node(&pdev->dev); 1397 1398 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, numa_node); 1399 1400 priv = &dev->priv; 1401 priv->numa_node = numa_node; 1402 1403 if (id) 1404 priv->pci_dev_data = id->driver_data; 1405 1406 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) { 1407 device_printf(bsddev, 1408 "WARN: selected profile out of range, selecting default (%d)\n", 1409 MLX5_DEFAULT_PROF); 1410 mlx5_prof_sel = MLX5_DEFAULT_PROF; 1411 } 1412 dev->profile = &profiles[mlx5_prof_sel]; 1413 dev->pdev = pdev; 1414 dev->event = mlx5_core_event; 1415 1416 /* Set desc */ 1417 device_set_desc(bsddev, mlx5_version); 1418 1419 sysctl_ctx_init(&dev->sysctl_ctx); 1420 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1421 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1422 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1423 "Maximum number of MSIX event queue vectors, if set"); 1424 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1425 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1426 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0, 1427 "0:Invalid 1:Sufficient 2:Insufficient"); 1428 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1429 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1430 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0, 1431 "Current power value in Watts"); 1432 1433 pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1434 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1435 OID_AUTO, "pme_stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1436 "Port module event statistics"); 1437 if (pme_sysctl_node == NULL) { 1438 err = -ENOMEM; 1439 goto clean_sysctl_ctx; 1440 } 1441 pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1442 SYSCTL_CHILDREN(pme_sysctl_node), 1443 OID_AUTO, "errors", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1444 "Port module event error statistics"); 1445 if (pme_err_sysctl_node == NULL) { 1446 err = -ENOMEM; 1447 goto clean_sysctl_ctx; 1448 } 1449 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1450 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1451 "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1452 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED], 1453 0, "Number of time module plugged"); 1454 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1455 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1456 "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1457 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED], 1458 0, "Number of time module unplugged"); 1459 for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) { 1460 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1461 SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO, 1462 mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE, 1463 &dev->priv.pme_stats.error_counters[i], 1464 0, mlx5_pme_err_desc[2 * i + 1]); 1465 } 1466 1467 cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1468 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1469 OID_AUTO, "caps", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1470 "hardware capabilities raw bitstrings"); 1471 if (cap_sysctl_node == NULL) { 1472 err = -ENOMEM; 1473 goto clean_sysctl_ctx; 1474 } 1475 current_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1476 SYSCTL_CHILDREN(cap_sysctl_node), 1477 OID_AUTO, "current", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1478 ""); 1479 if (current_cap_sysctl_node == NULL) { 1480 err = -ENOMEM; 1481 goto clean_sysctl_ctx; 1482 } 1483 max_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1484 SYSCTL_CHILDREN(cap_sysctl_node), 1485 OID_AUTO, "max", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1486 ""); 1487 if (max_cap_sysctl_node == NULL) { 1488 err = -ENOMEM; 1489 goto clean_sysctl_ctx; 1490 } 1491 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1492 SYSCTL_CHILDREN(current_cap_sysctl_node), 1493 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE, 1494 &dev->hca_caps_cur[MLX5_CAP_GENERAL], 1495 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1496 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1497 SYSCTL_CHILDREN(max_cap_sysctl_node), 1498 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE, 1499 &dev->hca_caps_max[MLX5_CAP_GENERAL], 1500 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1501 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1502 SYSCTL_CHILDREN(current_cap_sysctl_node), 1503 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE, 1504 &dev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], 1505 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1506 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1507 SYSCTL_CHILDREN(max_cap_sysctl_node), 1508 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE, 1509 &dev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], 1510 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1511 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1512 SYSCTL_CHILDREN(current_cap_sysctl_node), 1513 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE, 1514 &dev->hca_caps_cur[MLX5_CAP_ODP], 1515 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1516 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1517 SYSCTL_CHILDREN(max_cap_sysctl_node), 1518 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE, 1519 &dev->hca_caps_max[MLX5_CAP_ODP], 1520 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1521 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1522 SYSCTL_CHILDREN(current_cap_sysctl_node), 1523 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE, 1524 &dev->hca_caps_cur[MLX5_CAP_ATOMIC], 1525 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1526 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1527 SYSCTL_CHILDREN(max_cap_sysctl_node), 1528 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE, 1529 &dev->hca_caps_max[MLX5_CAP_ATOMIC], 1530 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1531 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1532 SYSCTL_CHILDREN(current_cap_sysctl_node), 1533 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE, 1534 &dev->hca_caps_cur[MLX5_CAP_ROCE], 1535 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1536 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1537 SYSCTL_CHILDREN(max_cap_sysctl_node), 1538 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE, 1539 &dev->hca_caps_max[MLX5_CAP_ROCE], 1540 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1541 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1542 SYSCTL_CHILDREN(current_cap_sysctl_node), 1543 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1544 &dev->hca_caps_cur[MLX5_CAP_IPOIB_OFFLOADS], 1545 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1546 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1547 SYSCTL_CHILDREN(max_cap_sysctl_node), 1548 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1549 &dev->hca_caps_max[MLX5_CAP_IPOIB_OFFLOADS], 1550 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1551 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1552 SYSCTL_CHILDREN(current_cap_sysctl_node), 1553 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1554 &dev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], 1555 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1556 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1557 SYSCTL_CHILDREN(max_cap_sysctl_node), 1558 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1559 &dev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], 1560 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1561 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1562 SYSCTL_CHILDREN(current_cap_sysctl_node), 1563 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1564 &dev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], 1565 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1566 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1567 SYSCTL_CHILDREN(max_cap_sysctl_node), 1568 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1569 &dev->hca_caps_max[MLX5_CAP_FLOW_TABLE], 1570 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1571 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1572 SYSCTL_CHILDREN(current_cap_sysctl_node), 1573 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1574 &dev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], 1575 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1576 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1577 SYSCTL_CHILDREN(max_cap_sysctl_node), 1578 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1579 &dev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], 1580 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1581 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1582 SYSCTL_CHILDREN(current_cap_sysctl_node), 1583 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE, 1584 &dev->hca_caps_cur[MLX5_CAP_ESWITCH], 1585 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1586 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1587 SYSCTL_CHILDREN(max_cap_sysctl_node), 1588 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE, 1589 &dev->hca_caps_max[MLX5_CAP_ESWITCH], 1590 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1591 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1592 SYSCTL_CHILDREN(current_cap_sysctl_node), 1593 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE, 1594 &dev->hca_caps_cur[MLX5_CAP_SNAPSHOT], 1595 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1596 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1597 SYSCTL_CHILDREN(max_cap_sysctl_node), 1598 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE, 1599 &dev->hca_caps_max[MLX5_CAP_SNAPSHOT], 1600 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1601 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1602 SYSCTL_CHILDREN(current_cap_sysctl_node), 1603 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE, 1604 &dev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], 1605 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1606 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1607 SYSCTL_CHILDREN(max_cap_sysctl_node), 1608 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE, 1609 &dev->hca_caps_max[MLX5_CAP_VECTOR_CALC], 1610 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1611 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1612 SYSCTL_CHILDREN(current_cap_sysctl_node), 1613 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE, 1614 &dev->hca_caps_cur[MLX5_CAP_QOS], 1615 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1616 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1617 SYSCTL_CHILDREN(max_cap_sysctl_node), 1618 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE, 1619 &dev->hca_caps_max[MLX5_CAP_QOS], 1620 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1621 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1622 SYSCTL_CHILDREN(current_cap_sysctl_node), 1623 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1624 &dev->hca_caps_cur[MLX5_CAP_DEBUG], 1625 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1626 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1627 SYSCTL_CHILDREN(max_cap_sysctl_node), 1628 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1629 &dev->hca_caps_max[MLX5_CAP_DEBUG], 1630 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1631 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1632 SYSCTL_CHILDREN(cap_sysctl_node), 1633 OID_AUTO, "pcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1634 &dev->caps.pcam, sizeof(dev->caps.pcam), "IU", ""); 1635 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1636 SYSCTL_CHILDREN(cap_sysctl_node), 1637 OID_AUTO, "mcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1638 &dev->caps.mcam, sizeof(dev->caps.mcam), "IU", ""); 1639 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1640 SYSCTL_CHILDREN(cap_sysctl_node), 1641 OID_AUTO, "qcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1642 &dev->caps.qcam, sizeof(dev->caps.qcam), "IU", ""); 1643 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1644 SYSCTL_CHILDREN(cap_sysctl_node), 1645 OID_AUTO, "fpga", CTLFLAG_RD | CTLFLAG_MPSAFE, 1646 &dev->caps.fpga, sizeof(dev->caps.fpga), "IU", ""); 1647 1648 INIT_LIST_HEAD(&priv->ctx_list); 1649 spin_lock_init(&priv->ctx_lock); 1650 mutex_init(&dev->pci_status_mutex); 1651 mutex_init(&dev->intf_state_mutex); 1652 1653 mutex_init(&priv->bfregs.reg_head.lock); 1654 mutex_init(&priv->bfregs.wc_head.lock); 1655 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1656 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1657 1658 mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW); 1659 err = mlx5_pci_init(dev, priv); 1660 if (err) { 1661 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err); 1662 goto clean_dev; 1663 } 1664 1665 err = mlx5_health_init(dev); 1666 if (err) { 1667 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err); 1668 goto close_pci; 1669 } 1670 1671 mlx5_pagealloc_init(dev); 1672 1673 err = mlx5_load_one(dev, priv, true); 1674 if (err) { 1675 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err); 1676 goto clean_health; 1677 } 1678 1679 mlx5_fwdump_prep(dev); 1680 1681 mlx5_firmware_update(dev); 1682 1683 #ifdef PCI_IOV 1684 if (MLX5_CAP_GEN(dev, vport_group_manager)) { 1685 if (pci_find_extcap(bsddev, PCIZ_SRIOV, &sriov_pos) == 0) { 1686 num_vfs = pci_read_config(bsddev, sriov_pos + 1687 PCIR_SRIOV_TOTAL_VFS, 2); 1688 } else { 1689 mlx5_core_info(dev, "cannot find SR-IOV PCIe cap\n"); 1690 num_vfs = 0; 1691 } 1692 err = mlx5_eswitch_init(dev, 1 + num_vfs); 1693 if (err == 0) { 1694 pf_schema = pci_iov_schema_alloc_node(); 1695 vf_schema = pci_iov_schema_alloc_node(); 1696 pci_iov_schema_add_unicast_mac(vf_schema, 1697 iov_mac_addr_name, 0, NULL); 1698 pci_iov_schema_add_uint64(vf_schema, iov_node_guid_name, 1699 0, 0); 1700 pci_iov_schema_add_uint64(vf_schema, iov_port_guid_name, 1701 0, 0); 1702 err = pci_iov_attach(bsddev, pf_schema, vf_schema); 1703 if (err != 0) { 1704 device_printf(bsddev, 1705 "Failed to initialize SR-IOV support, error %d\n", 1706 err); 1707 } 1708 } else { 1709 mlx5_core_err(dev, "eswitch init failed, error %d\n", 1710 err); 1711 } 1712 } 1713 #endif 1714 1715 pci_save_state(pdev); 1716 return 0; 1717 1718 clean_health: 1719 mlx5_pagealloc_cleanup(dev); 1720 mlx5_health_cleanup(dev); 1721 close_pci: 1722 mlx5_pci_close(dev, priv); 1723 clean_dev: 1724 mtx_destroy(&dev->dump_lock); 1725 clean_sysctl_ctx: 1726 sysctl_ctx_free(&dev->sysctl_ctx); 1727 kfree(dev); 1728 return err; 1729 } 1730 1731 static void remove_one(struct pci_dev *pdev) 1732 { 1733 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1734 struct mlx5_priv *priv = &dev->priv; 1735 1736 #ifdef PCI_IOV 1737 pci_iov_detach(pdev->dev.bsddev); 1738 mlx5_eswitch_disable_sriov(priv->eswitch); 1739 #endif 1740 1741 if (mlx5_unload_one(dev, priv, true)) { 1742 mlx5_core_err(dev, "mlx5_unload_one() failed, leaked %lld bytes\n", 1743 (long long)(dev->priv.fw_pages * MLX5_ADAPTER_PAGE_SIZE)); 1744 } 1745 1746 mlx5_pagealloc_cleanup(dev); 1747 mlx5_health_cleanup(dev); 1748 mlx5_fwdump_clean(dev); 1749 mlx5_pci_close(dev, priv); 1750 mtx_destroy(&dev->dump_lock); 1751 pci_set_drvdata(pdev, NULL); 1752 sysctl_ctx_free(&dev->sysctl_ctx); 1753 kfree(dev); 1754 } 1755 1756 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1757 pci_channel_state_t state) 1758 { 1759 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1760 struct mlx5_priv *priv = &dev->priv; 1761 1762 mlx5_core_info(dev, "%s was called\n", __func__); 1763 mlx5_enter_error_state(dev, false); 1764 mlx5_unload_one(dev, priv, false); 1765 1766 if (state) { 1767 mlx5_drain_health_wq(dev); 1768 mlx5_pci_disable_device(dev); 1769 } 1770 1771 return state == pci_channel_io_perm_failure ? 1772 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1773 } 1774 1775 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1776 { 1777 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1778 int err = 0; 1779 1780 mlx5_core_info(dev,"%s was called\n", __func__); 1781 1782 err = mlx5_pci_enable_device(dev); 1783 if (err) { 1784 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n" 1785 ,err); 1786 return PCI_ERS_RESULT_DISCONNECT; 1787 } 1788 pci_set_master(pdev); 1789 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1790 pci_restore_state(pdev); 1791 pci_save_state(pdev); 1792 1793 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1794 } 1795 1796 /* wait for the device to show vital signs. For now we check 1797 * that we can read the device ID and that the health buffer 1798 * shows a non zero value which is different than 0xffffffff 1799 */ 1800 static void wait_vital(struct pci_dev *pdev) 1801 { 1802 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1803 struct mlx5_core_health *health = &dev->priv.health; 1804 const int niter = 100; 1805 u32 count; 1806 u16 did; 1807 int i; 1808 1809 /* Wait for firmware to be ready after reset */ 1810 msleep(1000); 1811 for (i = 0; i < niter; i++) { 1812 if (pci_read_config_word(pdev, 2, &did)) { 1813 mlx5_core_warn(dev, "failed reading config word\n"); 1814 break; 1815 } 1816 if (did == pdev->device) { 1817 mlx5_core_info(dev, 1818 "device ID correctly read after %d iterations\n", i); 1819 break; 1820 } 1821 msleep(50); 1822 } 1823 if (i == niter) 1824 mlx5_core_warn(dev, "could not read device ID\n"); 1825 1826 for (i = 0; i < niter; i++) { 1827 count = ioread32be(health->health_counter); 1828 if (count && count != 0xffffffff) { 1829 mlx5_core_info(dev, 1830 "Counter value 0x%x after %d iterations\n", count, i); 1831 break; 1832 } 1833 msleep(50); 1834 } 1835 1836 if (i == niter) 1837 mlx5_core_warn(dev, "could not read device ID\n"); 1838 } 1839 1840 static void mlx5_pci_resume(struct pci_dev *pdev) 1841 { 1842 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1843 struct mlx5_priv *priv = &dev->priv; 1844 int err; 1845 1846 mlx5_core_info(dev,"%s was called\n", __func__); 1847 1848 wait_vital(pdev); 1849 1850 err = mlx5_load_one(dev, priv, false); 1851 if (err) 1852 mlx5_core_err(dev, 1853 "mlx5_load_one failed with error code: %d\n" ,err); 1854 else 1855 mlx5_core_info(dev,"device recovered\n"); 1856 } 1857 1858 static const struct pci_error_handlers mlx5_err_handler = { 1859 .error_detected = mlx5_pci_err_detected, 1860 .slot_reset = mlx5_pci_slot_reset, 1861 .resume = mlx5_pci_resume 1862 }; 1863 1864 #ifdef PCI_IOV 1865 static int 1866 mlx5_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *pf_config) 1867 { 1868 struct pci_dev *pdev; 1869 struct mlx5_core_dev *core_dev; 1870 struct mlx5_priv *priv; 1871 int err; 1872 1873 pdev = device_get_softc(dev); 1874 core_dev = pci_get_drvdata(pdev); 1875 priv = &core_dev->priv; 1876 1877 if (priv->eswitch == NULL) 1878 return (ENXIO); 1879 if (priv->eswitch->total_vports < num_vfs + 1) 1880 num_vfs = priv->eswitch->total_vports - 1; 1881 err = mlx5_eswitch_enable_sriov(priv->eswitch, num_vfs); 1882 return (-err); 1883 } 1884 1885 static void 1886 mlx5_iov_uninit(device_t dev) 1887 { 1888 struct pci_dev *pdev; 1889 struct mlx5_core_dev *core_dev; 1890 struct mlx5_priv *priv; 1891 1892 pdev = device_get_softc(dev); 1893 core_dev = pci_get_drvdata(pdev); 1894 priv = &core_dev->priv; 1895 1896 mlx5_eswitch_disable_sriov(priv->eswitch); 1897 } 1898 1899 static int 1900 mlx5_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *vf_config) 1901 { 1902 struct pci_dev *pdev; 1903 struct mlx5_core_dev *core_dev; 1904 struct mlx5_priv *priv; 1905 const void *mac; 1906 size_t mac_size; 1907 uint64_t node_guid, port_guid; 1908 int error; 1909 1910 pdev = device_get_softc(dev); 1911 core_dev = pci_get_drvdata(pdev); 1912 priv = &core_dev->priv; 1913 1914 if (vfnum + 1 >= priv->eswitch->total_vports) 1915 return (ENXIO); 1916 1917 if (nvlist_exists_binary(vf_config, iov_mac_addr_name)) { 1918 mac = nvlist_get_binary(vf_config, iov_mac_addr_name, 1919 &mac_size); 1920 error = -mlx5_eswitch_set_vport_mac(priv->eswitch, 1921 vfnum + 1, __DECONST(u8 *, mac)); 1922 if (error != 0) { 1923 mlx5_core_err(core_dev, 1924 "setting MAC for VF %d failed, error %d\n", 1925 vfnum + 1, error); 1926 } 1927 } 1928 1929 if (nvlist_exists_number(vf_config, iov_node_guid_name)) { 1930 node_guid = nvlist_get_number(vf_config, iov_node_guid_name); 1931 error = -mlx5_modify_nic_vport_node_guid(core_dev, vfnum + 1, 1932 node_guid); 1933 if (error != 0) { 1934 mlx5_core_err(core_dev, 1935 "modifying node GUID for VF %d failed, error %d\n", 1936 vfnum + 1, error); 1937 } 1938 } 1939 1940 if (nvlist_exists_number(vf_config, iov_port_guid_name)) { 1941 port_guid = nvlist_get_number(vf_config, iov_port_guid_name); 1942 error = -mlx5_modify_nic_vport_port_guid(core_dev, vfnum + 1, 1943 port_guid); 1944 if (error != 0) { 1945 mlx5_core_err(core_dev, 1946 "modifying port GUID for VF %d failed, error %d\n", 1947 vfnum + 1, error); 1948 } 1949 } 1950 1951 error = -mlx5_eswitch_set_vport_state(priv->eswitch, vfnum + 1, 1952 VPORT_STATE_FOLLOW); 1953 if (error != 0) { 1954 mlx5_core_err(core_dev, 1955 "upping vport for VF %d failed, error %d\n", 1956 vfnum + 1, error); 1957 } 1958 error = -mlx5_core_enable_hca(core_dev, vfnum + 1); 1959 if (error != 0) { 1960 mlx5_core_err(core_dev, "enabling VF %d failed, error %d\n", 1961 vfnum + 1, error); 1962 } 1963 return (error); 1964 } 1965 #endif 1966 1967 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1968 { 1969 bool fast_teardown, force_teardown; 1970 int err; 1971 1972 if (!mlx5_fast_unload_enabled) { 1973 mlx5_core_dbg(dev, "fast unload is disabled by user\n"); 1974 return -EOPNOTSUPP; 1975 } 1976 1977 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1978 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1979 1980 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1981 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1982 1983 if (!fast_teardown && !force_teardown) 1984 return -EOPNOTSUPP; 1985 1986 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1987 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1988 return -EAGAIN; 1989 } 1990 1991 /* Panic tear down fw command will stop the PCI bus communication 1992 * with the HCA, so the health polll is no longer needed. 1993 */ 1994 mlx5_drain_health_wq(dev); 1995 mlx5_stop_health_poll(dev, false); 1996 1997 err = mlx5_cmd_fast_teardown_hca(dev); 1998 if (!err) 1999 goto done; 2000 2001 err = mlx5_cmd_force_teardown_hca(dev); 2002 if (!err) 2003 goto done; 2004 2005 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 2006 mlx5_start_health_poll(dev); 2007 return err; 2008 done: 2009 mlx5_enter_error_state(dev, true); 2010 return 0; 2011 } 2012 2013 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev) 2014 { 2015 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 2016 int x; 2017 2018 mdev->priv.disable_irqs = 1; 2019 2020 /* wait for all IRQ handlers to finish processing */ 2021 for (x = 0; x != nvec; x++) 2022 synchronize_irq(mdev->priv.msix_arr[x].vector); 2023 } 2024 2025 static void shutdown_one(struct pci_dev *pdev) 2026 { 2027 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 2028 struct mlx5_priv *priv = &dev->priv; 2029 int err; 2030 2031 /* enter polling mode */ 2032 mlx5_cmd_use_polling(dev); 2033 2034 set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state); 2035 2036 /* disable all interrupts */ 2037 mlx5_shutdown_disable_interrupts(dev); 2038 2039 err = mlx5_try_fast_unload(dev); 2040 if (err) 2041 mlx5_unload_one(dev, priv, false); 2042 mlx5_pci_disable_device(dev); 2043 } 2044 2045 static const struct pci_device_id mlx5_core_pci_table[] = { 2046 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 2047 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 2048 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 2049 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 2050 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 2051 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 2052 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5, PCIe 3.0 */ 2053 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 2054 { PCI_VDEVICE(MELLANOX, 4121) }, /* ConnectX-5 Ex */ 2055 { PCI_VDEVICE(MELLANOX, 4122) }, /* ConnectX-5 Ex VF */ 2056 { PCI_VDEVICE(MELLANOX, 4123) }, /* ConnectX-6 */ 2057 { PCI_VDEVICE(MELLANOX, 4124) }, /* ConnectX-6 VF */ 2058 { PCI_VDEVICE(MELLANOX, 4125) }, /* ConnectX-6 Dx */ 2059 { PCI_VDEVICE(MELLANOX, 4126) }, /* ConnectX Family mlx5Gen Virtual Function */ 2060 { PCI_VDEVICE(MELLANOX, 4127) }, /* ConnectX-6 LX */ 2061 { PCI_VDEVICE(MELLANOX, 4128) }, 2062 { PCI_VDEVICE(MELLANOX, 4129) }, /* ConnectX-7 */ 2063 { PCI_VDEVICE(MELLANOX, 4130) }, 2064 { PCI_VDEVICE(MELLANOX, 4131) }, /* ConnectX-8 */ 2065 { PCI_VDEVICE(MELLANOX, 4132) }, 2066 { PCI_VDEVICE(MELLANOX, 4133) }, 2067 { PCI_VDEVICE(MELLANOX, 4134) }, 2068 { PCI_VDEVICE(MELLANOX, 4135) }, 2069 { PCI_VDEVICE(MELLANOX, 4136) }, 2070 { PCI_VDEVICE(MELLANOX, 4137) }, 2071 { PCI_VDEVICE(MELLANOX, 4138) }, 2072 { PCI_VDEVICE(MELLANOX, 4139) }, 2073 { PCI_VDEVICE(MELLANOX, 4140) }, 2074 { PCI_VDEVICE(MELLANOX, 4141) }, 2075 { PCI_VDEVICE(MELLANOX, 4142) }, 2076 { PCI_VDEVICE(MELLANOX, 4143) }, 2077 { PCI_VDEVICE(MELLANOX, 4144) }, 2078 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2079 { PCI_VDEVICE(MELLANOX, 0xa2d3) }, /* BlueField integrated ConnectX-5 network controller VF */ 2080 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2081 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */ 2082 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 integrated ConnectX-8 network controller */ 2083 { } 2084 }; 2085 2086 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2087 2088 void mlx5_disable_device(struct mlx5_core_dev *dev) 2089 { 2090 mlx5_pci_err_detected(dev->pdev, 0); 2091 } 2092 2093 void mlx5_recover_device(struct mlx5_core_dev *dev) 2094 { 2095 mlx5_pci_disable_device(dev); 2096 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 2097 mlx5_pci_resume(dev->pdev); 2098 } 2099 2100 struct pci_driver mlx5_core_driver = { 2101 .name = DRIVER_NAME, 2102 .id_table = mlx5_core_pci_table, 2103 .shutdown = shutdown_one, 2104 .probe = init_one, 2105 .remove = remove_one, 2106 .err_handler = &mlx5_err_handler, 2107 #ifdef PCI_IOV 2108 .bsd_iov_init = mlx5_iov_init, 2109 .bsd_iov_uninit = mlx5_iov_uninit, 2110 .bsd_iov_add_vf = mlx5_iov_add_vf, 2111 #endif 2112 }; 2113 2114 static int __init init(void) 2115 { 2116 int err; 2117 2118 err = pci_register_driver(&mlx5_core_driver); 2119 if (err) 2120 goto err_debug; 2121 2122 err = mlx5_ctl_init(); 2123 if (err) 2124 goto err_ctl; 2125 2126 return 0; 2127 2128 err_ctl: 2129 pci_unregister_driver(&mlx5_core_driver); 2130 2131 err_debug: 2132 return err; 2133 } 2134 2135 static void __exit cleanup(void) 2136 { 2137 mlx5_ctl_fini(); 2138 pci_unregister_driver(&mlx5_core_driver); 2139 } 2140 2141 module_init_order(init, SI_ORDER_FIRST); 2142 module_exit_order(cleanup, SI_ORDER_FIRST); 2143