1 /*- 2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/kmod.h> 29 #include <linux/module.h> 30 #include <linux/errno.h> 31 #include <linux/pci.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/slab.h> 34 #include <linux/io-mapping.h> 35 #include <linux/interrupt.h> 36 #include <linux/hardirq.h> 37 #include <dev/mlx5/driver.h> 38 #include <dev/mlx5/cq.h> 39 #include <dev/mlx5/qp.h> 40 #include <dev/mlx5/srq.h> 41 #include <dev/mlx5/mpfs.h> 42 #include <dev/mlx5/vport.h> 43 #include <linux/delay.h> 44 #include <dev/mlx5/mlx5_ifc.h> 45 #include <dev/mlx5/mlx5_fpga/core.h> 46 #include <dev/mlx5/mlx5_lib/mlx5.h> 47 #include "mlx5_core.h" 48 #include "eswitch.h" 49 #include "fs_core.h" 50 #ifdef PCI_IOV 51 #include <sys/nv.h> 52 #include <dev/pci/pci_iov.h> 53 #include <sys/iov_schema.h> 54 #endif 55 56 static const char mlx5_version[] = "Mellanox Core driver " 57 DRIVER_VERSION " (" DRIVER_RELDATE ")"; 58 MODULE_DESCRIPTION("Mellanox ConnectX-4 and onwards core driver"); 59 MODULE_LICENSE("Dual BSD/GPL"); 60 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1); 61 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1); 62 MODULE_DEPEND(mlx5, firmware, 1, 1, 1); 63 MODULE_VERSION(mlx5, 1); 64 65 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 66 "mlx5 hardware controls"); 67 68 int mlx5_core_debug_mask; 69 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN, 70 &mlx5_core_debug_mask, 0, 71 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0"); 72 73 #define MLX5_DEFAULT_PROF 2 74 static int mlx5_prof_sel = MLX5_DEFAULT_PROF; 75 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN, 76 &mlx5_prof_sel, 0, 77 "profile selector. Valid range 0 - 2"); 78 79 static int mlx5_fast_unload_enabled = 1; 80 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN, 81 &mlx5_fast_unload_enabled, 0, 82 "Set to enable fast unload. Clear to disable."); 83 84 static LIST_HEAD(intf_list); 85 static LIST_HEAD(dev_list); 86 static DEFINE_MUTEX(intf_mutex); 87 88 struct mlx5_device_context { 89 struct list_head list; 90 struct mlx5_interface *intf; 91 void *context; 92 }; 93 94 enum { 95 MLX5_ATOMIC_REQ_MODE_BE = 0x0, 96 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1, 97 }; 98 99 static struct mlx5_profile profiles[] = { 100 [0] = { 101 .mask = 0, 102 }, 103 [1] = { 104 .mask = MLX5_PROF_MASK_QP_SIZE, 105 .log_max_qp = 12, 106 }, 107 [2] = { 108 .mask = MLX5_PROF_MASK_QP_SIZE | 109 MLX5_PROF_MASK_MR_CACHE, 110 .log_max_qp = 17, 111 .mr_cache[0] = { 112 .size = 500, 113 .limit = 250 114 }, 115 .mr_cache[1] = { 116 .size = 500, 117 .limit = 250 118 }, 119 .mr_cache[2] = { 120 .size = 500, 121 .limit = 250 122 }, 123 .mr_cache[3] = { 124 .size = 500, 125 .limit = 250 126 }, 127 .mr_cache[4] = { 128 .size = 500, 129 .limit = 250 130 }, 131 .mr_cache[5] = { 132 .size = 500, 133 .limit = 250 134 }, 135 .mr_cache[6] = { 136 .size = 500, 137 .limit = 250 138 }, 139 .mr_cache[7] = { 140 .size = 500, 141 .limit = 250 142 }, 143 .mr_cache[8] = { 144 .size = 500, 145 .limit = 250 146 }, 147 .mr_cache[9] = { 148 .size = 500, 149 .limit = 250 150 }, 151 .mr_cache[10] = { 152 .size = 500, 153 .limit = 250 154 }, 155 .mr_cache[11] = { 156 .size = 500, 157 .limit = 250 158 }, 159 .mr_cache[12] = { 160 .size = 64, 161 .limit = 32 162 }, 163 .mr_cache[13] = { 164 .size = 32, 165 .limit = 16 166 }, 167 .mr_cache[14] = { 168 .size = 16, 169 .limit = 8 170 }, 171 }, 172 [3] = { 173 .mask = MLX5_PROF_MASK_QP_SIZE, 174 .log_max_qp = 17, 175 }, 176 }; 177 178 #ifdef PCI_IOV 179 static const char iov_mac_addr_name[] = "mac-addr"; 180 static const char iov_node_guid_name[] = "node-guid"; 181 static const char iov_port_guid_name[] = "port-guid"; 182 #endif 183 184 static int set_dma_caps(struct pci_dev *pdev) 185 { 186 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 187 int err; 188 189 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 190 if (err) { 191 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n"); 192 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 193 if (err) { 194 mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n"); 195 return err; 196 } 197 } 198 199 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 200 if (err) { 201 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n"); 202 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 203 if (err) { 204 mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n"); 205 return err; 206 } 207 } 208 209 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024); 210 return err; 211 } 212 213 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev, 214 u16 *p_power, u8 *p_status) 215 { 216 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {}; 217 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {}; 218 int err; 219 220 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), 221 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0); 222 223 *p_status = MLX5_GET(mpein_reg, out, pwr_status); 224 *p_power = MLX5_GET(mpein_reg, out, pci_power); 225 return err; 226 } 227 228 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev) 229 { 230 struct pci_dev *pdev = dev->pdev; 231 int err = 0; 232 233 mutex_lock(&dev->pci_status_mutex); 234 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) { 235 err = pci_enable_device(pdev); 236 if (!err) 237 dev->pci_status = MLX5_PCI_STATUS_ENABLED; 238 } 239 mutex_unlock(&dev->pci_status_mutex); 240 241 return err; 242 } 243 244 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev) 245 { 246 struct pci_dev *pdev = dev->pdev; 247 248 mutex_lock(&dev->pci_status_mutex); 249 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) { 250 pci_disable_device(pdev); 251 dev->pci_status = MLX5_PCI_STATUS_DISABLED; 252 } 253 mutex_unlock(&dev->pci_status_mutex); 254 } 255 256 static int request_bar(struct pci_dev *pdev) 257 { 258 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 259 int err = 0; 260 261 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 262 mlx5_core_err(dev, "Missing registers BAR, aborting\n"); 263 return -ENODEV; 264 } 265 266 err = pci_request_regions(pdev, DRIVER_NAME); 267 if (err) 268 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n"); 269 270 return err; 271 } 272 273 static void release_bar(struct pci_dev *pdev) 274 { 275 pci_release_regions(pdev); 276 } 277 278 static int mlx5_enable_msix(struct mlx5_core_dev *dev) 279 { 280 struct mlx5_priv *priv = &dev->priv; 281 struct mlx5_eq_table *table = &priv->eq_table; 282 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq); 283 int limit = dev->msix_eqvec; 284 int nvec = MLX5_EQ_VEC_COMP_BASE; 285 int i; 286 287 if (limit > 0) 288 nvec += limit; 289 else 290 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus(); 291 292 if (nvec > num_eqs) 293 nvec = num_eqs; 294 if (nvec > 256) 295 nvec = 256; /* limit of firmware API */ 296 if (nvec <= MLX5_EQ_VEC_COMP_BASE) 297 return -ENOMEM; 298 299 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL); 300 301 for (i = 0; i < nvec; i++) 302 priv->msix_arr[i].entry = i; 303 304 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr, 305 MLX5_EQ_VEC_COMP_BASE + 1, nvec); 306 if (nvec < 0) 307 return nvec; 308 309 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE; 310 return 0; 311 } 312 313 static void mlx5_disable_msix(struct mlx5_core_dev *dev) 314 { 315 struct mlx5_priv *priv = &dev->priv; 316 317 pci_disable_msix(dev->pdev); 318 kfree(priv->msix_arr); 319 } 320 321 struct mlx5_reg_host_endianess { 322 u8 he; 323 u8 rsvd[15]; 324 }; 325 326 327 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos)) 328 329 enum { 330 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) | 331 MLX5_DEV_CAP_FLAG_DCT | 332 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR, 333 }; 334 335 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size) 336 { 337 switch (size) { 338 case 128: 339 return 0; 340 case 256: 341 return 1; 342 case 512: 343 return 2; 344 case 1024: 345 return 3; 346 case 2048: 347 return 4; 348 case 4096: 349 return 5; 350 default: 351 mlx5_core_warn(dev, "invalid pkey table size %d\n", size); 352 return 0; 353 } 354 } 355 356 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev, 357 enum mlx5_cap_type cap_type, 358 enum mlx5_cap_mode cap_mode) 359 { 360 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)]; 361 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out); 362 void *out, *hca_caps; 363 u16 opmod = (cap_type << 1) | (cap_mode & 0x01); 364 int err; 365 366 memset(in, 0, sizeof(in)); 367 out = kzalloc(out_sz, GFP_KERNEL); 368 369 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); 370 MLX5_SET(query_hca_cap_in, in, op_mod, opmod); 371 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz); 372 if (err) { 373 mlx5_core_warn(dev, 374 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n", 375 cap_type, cap_mode, err); 376 goto query_ex; 377 } 378 379 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability); 380 381 switch (cap_mode) { 382 case HCA_CAP_OPMOD_GET_MAX: 383 memcpy(dev->hca_caps_max[cap_type], hca_caps, 384 MLX5_UN_SZ_BYTES(hca_cap_union)); 385 break; 386 case HCA_CAP_OPMOD_GET_CUR: 387 memcpy(dev->hca_caps_cur[cap_type], hca_caps, 388 MLX5_UN_SZ_BYTES(hca_cap_union)); 389 break; 390 default: 391 mlx5_core_warn(dev, 392 "Tried to query dev cap type(%x) with wrong opmode(%x)\n", 393 cap_type, cap_mode); 394 err = -EINVAL; 395 break; 396 } 397 query_ex: 398 kfree(out); 399 return err; 400 } 401 402 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type) 403 { 404 int ret; 405 406 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR); 407 if (ret) 408 return ret; 409 410 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX); 411 } 412 413 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz) 414 { 415 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0}; 416 417 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP); 418 419 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out)); 420 } 421 422 static int handle_hca_cap(struct mlx5_core_dev *dev) 423 { 424 void *set_ctx = NULL; 425 struct mlx5_profile *prof = dev->profile; 426 int err = -ENOMEM; 427 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 428 void *set_hca_cap; 429 430 set_ctx = kzalloc(set_sz, GFP_KERNEL); 431 432 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 433 if (err) 434 goto query_ex; 435 436 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, 437 capability); 438 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL], 439 MLX5_ST_SZ_BYTES(cmd_hca_cap)); 440 441 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n", 442 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), 443 128); 444 /* we limit the size of the pkey table to 128 entries for now */ 445 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size, 446 to_fw_pkey_sz(dev, 128)); 447 448 if (prof->mask & MLX5_PROF_MASK_QP_SIZE) 449 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp, 450 prof->log_max_qp); 451 452 /* disable cmdif checksum */ 453 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0); 454 455 /* Enable 4K UAR only when HCA supports it and page size is bigger 456 * than 4K. 457 */ 458 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096) 459 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1); 460 461 /* enable drain sigerr */ 462 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1); 463 464 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12); 465 466 err = set_caps(dev, set_ctx, set_sz); 467 468 query_ex: 469 kfree(set_ctx); 470 return err; 471 } 472 473 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev) 474 { 475 void *set_ctx; 476 void *set_hca_cap; 477 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in); 478 int req_endianness; 479 int err; 480 481 if (MLX5_CAP_GEN(dev, atomic)) { 482 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 483 if (err) 484 return err; 485 } else { 486 return 0; 487 } 488 489 req_endianness = 490 MLX5_CAP_ATOMIC(dev, 491 supported_atomic_req_8B_endianess_mode_1); 492 493 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS) 494 return 0; 495 496 set_ctx = kzalloc(set_sz, GFP_KERNEL); 497 if (!set_ctx) 498 return -ENOMEM; 499 500 MLX5_SET(set_hca_cap_in, set_ctx, op_mod, 501 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1); 502 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability); 503 504 /* Set requestor to host endianness */ 505 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode, 506 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS); 507 508 err = set_caps(dev, set_ctx, set_sz); 509 510 kfree(set_ctx); 511 return err; 512 } 513 514 static int set_hca_ctrl(struct mlx5_core_dev *dev) 515 { 516 struct mlx5_reg_host_endianess he_in; 517 struct mlx5_reg_host_endianess he_out; 518 int err; 519 520 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH && 521 !MLX5_CAP_GEN(dev, roce)) 522 return 0; 523 524 memset(&he_in, 0, sizeof(he_in)); 525 he_in.he = MLX5_SET_HOST_ENDIANNESS; 526 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in), 527 &he_out, sizeof(he_out), 528 MLX5_REG_HOST_ENDIANNESS, 0, 1); 529 return err; 530 } 531 532 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id) 533 { 534 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0}; 535 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0}; 536 537 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA); 538 MLX5_SET(enable_hca_in, in, function_id, func_id); 539 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 540 } 541 542 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev) 543 { 544 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0}; 545 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0}; 546 547 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA); 548 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 549 } 550 551 static int mlx5_core_set_issi(struct mlx5_core_dev *dev) 552 { 553 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0}; 554 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0}; 555 u32 sup_issi; 556 int err; 557 558 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI); 559 560 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out)); 561 if (err) { 562 u32 syndrome; 563 u8 status; 564 565 mlx5_cmd_mbox_status(query_out, &status, &syndrome); 566 if (status == MLX5_CMD_STAT_BAD_OP_ERR) { 567 mlx5_core_dbg(dev, "Only ISSI 0 is supported\n"); 568 return 0; 569 } 570 571 mlx5_core_err(dev, "failed to query ISSI\n"); 572 return err; 573 } 574 575 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0); 576 577 if (sup_issi & (1 << 1)) { 578 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0}; 579 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0}; 580 581 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI); 582 MLX5_SET(set_issi_in, set_in, current_issi, 1); 583 584 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out)); 585 if (err) { 586 mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err); 587 return err; 588 } 589 590 dev->issi = 1; 591 592 return 0; 593 } else if (sup_issi & (1 << 0)) { 594 return 0; 595 } 596 597 return -ENOTSUPP; 598 } 599 600 601 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn) 602 { 603 struct mlx5_eq_table *table = &dev->priv.eq_table; 604 struct mlx5_eq *eq; 605 int err = -ENOENT; 606 607 spin_lock(&table->lock); 608 list_for_each_entry(eq, &table->comp_eqs_list, list) { 609 if (eq->index == vector) { 610 *eqn = eq->eqn; 611 *irqn = eq->irqn; 612 err = 0; 613 break; 614 } 615 } 616 spin_unlock(&table->lock); 617 618 return err; 619 } 620 EXPORT_SYMBOL(mlx5_vector2eqn); 621 622 static void free_comp_eqs(struct mlx5_core_dev *dev) 623 { 624 struct mlx5_eq_table *table = &dev->priv.eq_table; 625 struct mlx5_eq *eq, *n; 626 627 spin_lock(&table->lock); 628 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) { 629 list_del(&eq->list); 630 spin_unlock(&table->lock); 631 if (mlx5_destroy_unmap_eq(dev, eq)) 632 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n", 633 eq->eqn); 634 kfree(eq); 635 spin_lock(&table->lock); 636 } 637 spin_unlock(&table->lock); 638 } 639 640 static int alloc_comp_eqs(struct mlx5_core_dev *dev) 641 { 642 struct mlx5_eq_table *table = &dev->priv.eq_table; 643 struct mlx5_eq *eq; 644 int ncomp_vec; 645 int nent; 646 int err; 647 int i; 648 649 INIT_LIST_HEAD(&table->comp_eqs_list); 650 ncomp_vec = table->num_comp_vectors; 651 nent = MLX5_COMP_EQ_SIZE; 652 for (i = 0; i < ncomp_vec; i++) { 653 eq = kzalloc_node(sizeof(*eq), GFP_KERNEL, dev->priv.numa_node); 654 655 err = mlx5_create_map_eq(dev, eq, 656 i + MLX5_EQ_VEC_COMP_BASE, nent, 0); 657 if (err) { 658 kfree(eq); 659 goto clean; 660 } 661 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn); 662 eq->index = i; 663 spin_lock(&table->lock); 664 list_add_tail(&eq->list, &table->comp_eqs_list); 665 spin_unlock(&table->lock); 666 } 667 668 return 0; 669 670 clean: 671 free_comp_eqs(dev); 672 return err; 673 } 674 675 static inline int fw_initializing(struct mlx5_core_dev *dev) 676 { 677 return ioread32be(&dev->iseg->initializing) >> 31; 678 } 679 680 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili, 681 u32 warn_time_mili) 682 { 683 int warn = jiffies + msecs_to_jiffies(warn_time_mili); 684 int end = jiffies + msecs_to_jiffies(max_wait_mili); 685 int err = 0; 686 687 MPASS(max_wait_mili > warn_time_mili); 688 689 while (fw_initializing(dev) == 1) { 690 if (time_after(jiffies, end)) { 691 err = -EBUSY; 692 break; 693 } 694 if (warn_time_mili && time_after(jiffies, warn)) { 695 mlx5_core_warn(dev, 696 "Waiting for FW initialization, timeout abort in %u s\n", 697 (unsigned)(jiffies_to_msecs(end - warn) / 1000)); 698 warn = jiffies + msecs_to_jiffies(warn_time_mili); 699 } 700 msleep(FW_INIT_WAIT_MS); 701 } 702 703 if (err != 0) 704 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n", 705 ioread32be(&dev->iseg->initializing)); 706 707 return err; 708 } 709 710 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 711 { 712 struct mlx5_device_context *dev_ctx; 713 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 714 715 dev_ctx = kzalloc_node(sizeof(*dev_ctx), GFP_KERNEL, priv->numa_node); 716 if (!dev_ctx) 717 return; 718 719 dev_ctx->intf = intf; 720 CURVNET_SET_QUIET(vnet0); 721 dev_ctx->context = intf->add(dev); 722 CURVNET_RESTORE(); 723 724 if (dev_ctx->context) { 725 spin_lock_irq(&priv->ctx_lock); 726 list_add_tail(&dev_ctx->list, &priv->ctx_list); 727 spin_unlock_irq(&priv->ctx_lock); 728 } else { 729 kfree(dev_ctx); 730 } 731 } 732 733 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv) 734 { 735 struct mlx5_device_context *dev_ctx; 736 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv); 737 738 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 739 if (dev_ctx->intf == intf) { 740 spin_lock_irq(&priv->ctx_lock); 741 list_del(&dev_ctx->list); 742 spin_unlock_irq(&priv->ctx_lock); 743 744 intf->remove(dev, dev_ctx->context); 745 kfree(dev_ctx); 746 return; 747 } 748 } 749 750 int 751 mlx5_register_device(struct mlx5_core_dev *dev) 752 { 753 struct mlx5_priv *priv = &dev->priv; 754 struct mlx5_interface *intf; 755 756 mutex_lock(&intf_mutex); 757 list_add_tail(&priv->dev_list, &dev_list); 758 list_for_each_entry(intf, &intf_list, list) 759 mlx5_add_device(intf, priv); 760 mutex_unlock(&intf_mutex); 761 762 return 0; 763 } 764 765 void 766 mlx5_unregister_device(struct mlx5_core_dev *dev) 767 { 768 struct mlx5_priv *priv = &dev->priv; 769 struct mlx5_interface *intf; 770 771 mutex_lock(&intf_mutex); 772 list_for_each_entry(intf, &intf_list, list) 773 mlx5_remove_device(intf, priv); 774 list_del(&priv->dev_list); 775 mutex_unlock(&intf_mutex); 776 } 777 778 int mlx5_register_interface(struct mlx5_interface *intf) 779 { 780 struct mlx5_priv *priv; 781 782 if (!intf->add || !intf->remove) 783 return -EINVAL; 784 785 mutex_lock(&intf_mutex); 786 list_add_tail(&intf->list, &intf_list); 787 list_for_each_entry(priv, &dev_list, dev_list) 788 mlx5_add_device(intf, priv); 789 mutex_unlock(&intf_mutex); 790 791 return 0; 792 } 793 EXPORT_SYMBOL(mlx5_register_interface); 794 795 void mlx5_unregister_interface(struct mlx5_interface *intf) 796 { 797 struct mlx5_priv *priv; 798 799 mutex_lock(&intf_mutex); 800 list_for_each_entry(priv, &dev_list, dev_list) 801 mlx5_remove_device(intf, priv); 802 list_del(&intf->list); 803 mutex_unlock(&intf_mutex); 804 } 805 EXPORT_SYMBOL(mlx5_unregister_interface); 806 807 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol) 808 { 809 struct mlx5_priv *priv = &mdev->priv; 810 struct mlx5_device_context *dev_ctx; 811 unsigned long flags; 812 void *result = NULL; 813 814 spin_lock_irqsave(&priv->ctx_lock, flags); 815 816 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list) 817 if ((dev_ctx->intf->protocol == protocol) && 818 dev_ctx->intf->get_dev) { 819 result = dev_ctx->intf->get_dev(dev_ctx->context); 820 break; 821 } 822 823 spin_unlock_irqrestore(&priv->ctx_lock, flags); 824 825 return result; 826 } 827 EXPORT_SYMBOL(mlx5_get_protocol_dev); 828 829 static int mlx5_auto_fw_update; 830 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH, 831 &mlx5_auto_fw_update, 0, 832 "Allow automatic firmware update on driver start"); 833 static int 834 mlx5_firmware_update(struct mlx5_core_dev *dev) 835 { 836 const struct firmware *fw; 837 int err; 838 839 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update); 840 if (!mlx5_auto_fw_update) 841 return (0); 842 fw = firmware_get("mlx5fw_mfa"); 843 if (fw) { 844 err = mlx5_firmware_flash(dev, fw); 845 firmware_put(fw, FIRMWARE_UNLOAD); 846 } 847 else 848 return (-ENOENT); 849 850 return err; 851 } 852 853 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 854 { 855 struct pci_dev *pdev = dev->pdev; 856 device_t bsddev; 857 int err; 858 859 pdev = dev->pdev; 860 bsddev = pdev->dev.bsddev; 861 pci_set_drvdata(dev->pdev, dev); 862 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN); 863 priv->name[MLX5_MAX_NAME_LEN - 1] = 0; 864 865 mutex_init(&priv->pgdir_mutex); 866 INIT_LIST_HEAD(&priv->pgdir_list); 867 spin_lock_init(&priv->mkey_lock); 868 869 err = mlx5_pci_enable_device(dev); 870 if (err) { 871 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n"); 872 goto err_dbg; 873 } 874 875 err = request_bar(pdev); 876 if (err) { 877 mlx5_core_err(dev, "error requesting BARs, aborting\n"); 878 goto err_disable; 879 } 880 881 pci_set_master(pdev); 882 883 err = set_dma_caps(pdev); 884 if (err) { 885 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n"); 886 goto err_clr_master; 887 } 888 889 dev->iseg_base = pci_resource_start(dev->pdev, 0); 890 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg)); 891 if (!dev->iseg) { 892 err = -ENOMEM; 893 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n"); 894 goto err_clr_master; 895 } 896 897 return 0; 898 899 err_clr_master: 900 release_bar(dev->pdev); 901 err_disable: 902 mlx5_pci_disable_device(dev); 903 err_dbg: 904 return err; 905 } 906 907 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 908 { 909 #ifdef PCI_IOV 910 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) 911 pci_iov_detach(dev->pdev->dev.bsddev); 912 #endif 913 iounmap(dev->iseg); 914 release_bar(dev->pdev); 915 mlx5_pci_disable_device(dev); 916 } 917 918 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv) 919 { 920 int err; 921 922 err = mlx5_vsc_find_cap(dev); 923 if (err) 924 mlx5_core_warn(dev, "Unable to find vendor specific capabilities\n"); 925 926 err = mlx5_query_hca_caps(dev); 927 if (err) { 928 mlx5_core_err(dev, "query hca failed\n"); 929 goto out; 930 } 931 932 err = mlx5_query_board_id(dev); 933 if (err) { 934 mlx5_core_err(dev, "query board id failed\n"); 935 goto out; 936 } 937 938 err = mlx5_eq_init(dev); 939 if (err) { 940 mlx5_core_err(dev, "failed to initialize eq\n"); 941 goto out; 942 } 943 944 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock); 945 946 err = mlx5_init_cq_table(dev); 947 if (err) { 948 mlx5_core_err(dev, "failed to initialize cq table\n"); 949 goto err_eq_cleanup; 950 } 951 952 mlx5_init_qp_table(dev); 953 mlx5_init_srq_table(dev); 954 mlx5_init_mr_table(dev); 955 956 mlx5_init_reserved_gids(dev); 957 mlx5_fpga_init(dev); 958 959 #ifdef RATELIMIT 960 err = mlx5_init_rl_table(dev); 961 if (err) { 962 mlx5_core_err(dev, "Failed to init rate limiting\n"); 963 goto err_tables_cleanup; 964 } 965 #endif 966 return 0; 967 968 #ifdef RATELIMIT 969 err_tables_cleanup: 970 mlx5_cleanup_mr_table(dev); 971 mlx5_cleanup_srq_table(dev); 972 mlx5_cleanup_qp_table(dev); 973 mlx5_cleanup_cq_table(dev); 974 #endif 975 976 err_eq_cleanup: 977 mlx5_eq_cleanup(dev); 978 979 out: 980 return err; 981 } 982 983 static void mlx5_cleanup_once(struct mlx5_core_dev *dev) 984 { 985 #ifdef RATELIMIT 986 mlx5_cleanup_rl_table(dev); 987 #endif 988 mlx5_fpga_cleanup(dev); 989 mlx5_cleanup_reserved_gids(dev); 990 mlx5_cleanup_mr_table(dev); 991 mlx5_cleanup_srq_table(dev); 992 mlx5_cleanup_qp_table(dev); 993 mlx5_cleanup_cq_table(dev); 994 mlx5_eq_cleanup(dev); 995 } 996 997 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 998 bool boot) 999 { 1000 int err; 1001 1002 mutex_lock(&dev->intf_state_mutex); 1003 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1004 mlx5_core_warn(dev, "interface is up, NOP\n"); 1005 goto out; 1006 } 1007 1008 mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n", 1009 fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev)); 1010 1011 /* 1012 * On load removing any previous indication of internal error, 1013 * device is up 1014 */ 1015 dev->state = MLX5_DEVICE_STATE_UP; 1016 1017 /* wait for firmware to accept initialization segments configurations 1018 */ 1019 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI, 1020 FW_INIT_WARN_MESSAGE_INTERVAL); 1021 if (err) { 1022 dev_err(&dev->pdev->dev, 1023 "Firmware over %d MS in pre-initializing state, aborting\n", 1024 FW_PRE_INIT_TIMEOUT_MILI); 1025 goto out_err; 1026 } 1027 1028 err = mlx5_cmd_init(dev); 1029 if (err) { 1030 mlx5_core_err(dev, 1031 "Failed initializing command interface, aborting\n"); 1032 goto out_err; 1033 } 1034 1035 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0); 1036 if (err) { 1037 mlx5_core_err(dev, 1038 "Firmware over %d MS in initializing state, aborting\n", 1039 FW_INIT_TIMEOUT_MILI); 1040 goto err_cmd_cleanup; 1041 } 1042 1043 err = mlx5_core_enable_hca(dev, 0); 1044 if (err) { 1045 mlx5_core_err(dev, "enable hca failed\n"); 1046 goto err_cmd_cleanup; 1047 } 1048 1049 err = mlx5_core_set_issi(dev); 1050 if (err) { 1051 mlx5_core_err(dev, "failed to set issi\n"); 1052 goto err_disable_hca; 1053 } 1054 1055 err = mlx5_pagealloc_start(dev); 1056 if (err) { 1057 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n"); 1058 goto err_disable_hca; 1059 } 1060 1061 err = mlx5_satisfy_startup_pages(dev, 1); 1062 if (err) { 1063 mlx5_core_err(dev, "failed to allocate boot pages\n"); 1064 goto err_pagealloc_stop; 1065 } 1066 1067 err = set_hca_ctrl(dev); 1068 if (err) { 1069 mlx5_core_err(dev, "set_hca_ctrl failed\n"); 1070 goto reclaim_boot_pages; 1071 } 1072 1073 err = handle_hca_cap(dev); 1074 if (err) { 1075 mlx5_core_err(dev, "handle_hca_cap failed\n"); 1076 goto reclaim_boot_pages; 1077 } 1078 1079 err = handle_hca_cap_atomic(dev); 1080 if (err) { 1081 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n"); 1082 goto reclaim_boot_pages; 1083 } 1084 1085 err = mlx5_satisfy_startup_pages(dev, 0); 1086 if (err) { 1087 mlx5_core_err(dev, "failed to allocate init pages\n"); 1088 goto reclaim_boot_pages; 1089 } 1090 1091 err = mlx5_cmd_init_hca(dev); 1092 if (err) { 1093 mlx5_core_err(dev, "init hca failed\n"); 1094 goto reclaim_boot_pages; 1095 } 1096 1097 mlx5_start_health_poll(dev); 1098 1099 if (boot && (err = mlx5_init_once(dev, priv))) { 1100 mlx5_core_err(dev, "sw objs init failed\n"); 1101 goto err_stop_poll; 1102 } 1103 1104 dev->priv.uar = mlx5_get_uars_page(dev); 1105 if (IS_ERR(dev->priv.uar)) { 1106 mlx5_core_err(dev, "Failed allocating uar, aborting\n"); 1107 err = PTR_ERR(dev->priv.uar); 1108 goto err_cleanup_once; 1109 } 1110 1111 err = mlx5_enable_msix(dev); 1112 if (err) { 1113 mlx5_core_err(dev, "enable msix failed\n"); 1114 goto err_cleanup_uar; 1115 } 1116 1117 err = mlx5_start_eqs(dev); 1118 if (err) { 1119 mlx5_core_err(dev, "Failed to start pages and async EQs\n"); 1120 goto err_disable_msix; 1121 } 1122 1123 err = alloc_comp_eqs(dev); 1124 if (err) { 1125 mlx5_core_err(dev, "Failed to alloc completion EQs\n"); 1126 goto err_stop_eqs; 1127 } 1128 1129 err = mlx5_init_fs(dev); 1130 if (err) { 1131 mlx5_core_err(dev, "flow steering init %d\n", err); 1132 goto err_free_comp_eqs; 1133 } 1134 1135 err = mlx5_mpfs_init(dev); 1136 if (err) { 1137 mlx5_core_err(dev, "mpfs init failed %d\n", err); 1138 goto err_fs; 1139 } 1140 1141 err = mlx5_fpga_device_start(dev); 1142 if (err) { 1143 mlx5_core_err(dev, "fpga device start failed %d\n", err); 1144 goto err_mpfs; 1145 } 1146 1147 err = mlx5_register_device(dev); 1148 if (err) { 1149 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err); 1150 goto err_fpga; 1151 } 1152 1153 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1154 1155 out: 1156 mutex_unlock(&dev->intf_state_mutex); 1157 return 0; 1158 1159 err_fpga: 1160 mlx5_fpga_device_stop(dev); 1161 1162 err_mpfs: 1163 mlx5_mpfs_destroy(dev); 1164 1165 err_fs: 1166 mlx5_cleanup_fs(dev); 1167 1168 err_free_comp_eqs: 1169 free_comp_eqs(dev); 1170 1171 err_stop_eqs: 1172 mlx5_stop_eqs(dev); 1173 1174 err_disable_msix: 1175 mlx5_disable_msix(dev); 1176 1177 err_cleanup_uar: 1178 mlx5_put_uars_page(dev, dev->priv.uar); 1179 1180 err_cleanup_once: 1181 if (boot) 1182 mlx5_cleanup_once(dev); 1183 1184 err_stop_poll: 1185 mlx5_stop_health_poll(dev, boot); 1186 if (mlx5_cmd_teardown_hca(dev)) { 1187 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1188 goto out_err; 1189 } 1190 1191 reclaim_boot_pages: 1192 mlx5_reclaim_startup_pages(dev); 1193 1194 err_pagealloc_stop: 1195 mlx5_pagealloc_stop(dev); 1196 1197 err_disable_hca: 1198 mlx5_core_disable_hca(dev); 1199 1200 err_cmd_cleanup: 1201 mlx5_cmd_cleanup(dev); 1202 1203 out_err: 1204 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; 1205 mutex_unlock(&dev->intf_state_mutex); 1206 1207 return err; 1208 } 1209 1210 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv, 1211 bool cleanup) 1212 { 1213 int err = 0; 1214 1215 if (cleanup) 1216 mlx5_drain_health_recovery(dev); 1217 1218 mutex_lock(&dev->intf_state_mutex); 1219 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) { 1220 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__); 1221 if (cleanup) 1222 mlx5_cleanup_once(dev); 1223 goto out; 1224 } 1225 1226 mlx5_unregister_device(dev); 1227 1228 mlx5_eswitch_cleanup(dev->priv.eswitch); 1229 mlx5_fpga_device_stop(dev); 1230 mlx5_mpfs_destroy(dev); 1231 mlx5_cleanup_fs(dev); 1232 mlx5_wait_for_reclaim_vfs_pages(dev); 1233 free_comp_eqs(dev); 1234 mlx5_stop_eqs(dev); 1235 mlx5_disable_msix(dev); 1236 mlx5_put_uars_page(dev, dev->priv.uar); 1237 if (cleanup) 1238 mlx5_cleanup_once(dev); 1239 mlx5_stop_health_poll(dev, cleanup); 1240 err = mlx5_cmd_teardown_hca(dev); 1241 if (err) { 1242 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n"); 1243 goto out; 1244 } 1245 mlx5_pagealloc_stop(dev); 1246 mlx5_reclaim_startup_pages(dev); 1247 mlx5_core_disable_hca(dev); 1248 mlx5_cmd_cleanup(dev); 1249 1250 out: 1251 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state); 1252 mutex_unlock(&dev->intf_state_mutex); 1253 return err; 1254 } 1255 1256 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event, 1257 unsigned long param) 1258 { 1259 struct mlx5_priv *priv = &dev->priv; 1260 struct mlx5_device_context *dev_ctx; 1261 unsigned long flags; 1262 1263 spin_lock_irqsave(&priv->ctx_lock, flags); 1264 1265 list_for_each_entry(dev_ctx, &priv->ctx_list, list) 1266 if (dev_ctx->intf->event) 1267 dev_ctx->intf->event(dev, dev_ctx->context, event, param); 1268 1269 spin_unlock_irqrestore(&priv->ctx_lock, flags); 1270 } 1271 1272 struct mlx5_core_event_handler { 1273 void (*event)(struct mlx5_core_dev *dev, 1274 enum mlx5_dev_event event, 1275 void *data); 1276 }; 1277 1278 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e, 1279 1280 #define MLX5_PORT_MODULE_ERROR_STATS(m) \ 1281 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \ 1282 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \ 1283 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \ 1284 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \ 1285 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \ 1286 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \ 1287 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \ 1288 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") \ 1289 m(+1, u64, pmd_type_not_enabled, "pmd_type_not_enabled", "PMD type is not enabled") \ 1290 m(+1, u64, laster_tec_failure, "laster_tec_failure", "Laster TEC failure") \ 1291 m(+1, u64, high_current, "high_current", "High current") \ 1292 m(+1, u64, high_voltage, "high_voltage", "High voltage") \ 1293 m(+1, u64, pcie_sys_power_slot_exceeded, "pcie_sys_power_slot_exceeded", "PCIe system power slot Exceeded") \ 1294 m(+1, u64, high_power, "high_power", "High power") \ 1295 m(+1, u64, module_state_machine_fault, "module_state_machine_fault", "Module State Machine fault") 1296 1297 static const char *mlx5_pme_err_desc[] = { 1298 MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC) 1299 }; 1300 1301 static int init_one(struct pci_dev *pdev, 1302 const struct pci_device_id *id) 1303 { 1304 struct mlx5_core_dev *dev; 1305 struct mlx5_priv *priv; 1306 device_t bsddev = pdev->dev.bsddev; 1307 #ifdef PCI_IOV 1308 nvlist_t *pf_schema, *vf_schema; 1309 int num_vfs, sriov_pos; 1310 #endif 1311 int i,err; 1312 int numa_node; 1313 struct sysctl_oid *pme_sysctl_node; 1314 struct sysctl_oid *pme_err_sysctl_node; 1315 struct sysctl_oid *cap_sysctl_node; 1316 struct sysctl_oid *current_cap_sysctl_node; 1317 struct sysctl_oid *max_cap_sysctl_node; 1318 1319 printk_once("mlx5: %s", mlx5_version); 1320 1321 numa_node = dev_to_node(&pdev->dev); 1322 1323 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, numa_node); 1324 1325 priv = &dev->priv; 1326 priv->numa_node = numa_node; 1327 1328 if (id) 1329 priv->pci_dev_data = id->driver_data; 1330 1331 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) { 1332 device_printf(bsddev, 1333 "WARN: selected profile out of range, selecting default (%d)\n", 1334 MLX5_DEFAULT_PROF); 1335 mlx5_prof_sel = MLX5_DEFAULT_PROF; 1336 } 1337 dev->profile = &profiles[mlx5_prof_sel]; 1338 dev->pdev = pdev; 1339 dev->event = mlx5_core_event; 1340 1341 /* Set desc */ 1342 device_set_desc(bsddev, mlx5_version); 1343 1344 sysctl_ctx_init(&dev->sysctl_ctx); 1345 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1346 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1347 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0, 1348 "Maximum number of MSIX event queue vectors, if set"); 1349 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1350 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1351 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0, 1352 "0:Invalid 1:Sufficient 2:Insufficient"); 1353 SYSCTL_ADD_INT(&dev->sysctl_ctx, 1354 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1355 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0, 1356 "Current power value in Watts"); 1357 1358 pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1359 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1360 OID_AUTO, "pme_stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1361 "Port module event statistics"); 1362 if (pme_sysctl_node == NULL) { 1363 err = -ENOMEM; 1364 goto clean_sysctl_ctx; 1365 } 1366 pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1367 SYSCTL_CHILDREN(pme_sysctl_node), 1368 OID_AUTO, "errors", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1369 "Port module event error statistics"); 1370 if (pme_err_sysctl_node == NULL) { 1371 err = -ENOMEM; 1372 goto clean_sysctl_ctx; 1373 } 1374 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1375 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1376 "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1377 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED], 1378 0, "Number of time module plugged"); 1379 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1380 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO, 1381 "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1382 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED], 1383 0, "Number of time module unplugged"); 1384 for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) { 1385 SYSCTL_ADD_U64(&dev->sysctl_ctx, 1386 SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO, 1387 mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE, 1388 &dev->priv.pme_stats.error_counters[i], 1389 0, mlx5_pme_err_desc[2 * i + 1]); 1390 } 1391 1392 cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1393 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)), 1394 OID_AUTO, "caps", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1395 "hardware capabilities raw bitstrings"); 1396 if (cap_sysctl_node == NULL) { 1397 err = -ENOMEM; 1398 goto clean_sysctl_ctx; 1399 } 1400 current_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1401 SYSCTL_CHILDREN(cap_sysctl_node), 1402 OID_AUTO, "current", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1403 ""); 1404 if (current_cap_sysctl_node == NULL) { 1405 err = -ENOMEM; 1406 goto clean_sysctl_ctx; 1407 } 1408 max_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx, 1409 SYSCTL_CHILDREN(cap_sysctl_node), 1410 OID_AUTO, "max", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, 1411 ""); 1412 if (max_cap_sysctl_node == NULL) { 1413 err = -ENOMEM; 1414 goto clean_sysctl_ctx; 1415 } 1416 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1417 SYSCTL_CHILDREN(current_cap_sysctl_node), 1418 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE, 1419 &dev->hca_caps_cur[MLX5_CAP_GENERAL], 1420 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1421 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1422 SYSCTL_CHILDREN(max_cap_sysctl_node), 1423 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE, 1424 &dev->hca_caps_max[MLX5_CAP_GENERAL], 1425 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1426 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1427 SYSCTL_CHILDREN(current_cap_sysctl_node), 1428 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE, 1429 &dev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], 1430 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1431 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1432 SYSCTL_CHILDREN(max_cap_sysctl_node), 1433 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE, 1434 &dev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], 1435 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1436 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1437 SYSCTL_CHILDREN(current_cap_sysctl_node), 1438 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE, 1439 &dev->hca_caps_cur[MLX5_CAP_ODP], 1440 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1441 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1442 SYSCTL_CHILDREN(max_cap_sysctl_node), 1443 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE, 1444 &dev->hca_caps_max[MLX5_CAP_ODP], 1445 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1446 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1447 SYSCTL_CHILDREN(current_cap_sysctl_node), 1448 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE, 1449 &dev->hca_caps_cur[MLX5_CAP_ATOMIC], 1450 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1451 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1452 SYSCTL_CHILDREN(max_cap_sysctl_node), 1453 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE, 1454 &dev->hca_caps_max[MLX5_CAP_ATOMIC], 1455 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1456 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1457 SYSCTL_CHILDREN(current_cap_sysctl_node), 1458 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE, 1459 &dev->hca_caps_cur[MLX5_CAP_ROCE], 1460 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1461 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1462 SYSCTL_CHILDREN(max_cap_sysctl_node), 1463 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE, 1464 &dev->hca_caps_max[MLX5_CAP_ROCE], 1465 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1466 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1467 SYSCTL_CHILDREN(current_cap_sysctl_node), 1468 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1469 &dev->hca_caps_cur[MLX5_CAP_IPOIB_OFFLOADS], 1470 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1471 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1472 SYSCTL_CHILDREN(max_cap_sysctl_node), 1473 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1474 &dev->hca_caps_max[MLX5_CAP_IPOIB_OFFLOADS], 1475 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1476 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1477 SYSCTL_CHILDREN(current_cap_sysctl_node), 1478 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1479 &dev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], 1480 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1481 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1482 SYSCTL_CHILDREN(max_cap_sysctl_node), 1483 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE, 1484 &dev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], 1485 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1486 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1487 SYSCTL_CHILDREN(current_cap_sysctl_node), 1488 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1489 &dev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], 1490 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1491 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1492 SYSCTL_CHILDREN(max_cap_sysctl_node), 1493 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1494 &dev->hca_caps_max[MLX5_CAP_FLOW_TABLE], 1495 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1496 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1497 SYSCTL_CHILDREN(current_cap_sysctl_node), 1498 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1499 &dev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], 1500 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1501 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1502 SYSCTL_CHILDREN(max_cap_sysctl_node), 1503 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE, 1504 &dev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], 1505 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1506 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1507 SYSCTL_CHILDREN(current_cap_sysctl_node), 1508 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE, 1509 &dev->hca_caps_cur[MLX5_CAP_ESWITCH], 1510 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1511 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1512 SYSCTL_CHILDREN(max_cap_sysctl_node), 1513 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE, 1514 &dev->hca_caps_max[MLX5_CAP_ESWITCH], 1515 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1516 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1517 SYSCTL_CHILDREN(current_cap_sysctl_node), 1518 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE, 1519 &dev->hca_caps_cur[MLX5_CAP_SNAPSHOT], 1520 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1521 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1522 SYSCTL_CHILDREN(max_cap_sysctl_node), 1523 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE, 1524 &dev->hca_caps_max[MLX5_CAP_SNAPSHOT], 1525 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1526 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1527 SYSCTL_CHILDREN(current_cap_sysctl_node), 1528 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE, 1529 &dev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], 1530 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1531 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1532 SYSCTL_CHILDREN(max_cap_sysctl_node), 1533 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE, 1534 &dev->hca_caps_max[MLX5_CAP_VECTOR_CALC], 1535 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1536 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1537 SYSCTL_CHILDREN(current_cap_sysctl_node), 1538 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE, 1539 &dev->hca_caps_cur[MLX5_CAP_QOS], 1540 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1541 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1542 SYSCTL_CHILDREN(max_cap_sysctl_node), 1543 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE, 1544 &dev->hca_caps_max[MLX5_CAP_QOS], 1545 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1546 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1547 SYSCTL_CHILDREN(current_cap_sysctl_node), 1548 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1549 &dev->hca_caps_cur[MLX5_CAP_DEBUG], 1550 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1551 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1552 SYSCTL_CHILDREN(max_cap_sysctl_node), 1553 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE, 1554 &dev->hca_caps_max[MLX5_CAP_DEBUG], 1555 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", ""); 1556 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1557 SYSCTL_CHILDREN(cap_sysctl_node), 1558 OID_AUTO, "pcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1559 &dev->caps.pcam, sizeof(dev->caps.pcam), "IU", ""); 1560 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1561 SYSCTL_CHILDREN(cap_sysctl_node), 1562 OID_AUTO, "mcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1563 &dev->caps.mcam, sizeof(dev->caps.mcam), "IU", ""); 1564 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1565 SYSCTL_CHILDREN(cap_sysctl_node), 1566 OID_AUTO, "qcam", CTLFLAG_RD | CTLFLAG_MPSAFE, 1567 &dev->caps.qcam, sizeof(dev->caps.qcam), "IU", ""); 1568 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx, 1569 SYSCTL_CHILDREN(cap_sysctl_node), 1570 OID_AUTO, "fpga", CTLFLAG_RD | CTLFLAG_MPSAFE, 1571 &dev->caps.fpga, sizeof(dev->caps.fpga), "IU", ""); 1572 1573 INIT_LIST_HEAD(&priv->ctx_list); 1574 spin_lock_init(&priv->ctx_lock); 1575 mutex_init(&dev->pci_status_mutex); 1576 mutex_init(&dev->intf_state_mutex); 1577 1578 mutex_init(&priv->bfregs.reg_head.lock); 1579 mutex_init(&priv->bfregs.wc_head.lock); 1580 INIT_LIST_HEAD(&priv->bfregs.reg_head.list); 1581 INIT_LIST_HEAD(&priv->bfregs.wc_head.list); 1582 1583 mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW); 1584 err = mlx5_pci_init(dev, priv); 1585 if (err) { 1586 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err); 1587 goto clean_dev; 1588 } 1589 1590 err = mlx5_health_init(dev); 1591 if (err) { 1592 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err); 1593 goto close_pci; 1594 } 1595 1596 mlx5_pagealloc_init(dev); 1597 1598 err = mlx5_load_one(dev, priv, true); 1599 if (err) { 1600 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err); 1601 goto clean_health; 1602 } 1603 1604 mlx5_fwdump_prep(dev); 1605 1606 mlx5_firmware_update(dev); 1607 1608 #ifdef PCI_IOV 1609 if (MLX5_CAP_GEN(dev, vport_group_manager)) { 1610 if (pci_find_extcap(bsddev, PCIZ_SRIOV, &sriov_pos) == 0) { 1611 num_vfs = pci_read_config(bsddev, sriov_pos + 1612 PCIR_SRIOV_TOTAL_VFS, 2); 1613 } else { 1614 mlx5_core_info(dev, "cannot find SR-IOV PCIe cap\n"); 1615 num_vfs = 0; 1616 } 1617 err = mlx5_eswitch_init(dev, 1 + num_vfs); 1618 if (err == 0) { 1619 pf_schema = pci_iov_schema_alloc_node(); 1620 vf_schema = pci_iov_schema_alloc_node(); 1621 pci_iov_schema_add_unicast_mac(vf_schema, 1622 iov_mac_addr_name, 0, NULL); 1623 pci_iov_schema_add_uint64(vf_schema, iov_node_guid_name, 1624 0, 0); 1625 pci_iov_schema_add_uint64(vf_schema, iov_port_guid_name, 1626 0, 0); 1627 err = pci_iov_attach(bsddev, pf_schema, vf_schema); 1628 if (err != 0) { 1629 device_printf(bsddev, 1630 "Failed to initialize SR-IOV support, error %d\n", 1631 err); 1632 } 1633 } else { 1634 mlx5_core_err(dev, "eswitch init failed, error %d\n", 1635 err); 1636 } 1637 } 1638 #endif 1639 1640 pci_save_state(pdev); 1641 return 0; 1642 1643 clean_health: 1644 mlx5_pagealloc_cleanup(dev); 1645 mlx5_health_cleanup(dev); 1646 close_pci: 1647 mlx5_pci_close(dev, priv); 1648 clean_dev: 1649 mtx_destroy(&dev->dump_lock); 1650 clean_sysctl_ctx: 1651 sysctl_ctx_free(&dev->sysctl_ctx); 1652 kfree(dev); 1653 return err; 1654 } 1655 1656 static void remove_one(struct pci_dev *pdev) 1657 { 1658 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1659 struct mlx5_priv *priv = &dev->priv; 1660 1661 #ifdef PCI_IOV 1662 pci_iov_detach(pdev->dev.bsddev); 1663 mlx5_eswitch_disable_sriov(priv->eswitch); 1664 #endif 1665 1666 if (mlx5_unload_one(dev, priv, true)) { 1667 mlx5_core_err(dev, "mlx5_unload_one() failed, leaked %lld bytes\n", 1668 (long long)(dev->priv.fw_pages * MLX5_ADAPTER_PAGE_SIZE)); 1669 } 1670 1671 mlx5_pagealloc_cleanup(dev); 1672 mlx5_health_cleanup(dev); 1673 mlx5_fwdump_clean(dev); 1674 mlx5_pci_close(dev, priv); 1675 mtx_destroy(&dev->dump_lock); 1676 pci_set_drvdata(pdev, NULL); 1677 sysctl_ctx_free(&dev->sysctl_ctx); 1678 kfree(dev); 1679 } 1680 1681 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev, 1682 pci_channel_state_t state) 1683 { 1684 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1685 struct mlx5_priv *priv = &dev->priv; 1686 1687 mlx5_core_info(dev, "%s was called\n", __func__); 1688 mlx5_enter_error_state(dev, false); 1689 mlx5_unload_one(dev, priv, false); 1690 1691 if (state) { 1692 mlx5_drain_health_wq(dev); 1693 mlx5_pci_disable_device(dev); 1694 } 1695 1696 return state == pci_channel_io_perm_failure ? 1697 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 1698 } 1699 1700 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev) 1701 { 1702 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1703 int err = 0; 1704 1705 mlx5_core_info(dev,"%s was called\n", __func__); 1706 1707 err = mlx5_pci_enable_device(dev); 1708 if (err) { 1709 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n" 1710 ,err); 1711 return PCI_ERS_RESULT_DISCONNECT; 1712 } 1713 pci_set_master(pdev); 1714 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0); 1715 pci_restore_state(pdev); 1716 pci_save_state(pdev); 1717 1718 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; 1719 } 1720 1721 /* wait for the device to show vital signs. For now we check 1722 * that we can read the device ID and that the health buffer 1723 * shows a non zero value which is different than 0xffffffff 1724 */ 1725 static void wait_vital(struct pci_dev *pdev) 1726 { 1727 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1728 struct mlx5_core_health *health = &dev->priv.health; 1729 const int niter = 100; 1730 u32 count; 1731 u16 did; 1732 int i; 1733 1734 /* Wait for firmware to be ready after reset */ 1735 msleep(1000); 1736 for (i = 0; i < niter; i++) { 1737 if (pci_read_config_word(pdev, 2, &did)) { 1738 mlx5_core_warn(dev, "failed reading config word\n"); 1739 break; 1740 } 1741 if (did == pdev->device) { 1742 mlx5_core_info(dev, 1743 "device ID correctly read after %d iterations\n", i); 1744 break; 1745 } 1746 msleep(50); 1747 } 1748 if (i == niter) 1749 mlx5_core_warn(dev, "could not read device ID\n"); 1750 1751 for (i = 0; i < niter; i++) { 1752 count = ioread32be(health->health_counter); 1753 if (count && count != 0xffffffff) { 1754 mlx5_core_info(dev, 1755 "Counter value 0x%x after %d iterations\n", count, i); 1756 break; 1757 } 1758 msleep(50); 1759 } 1760 1761 if (i == niter) 1762 mlx5_core_warn(dev, "could not read device ID\n"); 1763 } 1764 1765 static void mlx5_pci_resume(struct pci_dev *pdev) 1766 { 1767 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1768 struct mlx5_priv *priv = &dev->priv; 1769 int err; 1770 1771 mlx5_core_info(dev,"%s was called\n", __func__); 1772 1773 wait_vital(pdev); 1774 1775 err = mlx5_load_one(dev, priv, false); 1776 if (err) 1777 mlx5_core_err(dev, 1778 "mlx5_load_one failed with error code: %d\n" ,err); 1779 else 1780 mlx5_core_info(dev,"device recovered\n"); 1781 } 1782 1783 static const struct pci_error_handlers mlx5_err_handler = { 1784 .error_detected = mlx5_pci_err_detected, 1785 .slot_reset = mlx5_pci_slot_reset, 1786 .resume = mlx5_pci_resume 1787 }; 1788 1789 #ifdef PCI_IOV 1790 static int 1791 mlx5_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *pf_config) 1792 { 1793 struct pci_dev *pdev; 1794 struct mlx5_core_dev *core_dev; 1795 struct mlx5_priv *priv; 1796 int err; 1797 1798 pdev = device_get_softc(dev); 1799 core_dev = pci_get_drvdata(pdev); 1800 priv = &core_dev->priv; 1801 1802 if (priv->eswitch == NULL) 1803 return (ENXIO); 1804 if (priv->eswitch->total_vports < num_vfs + 1) 1805 num_vfs = priv->eswitch->total_vports - 1; 1806 err = mlx5_eswitch_enable_sriov(priv->eswitch, num_vfs); 1807 return (-err); 1808 } 1809 1810 static void 1811 mlx5_iov_uninit(device_t dev) 1812 { 1813 struct pci_dev *pdev; 1814 struct mlx5_core_dev *core_dev; 1815 struct mlx5_priv *priv; 1816 1817 pdev = device_get_softc(dev); 1818 core_dev = pci_get_drvdata(pdev); 1819 priv = &core_dev->priv; 1820 1821 mlx5_eswitch_disable_sriov(priv->eswitch); 1822 } 1823 1824 static int 1825 mlx5_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *vf_config) 1826 { 1827 struct pci_dev *pdev; 1828 struct mlx5_core_dev *core_dev; 1829 struct mlx5_priv *priv; 1830 const void *mac; 1831 size_t mac_size; 1832 uint64_t node_guid, port_guid; 1833 int error; 1834 1835 pdev = device_get_softc(dev); 1836 core_dev = pci_get_drvdata(pdev); 1837 priv = &core_dev->priv; 1838 1839 if (vfnum + 1 >= priv->eswitch->total_vports) 1840 return (ENXIO); 1841 1842 if (nvlist_exists_binary(vf_config, iov_mac_addr_name)) { 1843 mac = nvlist_get_binary(vf_config, iov_mac_addr_name, 1844 &mac_size); 1845 error = -mlx5_eswitch_set_vport_mac(priv->eswitch, 1846 vfnum + 1, __DECONST(u8 *, mac)); 1847 if (error != 0) { 1848 mlx5_core_err(core_dev, 1849 "setting MAC for VF %d failed, error %d\n", 1850 vfnum + 1, error); 1851 } 1852 } 1853 1854 if (nvlist_exists_number(vf_config, iov_node_guid_name)) { 1855 node_guid = nvlist_get_number(vf_config, iov_node_guid_name); 1856 error = -mlx5_modify_nic_vport_node_guid(core_dev, vfnum + 1, 1857 node_guid); 1858 if (error != 0) { 1859 mlx5_core_err(core_dev, 1860 "modifying node GUID for VF %d failed, error %d\n", 1861 vfnum + 1, error); 1862 } 1863 } 1864 1865 if (nvlist_exists_number(vf_config, iov_port_guid_name)) { 1866 port_guid = nvlist_get_number(vf_config, iov_port_guid_name); 1867 error = -mlx5_modify_nic_vport_port_guid(core_dev, vfnum + 1, 1868 port_guid); 1869 if (error != 0) { 1870 mlx5_core_err(core_dev, 1871 "modifying port GUID for VF %d failed, error %d\n", 1872 vfnum + 1, error); 1873 } 1874 } 1875 1876 error = -mlx5_eswitch_set_vport_state(priv->eswitch, vfnum + 1, 1877 VPORT_STATE_FOLLOW); 1878 if (error != 0) { 1879 mlx5_core_err(core_dev, 1880 "upping vport for VF %d failed, error %d\n", 1881 vfnum + 1, error); 1882 } 1883 error = -mlx5_core_enable_hca(core_dev, vfnum + 1); 1884 if (error != 0) { 1885 mlx5_core_err(core_dev, "enabling VF %d failed, error %d\n", 1886 vfnum + 1, error); 1887 } 1888 return (error); 1889 } 1890 #endif 1891 1892 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev) 1893 { 1894 bool fast_teardown, force_teardown; 1895 int err; 1896 1897 if (!mlx5_fast_unload_enabled) { 1898 mlx5_core_dbg(dev, "fast unload is disabled by user\n"); 1899 return -EOPNOTSUPP; 1900 } 1901 1902 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown); 1903 force_teardown = MLX5_CAP_GEN(dev, force_teardown); 1904 1905 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown); 1906 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown); 1907 1908 if (!fast_teardown && !force_teardown) 1909 return -EOPNOTSUPP; 1910 1911 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1912 mlx5_core_dbg(dev, "Device in internal error state, giving up\n"); 1913 return -EAGAIN; 1914 } 1915 1916 /* Panic tear down fw command will stop the PCI bus communication 1917 * with the HCA, so the health polll is no longer needed. 1918 */ 1919 mlx5_drain_health_wq(dev); 1920 mlx5_stop_health_poll(dev, false); 1921 1922 err = mlx5_cmd_fast_teardown_hca(dev); 1923 if (!err) 1924 goto done; 1925 1926 err = mlx5_cmd_force_teardown_hca(dev); 1927 if (!err) 1928 goto done; 1929 1930 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err); 1931 mlx5_start_health_poll(dev); 1932 return err; 1933 done: 1934 mlx5_enter_error_state(dev, true); 1935 return 0; 1936 } 1937 1938 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev) 1939 { 1940 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE; 1941 int x; 1942 1943 mdev->priv.disable_irqs = 1; 1944 1945 /* wait for all IRQ handlers to finish processing */ 1946 for (x = 0; x != nvec; x++) 1947 synchronize_irq(mdev->priv.msix_arr[x].vector); 1948 } 1949 1950 static void shutdown_one(struct pci_dev *pdev) 1951 { 1952 struct mlx5_core_dev *dev = pci_get_drvdata(pdev); 1953 struct mlx5_priv *priv = &dev->priv; 1954 int err; 1955 1956 /* enter polling mode */ 1957 mlx5_cmd_use_polling(dev); 1958 1959 set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state); 1960 1961 /* disable all interrupts */ 1962 mlx5_shutdown_disable_interrupts(dev); 1963 1964 err = mlx5_try_fast_unload(dev); 1965 if (err) 1966 mlx5_unload_one(dev, priv, false); 1967 mlx5_pci_disable_device(dev); 1968 } 1969 1970 static const struct pci_device_id mlx5_core_pci_table[] = { 1971 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */ 1972 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */ 1973 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */ 1974 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */ 1975 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */ 1976 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */ 1977 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5, PCIe 3.0 */ 1978 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */ 1979 { PCI_VDEVICE(MELLANOX, 4121) }, /* ConnectX-5 Ex */ 1980 { PCI_VDEVICE(MELLANOX, 4122) }, /* ConnectX-5 Ex VF */ 1981 { PCI_VDEVICE(MELLANOX, 4123) }, /* ConnectX-6 */ 1982 { PCI_VDEVICE(MELLANOX, 4124) }, /* ConnectX-6 VF */ 1983 { PCI_VDEVICE(MELLANOX, 4125) }, /* ConnectX-6 Dx */ 1984 { PCI_VDEVICE(MELLANOX, 4126) }, /* ConnectX Family mlx5Gen Virtual Function */ 1985 { PCI_VDEVICE(MELLANOX, 4127) }, /* ConnectX-6 LX */ 1986 { PCI_VDEVICE(MELLANOX, 4128) }, 1987 { PCI_VDEVICE(MELLANOX, 4129) }, 1988 { PCI_VDEVICE(MELLANOX, 4130) }, 1989 { PCI_VDEVICE(MELLANOX, 4131) }, 1990 { PCI_VDEVICE(MELLANOX, 4132) }, 1991 { PCI_VDEVICE(MELLANOX, 4133) }, 1992 { PCI_VDEVICE(MELLANOX, 4134) }, 1993 { PCI_VDEVICE(MELLANOX, 4135) }, 1994 { PCI_VDEVICE(MELLANOX, 4136) }, 1995 { PCI_VDEVICE(MELLANOX, 4137) }, 1996 { PCI_VDEVICE(MELLANOX, 4138) }, 1997 { PCI_VDEVICE(MELLANOX, 4139) }, 1998 { PCI_VDEVICE(MELLANOX, 4140) }, 1999 { PCI_VDEVICE(MELLANOX, 4141) }, 2000 { PCI_VDEVICE(MELLANOX, 4142) }, 2001 { PCI_VDEVICE(MELLANOX, 4143) }, 2002 { PCI_VDEVICE(MELLANOX, 4144) }, 2003 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */ 2004 { PCI_VDEVICE(MELLANOX, 0xa2d3) }, /* BlueField integrated ConnectX-5 network controller VF */ 2005 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */ 2006 { } 2007 }; 2008 2009 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table); 2010 2011 void mlx5_disable_device(struct mlx5_core_dev *dev) 2012 { 2013 mlx5_pci_err_detected(dev->pdev, 0); 2014 } 2015 2016 void mlx5_recover_device(struct mlx5_core_dev *dev) 2017 { 2018 mlx5_pci_disable_device(dev); 2019 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED) 2020 mlx5_pci_resume(dev->pdev); 2021 } 2022 2023 struct pci_driver mlx5_core_driver = { 2024 .name = DRIVER_NAME, 2025 .id_table = mlx5_core_pci_table, 2026 .shutdown = shutdown_one, 2027 .probe = init_one, 2028 .remove = remove_one, 2029 .err_handler = &mlx5_err_handler, 2030 #ifdef PCI_IOV 2031 .bsd_iov_init = mlx5_iov_init, 2032 .bsd_iov_uninit = mlx5_iov_uninit, 2033 .bsd_iov_add_vf = mlx5_iov_add_vf, 2034 #endif 2035 }; 2036 2037 static int __init init(void) 2038 { 2039 int err; 2040 2041 err = pci_register_driver(&mlx5_core_driver); 2042 if (err) 2043 goto err_debug; 2044 2045 err = mlx5_ctl_init(); 2046 if (err) 2047 goto err_ctl; 2048 2049 return 0; 2050 2051 err_ctl: 2052 pci_unregister_driver(&mlx5_core_driver); 2053 2054 err_debug: 2055 return err; 2056 } 2057 2058 static void __exit cleanup(void) 2059 { 2060 mlx5_ctl_fini(); 2061 pci_unregister_driver(&mlx5_core_driver); 2062 } 2063 2064 module_init_order(init, SI_ORDER_FIRST); 2065 module_exit_order(cleanup, SI_ORDER_FIRST); 2066