1 /*- 2 * Copyright (c) 2013-2020, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <dev/mlx5/driver.h> 29 #include <linux/module.h> 30 #include "mlx5_core.h" 31 32 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out, 33 int outlen) 34 { 35 u32 in[MLX5_ST_SZ_DW(query_adapter_in)]; 36 int err; 37 38 memset(in, 0, sizeof(in)); 39 40 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER); 41 42 err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); 43 return err; 44 } 45 46 int mlx5_query_board_id(struct mlx5_core_dev *dev) 47 { 48 u32 *out; 49 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 50 int err; 51 52 out = kzalloc(outlen, GFP_KERNEL); 53 54 err = mlx5_cmd_query_adapter(dev, out, outlen); 55 if (err) 56 goto out_out; 57 58 memcpy(dev->board_id, 59 MLX5_ADDR_OF(query_adapter_out, out, 60 query_adapter_struct.vsd_contd_psid), 61 MLX5_FLD_SZ_BYTES(query_adapter_out, 62 query_adapter_struct.vsd_contd_psid)); 63 64 out_out: 65 kfree(out); 66 67 return err; 68 } 69 70 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id) 71 { 72 u32 *out; 73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out); 74 int err; 75 76 out = kzalloc(outlen, GFP_KERNEL); 77 78 err = mlx5_cmd_query_adapter(mdev, out, outlen); 79 if (err) 80 goto out_out; 81 82 *vendor_id = MLX5_GET(query_adapter_out, out, 83 query_adapter_struct.ieee_vendor_id); 84 85 out_out: 86 kfree(out); 87 88 return err; 89 } 90 EXPORT_SYMBOL(mlx5_core_query_vendor_id); 91 92 static int mlx5_core_query_special_contexts(struct mlx5_core_dev *dev) 93 { 94 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)]; 95 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)]; 96 int err; 97 98 memset(in, 0, sizeof(in)); 99 memset(out, 0, sizeof(out)); 100 101 MLX5_SET(query_special_contexts_in, in, opcode, 102 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS); 103 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 104 if (err) 105 return err; 106 107 dev->special_contexts.resd_lkey = MLX5_GET(query_special_contexts_out, 108 out, resd_lkey); 109 110 return err; 111 } 112 113 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev) 114 { 115 return mlx5_query_qcam_reg(dev, dev->caps.qcam, 116 MLX5_QCAM_FEATURE_ENHANCED_FEATURES, 117 MLX5_QCAM_REGS_FIRST_128); 118 } 119 120 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev) 121 { 122 return mlx5_query_pcam_reg(dev, dev->caps.pcam, 123 MLX5_PCAM_FEATURE_ENHANCED_FEATURES, 124 MLX5_PCAM_REGS_5000_TO_507F); 125 } 126 127 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev) 128 { 129 return mlx5_query_mcam_reg(dev, dev->caps.mcam, 130 MLX5_MCAM_FEATURE_ENHANCED_FEATURES, 131 MLX5_MCAM_REGS_FIRST_128); 132 } 133 134 int mlx5_query_hca_caps(struct mlx5_core_dev *dev) 135 { 136 int err; 137 138 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL); 139 if (err) 140 return err; 141 142 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { 143 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS); 144 if (err) 145 return err; 146 } 147 148 if (MLX5_CAP_GEN(dev, pg)) { 149 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP); 150 if (err) 151 return err; 152 } 153 154 if (MLX5_CAP_GEN(dev, atomic)) { 155 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC); 156 if (err) 157 return err; 158 } 159 160 if (MLX5_CAP_GEN(dev, roce)) { 161 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE); 162 if (err) 163 return err; 164 } 165 166 if ((MLX5_CAP_GEN(dev, port_type) == 167 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET && 168 MLX5_CAP_GEN(dev, nic_flow_table)) || 169 (MLX5_CAP_GEN(dev, port_type) == MLX5_CMD_HCA_CAP_PORT_TYPE_IB && 170 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads))) { 171 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE); 172 if (err) 173 return err; 174 } 175 176 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) { 177 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE); 178 if (err) 179 return err; 180 } 181 182 if (MLX5_CAP_GEN(dev, vport_group_manager)) { 183 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH); 184 if (err) 185 return err; 186 } 187 188 if (MLX5_CAP_GEN(dev, snapshot)) { 189 err = mlx5_core_get_caps(dev, MLX5_CAP_SNAPSHOT); 190 if (err) 191 return err; 192 } 193 194 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { 195 err = mlx5_core_get_caps(dev, MLX5_CAP_EOIB_OFFLOADS); 196 if (err) 197 return err; 198 } 199 200 if (MLX5_CAP_GEN(dev, debug)) { 201 err = mlx5_core_get_caps(dev, MLX5_CAP_DEBUG); 202 if (err) 203 return err; 204 } 205 206 if (MLX5_CAP_GEN(dev, qos)) { 207 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS); 208 if (err) 209 return err; 210 } 211 212 if (MLX5_CAP_GEN(dev, qcam_reg)) { 213 err = mlx5_get_qcam_reg(dev); 214 if (err) 215 return err; 216 } 217 218 if (MLX5_CAP_GEN(dev, mcam_reg)) { 219 err = mlx5_get_mcam_reg(dev); 220 if (err) 221 return err; 222 } 223 224 if (MLX5_CAP_GEN(dev, pcam_reg)) { 225 err = mlx5_get_pcam_reg(dev); 226 if (err) 227 return err; 228 } 229 230 if (MLX5_CAP_GEN(dev, tls_tx)) { 231 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS); 232 if (err) 233 return err; 234 } 235 236 if (MLX5_CAP_GEN(dev, event_cap)) { 237 err = mlx5_core_get_caps(dev, MLX5_CAP_DEV_EVENT); 238 if (err) 239 return err; 240 } 241 242 err = mlx5_core_query_special_contexts(dev); 243 if (err) 244 return err; 245 246 return 0; 247 } 248 249 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev) 250 { 251 u32 in[MLX5_ST_SZ_DW(init_hca_in)]; 252 u32 out[MLX5_ST_SZ_DW(init_hca_out)]; 253 254 memset(in, 0, sizeof(in)); 255 256 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA); 257 258 memset(out, 0, sizeof(out)); 259 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 260 } 261 262 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev) 263 { 264 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 265 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 266 267 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 268 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 269 } 270 271 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev) 272 { 273 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; 274 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; 275 int force_state; 276 int ret; 277 278 if (!MLX5_CAP_GEN(dev, force_teardown)) { 279 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n"); 280 return -EOPNOTSUPP; 281 } 282 283 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 284 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE); 285 286 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out)); 287 if (ret) 288 return ret; 289 290 force_state = MLX5_GET(teardown_hca_out, out, state); 291 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 292 mlx5_core_err(dev, "teardown with force mode failed\n"); 293 return -EIO; 294 } 295 296 return 0; 297 } 298 299 #define MLX5_FAST_TEARDOWN_WAIT_MS 3000 300 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev) 301 { 302 int end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS; 303 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {}; 304 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {}; 305 int state; 306 int ret; 307 308 if (!MLX5_CAP_GEN(dev, fast_teardown)) { 309 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n"); 310 return -EOPNOTSUPP; 311 } 312 313 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA); 314 MLX5_SET(teardown_hca_in, in, profile, 315 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN); 316 317 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); 318 if (ret) 319 return ret; 320 321 state = MLX5_GET(teardown_hca_out, out, state); 322 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) { 323 mlx5_core_warn(dev, "teardown with fast mode failed\n"); 324 return -EIO; 325 } 326 327 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED); 328 329 /* Loop until device state turns to disable */ 330 end = jiffies + msecs_to_jiffies(delay_ms); 331 do { 332 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED) 333 break; 334 335 pause("W", 1); 336 } while (!time_after(jiffies, end)); 337 338 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) { 339 mlx5_core_err(dev, "NIC IFC still %d after %ums.\n", 340 mlx5_get_nic_state(dev), delay_ms); 341 return -EIO; 342 } 343 return 0; 344 } 345 346 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 347 u64 addr) 348 { 349 u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0}; 350 u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0}; 351 __be64 be_addr; 352 void *pas; 353 354 MLX5_SET(set_dc_cnak_trace_in, in, opcode, MLX5_CMD_OP_SET_DC_CNAK_TRACE); 355 MLX5_SET(set_dc_cnak_trace_in, in, enable, enable); 356 pas = MLX5_ADDR_OF(set_dc_cnak_trace_in, in, pas); 357 be_addr = cpu_to_be64(addr); 358 memcpy(MLX5_ADDR_OF(cmd_pas, pas, pa_h), &be_addr, sizeof(be_addr)); 359 360 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out)); 361 } 362 363 enum mlxsw_reg_mcc_instruction { 364 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 365 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 366 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 367 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 368 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 369 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08, 370 }; 371 372 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev, 373 enum mlxsw_reg_mcc_instruction instr, 374 u16 component_index, u32 update_handle, 375 u32 component_size) 376 { 377 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 378 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 379 380 memset(in, 0, sizeof(in)); 381 382 MLX5_SET(mcc_reg, in, instruction, instr); 383 MLX5_SET(mcc_reg, in, component_index, component_index); 384 MLX5_SET(mcc_reg, in, update_handle, update_handle); 385 MLX5_SET(mcc_reg, in, component_size, component_size); 386 387 return mlx5_core_access_reg(dev, in, sizeof(in), out, 388 sizeof(out), MLX5_REG_MCC, 0, 1); 389 } 390 391 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev, 392 u32 *update_handle, u8 *error_code, 393 u8 *control_state) 394 { 395 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; 396 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; 397 int err; 398 399 memset(in, 0, sizeof(in)); 400 memset(out, 0, sizeof(out)); 401 MLX5_SET(mcc_reg, in, update_handle, *update_handle); 402 403 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 404 sizeof(out), MLX5_REG_MCC, 0, 0); 405 if (err) 406 goto out; 407 408 *update_handle = MLX5_GET(mcc_reg, out, update_handle); 409 *error_code = MLX5_GET(mcc_reg, out, error_code); 410 *control_state = MLX5_GET(mcc_reg, out, control_state); 411 412 out: 413 return err; 414 } 415 416 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev, 417 u32 update_handle, 418 u32 offset, u16 size, 419 u8 *data) 420 { 421 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size; 422 u32 out[MLX5_ST_SZ_DW(mcda_reg)]; 423 int i, j, dw_size = size >> 2; 424 __be32 data_element; 425 u32 *in; 426 427 in = kzalloc(in_size, GFP_KERNEL); 428 if (!in) 429 return -ENOMEM; 430 431 MLX5_SET(mcda_reg, in, update_handle, update_handle); 432 MLX5_SET(mcda_reg, in, offset, offset); 433 MLX5_SET(mcda_reg, in, size, size); 434 435 for (i = 0; i < dw_size; i++) { 436 j = i * 4; 437 data_element = htonl(*(u32 *)&data[j]); 438 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4); 439 } 440 441 err = mlx5_core_access_reg(dev, in, in_size, out, 442 sizeof(out), MLX5_REG_MCDA, 0, 1); 443 kfree(in); 444 return err; 445 } 446 447 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev, 448 u16 component_index, 449 u32 *max_component_size, 450 u8 *log_mcda_word_size, 451 u16 *mcda_max_write_size) 452 { 453 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)]; 454 int offset = MLX5_ST_SZ_DW(mcqi_reg); 455 u32 in[MLX5_ST_SZ_DW(mcqi_reg)]; 456 int err; 457 458 memset(in, 0, sizeof(in)); 459 memset(out, 0, sizeof(out)); 460 461 MLX5_SET(mcqi_reg, in, component_index, component_index); 462 MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap)); 463 464 err = mlx5_core_access_reg(dev, in, sizeof(in), out, 465 sizeof(out), MLX5_REG_MCQI, 0, 0); 466 if (err) 467 goto out; 468 469 *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size); 470 *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size); 471 *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size); 472 473 out: 474 return err; 475 } 476 477 struct mlx5_mlxfw_dev { 478 struct mlxfw_dev mlxfw_dev; 479 struct mlx5_core_dev *mlx5_core_dev; 480 }; 481 482 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev, 483 u16 component_index, u32 *p_max_size, 484 u8 *p_align_bits, u16 *p_max_write_size) 485 { 486 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 487 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 488 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 489 490 return mlx5_reg_mcqi_query(dev, component_index, p_max_size, 491 p_align_bits, p_max_write_size); 492 } 493 494 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle) 495 { 496 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 497 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 498 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 499 u8 control_state, error_code; 500 int err; 501 502 *fwhandle = 0; 503 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state); 504 if (err) 505 return err; 506 507 if (control_state != MLXFW_FSM_STATE_IDLE) 508 return -EBUSY; 509 510 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE, 511 0, *fwhandle, 0); 512 } 513 514 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 515 u16 component_index, u32 component_size) 516 { 517 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 518 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 519 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 520 521 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT, 522 component_index, fwhandle, component_size); 523 } 524 525 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 526 u8 *data, u16 size, u32 offset) 527 { 528 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 529 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 530 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 531 532 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data); 533 } 534 535 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 536 u16 component_index) 537 { 538 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 539 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 540 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 541 542 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT, 543 component_index, fwhandle, 0); 544 } 545 546 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 547 { 548 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 549 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 550 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 551 552 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0, 553 fwhandle, 0); 554 } 555 556 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle, 557 enum mlxfw_fsm_state *fsm_state, 558 enum mlxfw_fsm_state_err *fsm_state_err) 559 { 560 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 561 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 562 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 563 u8 control_state, error_code; 564 int err; 565 566 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state); 567 if (err) 568 return err; 569 570 *fsm_state = control_state; 571 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code, 572 MLXFW_FSM_STATE_ERR_MAX); 573 return 0; 574 } 575 576 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 577 { 578 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 579 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 580 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 581 582 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0); 583 } 584 585 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle) 586 { 587 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev = 588 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev); 589 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev; 590 591 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0, 592 fwhandle, 0); 593 } 594 595 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = { 596 .component_query = mlx5_component_query, 597 .fsm_lock = mlx5_fsm_lock, 598 .fsm_component_update = mlx5_fsm_component_update, 599 .fsm_block_download = mlx5_fsm_block_download, 600 .fsm_component_verify = mlx5_fsm_component_verify, 601 .fsm_activate = mlx5_fsm_activate, 602 .fsm_query_state = mlx5_fsm_query_state, 603 .fsm_cancel = mlx5_fsm_cancel, 604 .fsm_release = mlx5_fsm_release 605 }; 606 607 int mlx5_firmware_flash(struct mlx5_core_dev *dev, 608 const struct firmware *firmware) 609 { 610 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = { 611 .mlxfw_dev = { 612 .ops = &mlx5_mlxfw_dev_ops, 613 .psid = dev->board_id, 614 .psid_size = strlen(dev->board_id), 615 }, 616 .mlx5_core_dev = dev 617 }; 618 619 if (!MLX5_CAP_GEN(dev, mcam_reg) || 620 !MLX5_CAP_MCAM_REG(dev, mcqi) || 621 !MLX5_CAP_MCAM_REG(dev, mcc) || 622 !MLX5_CAP_MCAM_REG(dev, mcda)) { 623 pr_info("%s flashing isn't supported by the running FW\n", __func__); 624 return -EOPNOTSUPP; 625 } 626 627 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware); 628 } 629