1 /*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include <linux/interrupt.h> 29 #include <linux/module.h> 30 #include <dev/mlx5/driver.h> 31 #include <dev/mlx5/mlx5_ifc.h> 32 #include "mlx5_core.h" 33 34 #include "opt_rss.h" 35 36 #ifdef RSS 37 #include <net/rss_config.h> 38 #include <netinet/in_rss.h> 39 #endif 40 41 enum { 42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 43 MLX5_EQE_OWNER_INIT_VAL = 0x1, 44 }; 45 46 enum { 47 MLX5_NUM_SPARE_EQE = 0x80, 48 MLX5_NUM_ASYNC_EQE = 0x100, 49 MLX5_NUM_CMD_EQE = 32, 50 }; 51 52 enum { 53 MLX5_EQ_DOORBEL_OFFSET = 0x40, 54 }; 55 56 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 57 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 58 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 59 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 60 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 61 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 62 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 63 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 64 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 65 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 66 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 67 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 68 69 struct map_eq_in { 70 u64 mask; 71 u32 reserved; 72 u32 unmap_eqn; 73 }; 74 75 struct cre_des_eq { 76 u8 reserved[15]; 77 u8 eqn; 78 }; 79 80 /*Function prototype*/ 81 static void mlx5_port_module_event(struct mlx5_core_dev *dev, 82 struct mlx5_eqe *eqe); 83 84 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 85 { 86 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]; 87 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)]; 88 89 memset(in, 0, sizeof(in)); 90 91 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 92 MLX5_SET(destroy_eq_in, in, eq_number, eqn); 93 94 memset(out, 0, sizeof(out)); 95 return mlx5_cmd_exec_check_status(dev, in, sizeof(in), 96 out, sizeof(out)); 97 } 98 99 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 100 { 101 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 102 } 103 104 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 105 { 106 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 107 108 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 109 } 110 111 static const char *eqe_type_str(u8 type) 112 { 113 switch (type) { 114 case MLX5_EVENT_TYPE_COMP: 115 return "MLX5_EVENT_TYPE_COMP"; 116 case MLX5_EVENT_TYPE_PATH_MIG: 117 return "MLX5_EVENT_TYPE_PATH_MIG"; 118 case MLX5_EVENT_TYPE_COMM_EST: 119 return "MLX5_EVENT_TYPE_COMM_EST"; 120 case MLX5_EVENT_TYPE_SQ_DRAINED: 121 return "MLX5_EVENT_TYPE_SQ_DRAINED"; 122 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 123 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 124 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 125 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 126 case MLX5_EVENT_TYPE_CQ_ERROR: 127 return "MLX5_EVENT_TYPE_CQ_ERROR"; 128 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 129 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 130 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 131 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 132 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 133 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 134 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 135 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 136 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 137 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 138 case MLX5_EVENT_TYPE_INTERNAL_ERROR: 139 return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 140 case MLX5_EVENT_TYPE_PORT_CHANGE: 141 return "MLX5_EVENT_TYPE_PORT_CHANGE"; 142 case MLX5_EVENT_TYPE_GPIO_EVENT: 143 return "MLX5_EVENT_TYPE_GPIO_EVENT"; 144 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 145 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 146 case MLX5_EVENT_TYPE_REMOTE_CONFIG: 147 return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 148 case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 149 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 150 case MLX5_EVENT_TYPE_STALL_EVENT: 151 return "MLX5_EVENT_TYPE_STALL_EVENT"; 152 case MLX5_EVENT_TYPE_CMD: 153 return "MLX5_EVENT_TYPE_CMD"; 154 case MLX5_EVENT_TYPE_PAGE_REQUEST: 155 return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 156 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 157 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 158 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 159 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT"; 160 default: 161 return "Unrecognized event"; 162 } 163 } 164 165 static enum mlx5_dev_event port_subtype_event(u8 subtype) 166 { 167 switch (subtype) { 168 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 169 return MLX5_DEV_EVENT_PORT_DOWN; 170 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 171 return MLX5_DEV_EVENT_PORT_UP; 172 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 173 return MLX5_DEV_EVENT_PORT_INITIALIZED; 174 case MLX5_PORT_CHANGE_SUBTYPE_LID: 175 return MLX5_DEV_EVENT_LID_CHANGE; 176 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 177 return MLX5_DEV_EVENT_PKEY_CHANGE; 178 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 179 return MLX5_DEV_EVENT_GUID_CHANGE; 180 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 181 return MLX5_DEV_EVENT_CLIENT_REREG; 182 } 183 return -1; 184 } 185 186 static enum mlx5_dev_event dcbx_subevent(u8 subtype) 187 { 188 switch (subtype) { 189 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 190 return MLX5_DEV_EVENT_ERROR_STATE_DCBX; 191 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 192 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE; 193 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 194 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE; 195 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 196 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE; 197 } 198 return -1; 199 } 200 201 static void eq_update_ci(struct mlx5_eq *eq, int arm) 202 { 203 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 204 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 205 __raw_writel((__force u32) cpu_to_be32(val), addr); 206 /* We still want ordering, just not swabbing, so add a barrier */ 207 mb(); 208 } 209 210 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 211 { 212 struct mlx5_eqe *eqe; 213 int eqes_found = 0; 214 int set_ci = 0; 215 u32 cqn; 216 u32 rsn; 217 u8 port; 218 219 while ((eqe = next_eqe_sw(eq))) { 220 /* 221 * Make sure we read EQ entry contents after we've 222 * checked the ownership bit. 223 */ 224 rmb(); 225 226 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 227 eq->eqn, eqe_type_str(eqe->type)); 228 switch (eqe->type) { 229 case MLX5_EVENT_TYPE_COMP: 230 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 231 mlx5_cq_completion(dev, cqn); 232 break; 233 234 case MLX5_EVENT_TYPE_PATH_MIG: 235 case MLX5_EVENT_TYPE_COMM_EST: 236 case MLX5_EVENT_TYPE_SQ_DRAINED: 237 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 238 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 239 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 240 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 241 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 242 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 243 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 244 eqe_type_str(eqe->type), eqe->type, rsn); 245 mlx5_rsc_event(dev, rsn, eqe->type); 246 break; 247 248 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 249 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 250 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 251 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 252 eqe_type_str(eqe->type), eqe->type, rsn); 253 mlx5_srq_event(dev, rsn, eqe->type); 254 break; 255 256 case MLX5_EVENT_TYPE_CMD: 257 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector)); 258 break; 259 260 case MLX5_EVENT_TYPE_PORT_CHANGE: 261 port = (eqe->data.port.port >> 4) & 0xf; 262 switch (eqe->sub_type) { 263 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 264 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 265 case MLX5_PORT_CHANGE_SUBTYPE_LID: 266 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 267 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 268 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 269 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 270 if (dev->event) 271 dev->event(dev, port_subtype_event(eqe->sub_type), 272 (unsigned long)port); 273 break; 274 default: 275 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 276 port, eqe->sub_type); 277 } 278 break; 279 280 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT: 281 port = (eqe->data.port.port >> 4) & 0xf; 282 switch (eqe->sub_type) { 283 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX: 284 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE: 285 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE: 286 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE: 287 if (dev->event) 288 dev->event(dev, 289 dcbx_subevent(eqe->sub_type), 290 0); 291 break; 292 default: 293 mlx5_core_warn(dev, 294 "dcbx event with unrecognized subtype: port %d, sub_type %d\n", 295 port, eqe->sub_type); 296 } 297 break; 298 299 case MLX5_EVENT_TYPE_CQ_ERROR: 300 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 301 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 302 cqn, eqe->data.cq_err.syndrome); 303 mlx5_cq_event(dev, cqn, eqe->type); 304 break; 305 306 case MLX5_EVENT_TYPE_PAGE_REQUEST: 307 { 308 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 309 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 310 311 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 312 func_id, npages); 313 mlx5_core_req_pages_handler(dev, func_id, npages); 314 } 315 break; 316 317 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 318 mlx5_port_module_event(dev, eqe); 319 break; 320 321 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 322 { 323 struct mlx5_eqe_vport_change *vc_eqe = 324 &eqe->data.vport_change; 325 u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 326 327 if (dev->event) 328 dev->event(dev, 329 MLX5_DEV_EVENT_VPORT_CHANGE, 330 (unsigned long)vport_num); 331 } 332 break; 333 334 default: 335 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 336 eqe->type, eq->eqn); 337 break; 338 } 339 340 ++eq->cons_index; 341 eqes_found = 1; 342 ++set_ci; 343 344 /* The HCA will think the queue has overflowed if we 345 * don't tell it we've been processing events. We 346 * create our EQs with MLX5_NUM_SPARE_EQE extra 347 * entries, so we must update our consumer index at 348 * least that often. 349 */ 350 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 351 eq_update_ci(eq, 0); 352 set_ci = 0; 353 } 354 } 355 356 eq_update_ci(eq, 1); 357 358 return eqes_found; 359 } 360 361 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 362 { 363 struct mlx5_eq *eq = eq_ptr; 364 struct mlx5_core_dev *dev = eq->dev; 365 366 mlx5_eq_int(dev, eq); 367 368 /* MSI-X vectors always belong to us */ 369 return IRQ_HANDLED; 370 } 371 372 static void init_eq_buf(struct mlx5_eq *eq) 373 { 374 struct mlx5_eqe *eqe; 375 int i; 376 377 for (i = 0; i < eq->nent; i++) { 378 eqe = get_eqe(eq, i); 379 eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 380 } 381 } 382 383 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 384 int nent, u64 mask, const char *name, struct mlx5_uar *uar) 385 { 386 struct mlx5_priv *priv = &dev->priv; 387 struct mlx5_create_eq_mbox_in *in; 388 struct mlx5_create_eq_mbox_out out; 389 int err; 390 int inlen; 391 392 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 393 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 394 &eq->buf); 395 if (err) 396 return err; 397 398 init_eq_buf(eq); 399 400 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages; 401 in = mlx5_vzalloc(inlen); 402 if (!in) { 403 err = -ENOMEM; 404 goto err_buf; 405 } 406 memset(&out, 0, sizeof(out)); 407 408 mlx5_fill_page_array(&eq->buf, in->pas); 409 410 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ); 411 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index); 412 in->ctx.intr = vecidx; 413 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT; 414 in->events_mask = cpu_to_be64(mask); 415 416 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out)); 417 if (err) 418 goto err_in; 419 420 if (out.hdr.status) { 421 err = mlx5_cmd_status_to_err(&out.hdr); 422 goto err_in; 423 } 424 425 eq->eqn = out.eq_number; 426 eq->irqn = vecidx; 427 eq->dev = dev; 428 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 429 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 430 name, pci_name(dev->pdev)); 431 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 432 priv->irq_info[vecidx].name, eq); 433 if (err) 434 goto err_eq; 435 #ifdef RSS 436 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 437 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 438 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 439 rss_getcpu(bucket % rss_getnumbuckets())); 440 if (err) 441 goto err_irq; 442 } 443 #else 444 if (0) 445 goto err_irq; 446 #endif 447 448 449 /* EQs are created in ARMED state 450 */ 451 eq_update_ci(eq, 1); 452 453 kvfree(in); 454 return 0; 455 456 err_irq: 457 free_irq(priv->msix_arr[vecidx].vector, eq); 458 459 err_eq: 460 mlx5_cmd_destroy_eq(dev, eq->eqn); 461 462 err_in: 463 kvfree(in); 464 465 err_buf: 466 mlx5_buf_free(dev, &eq->buf); 467 return err; 468 } 469 EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 470 471 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 472 { 473 int err; 474 475 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 476 err = mlx5_cmd_destroy_eq(dev, eq->eqn); 477 if (err) 478 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 479 eq->eqn); 480 mlx5_buf_free(dev, &eq->buf); 481 482 return err; 483 } 484 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 485 486 int mlx5_eq_init(struct mlx5_core_dev *dev) 487 { 488 int err; 489 490 spin_lock_init(&dev->priv.eq_table.lock); 491 492 err = 0; 493 494 return err; 495 } 496 497 498 void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 499 { 500 } 501 502 int mlx5_start_eqs(struct mlx5_core_dev *dev) 503 { 504 struct mlx5_eq_table *table = &dev->priv.eq_table; 505 u32 async_event_mask = MLX5_ASYNC_EVENT_MASK; 506 int err; 507 508 if (MLX5_CAP_GEN(dev, port_module_event)) 509 async_event_mask |= (1ull << 510 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 511 512 if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 513 async_event_mask |= (1ull << 514 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 515 516 if (MLX5_CAP_GEN(dev, dcbx)) 517 async_event_mask |= (1ull << 518 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT); 519 520 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 521 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 522 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 523 if (err) { 524 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 525 return err; 526 } 527 528 mlx5_cmd_use_events(dev); 529 530 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 531 MLX5_NUM_ASYNC_EQE, async_event_mask, 532 "mlx5_async_eq", &dev->priv.uuari.uars[0]); 533 if (err) { 534 mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 535 goto err1; 536 } 537 538 err = mlx5_create_map_eq(dev, &table->pages_eq, 539 MLX5_EQ_VEC_PAGES, 540 /* TODO: sriov max_vf + */ 1, 541 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 542 &dev->priv.uuari.uars[0]); 543 if (err) { 544 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 545 goto err2; 546 } 547 548 return err; 549 550 err2: 551 mlx5_destroy_unmap_eq(dev, &table->async_eq); 552 553 err1: 554 mlx5_cmd_use_polling(dev); 555 mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 556 return err; 557 } 558 559 int mlx5_stop_eqs(struct mlx5_core_dev *dev) 560 { 561 struct mlx5_eq_table *table = &dev->priv.eq_table; 562 int err; 563 564 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 565 if (err) 566 return err; 567 568 mlx5_destroy_unmap_eq(dev, &table->async_eq); 569 mlx5_cmd_use_polling(dev); 570 571 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 572 if (err) 573 mlx5_cmd_use_events(dev); 574 575 return err; 576 } 577 578 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 579 struct mlx5_query_eq_mbox_out *out, int outlen) 580 { 581 struct mlx5_query_eq_mbox_in in; 582 int err; 583 584 memset(&in, 0, sizeof(in)); 585 memset(out, 0, outlen); 586 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ); 587 in.eqn = eq->eqn; 588 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen); 589 if (err) 590 return err; 591 592 if (out->hdr.status) 593 err = mlx5_cmd_status_to_err(&out->hdr); 594 595 return err; 596 } 597 598 EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 599 600 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 601 { 602 switch (error_type) { 603 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 604 return "Power Budget Exceeded"; 605 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 606 return "Long Range for non MLNX cable/module"; 607 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 608 return "Bus stuck(I2C or data shorted)"; 609 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 610 return "No EEPROM/retry timeout"; 611 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 612 return "Enforce part number list"; 613 case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER: 614 return "Unknown identifier"; 615 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 616 return "High Temperature"; 617 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED: 618 return "Cable is shorted"; 619 620 default: 621 return "Unknown error type"; 622 } 623 } 624 625 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num) 626 { 627 if (module_num < 0 || module_num >= MLX5_MAX_PORTS) 628 return 0; /* undefined */ 629 return dev->module_status[module_num]; 630 } 631 632 static void mlx5_port_module_event(struct mlx5_core_dev *dev, 633 struct mlx5_eqe *eqe) 634 { 635 unsigned int module_num; 636 unsigned int module_status; 637 unsigned int error_type; 638 struct mlx5_eqe_port_module_event *module_event_eqe; 639 struct pci_dev *pdev = dev->pdev; 640 641 module_event_eqe = &eqe->data.port_module_event; 642 643 module_num = (unsigned int)module_event_eqe->module; 644 module_status = (unsigned int)module_event_eqe->module_status & 645 PORT_MODULE_EVENT_MODULE_STATUS_MASK; 646 error_type = (unsigned int)module_event_eqe->error_type & 647 PORT_MODULE_EVENT_ERROR_TYPE_MASK; 648 649 switch (module_status) { 650 case MLX5_MODULE_STATUS_PLUGGED: 651 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged\n", module_num); 652 break; 653 654 case MLX5_MODULE_STATUS_UNPLUGGED: 655 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num); 656 break; 657 658 case MLX5_MODULE_STATUS_ERROR: 659 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 660 break; 661 662 default: 663 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num); 664 } 665 /* store module status */ 666 if (module_num < MLX5_MAX_PORTS) 667 dev->module_status[module_num] = module_status; 668 } 669 670