1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) { 215 adap->flags &= ~FW_OK; 216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 218 if (pcie_fw != 0xffffffff) 219 t4_os_dump_devlog(adap); 220 } 221 } 222 223 /* 224 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 225 */ 226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 227 u32 mbox_addr) 228 { 229 for ( ; nflit; nflit--, mbox_addr += 8) 230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 231 } 232 233 /* 234 * Handle a FW assertion reported in a mailbox. 235 */ 236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 237 { 238 CH_ALERT(adap, 239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 240 asrt->u.assert.filename_0_7, 241 be32_to_cpu(asrt->u.assert.line), 242 be32_to_cpu(asrt->u.assert.x), 243 be32_to_cpu(asrt->u.assert.y)); 244 } 245 246 struct port_tx_state { 247 uint64_t rx_pause; 248 uint64_t tx_frames; 249 }; 250 251 static void 252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 253 { 254 uint32_t rx_pause_reg, tx_frames_reg; 255 256 if (is_t4(sc)) { 257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 259 } else { 260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 262 } 263 264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 266 } 267 268 static void 269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 270 { 271 int i; 272 273 for_each_port(sc, i) 274 read_tx_state_one(sc, i, &tx_state[i]); 275 } 276 277 static void 278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 279 { 280 uint32_t port_ctl_reg; 281 uint64_t tx_frames, rx_pause; 282 int i; 283 284 for_each_port(sc, i) { 285 rx_pause = tx_state[i].rx_pause; 286 tx_frames = tx_state[i].tx_frames; 287 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 288 289 if (is_t4(sc)) 290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 291 else 292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 294 rx_pause != tx_state[i].rx_pause && 295 tx_frames == tx_state[i].tx_frames) { 296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 297 mdelay(1); 298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 299 } 300 } 301 } 302 303 #define X_CIM_PF_NOACCESS 0xeeeeeeee 304 /** 305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 306 * @adap: the adapter 307 * @mbox: index of the mailbox to use 308 * @cmd: the command to write 309 * @size: command length in bytes 310 * @rpl: where to optionally store the reply 311 * @sleep_ok: if true we may sleep while awaiting command completion 312 * @timeout: time to wait for command to finish before timing out 313 * (negative implies @sleep_ok=false) 314 * 315 * Sends the given command to FW through the selected mailbox and waits 316 * for the FW to execute the command. If @rpl is not %NULL it is used to 317 * store the FW's reply to the command. The command and its optional 318 * reply are of the same length. Some FW commands like RESET and 319 * INITIALIZE can take a considerable amount of time to execute. 320 * @sleep_ok determines whether we may sleep while awaiting the response. 321 * If sleeping is allowed we use progressive backoff otherwise we spin. 322 * Note that passing in a negative @timeout is an alternate mechanism 323 * for specifying @sleep_ok=false. This is useful when a higher level 324 * interface allows for specification of @timeout but not @sleep_ok ... 325 * 326 * The return value is 0 on success or a negative errno on failure. A 327 * failure can happen either because we are not able to execute the 328 * command or FW executes it but signals an error. In the latter case 329 * the return value is the error code indicated by FW (negated). 330 */ 331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 332 int size, void *rpl, bool sleep_ok, int timeout) 333 { 334 /* 335 * We delay in small increments at first in an effort to maintain 336 * responsiveness for simple, fast executing commands but then back 337 * off to larger delays to a maximum retry delay. 338 */ 339 static const int delay[] = { 340 1, 1, 3, 5, 10, 10, 20, 50, 100 341 }; 342 u32 v; 343 u64 res; 344 int i, ms, delay_idx, ret, next_tx_check; 345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 347 u32 ctl; 348 __be64 cmd_rpl[MBOX_LEN/8]; 349 u32 pcie_fw; 350 struct port_tx_state tx_state[MAX_NPORTS]; 351 352 if (adap->flags & CHK_MBOX_ACCESS) 353 ASSERT_SYNCHRONIZED_OP(adap); 354 355 if (size <= 0 || (size & 15) || size > MBOX_LEN) 356 return -EINVAL; 357 358 if (adap->flags & IS_VF) { 359 if (is_t6(adap)) 360 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 361 else 362 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 364 } 365 366 /* 367 * If we have a negative timeout, that implies that we can't sleep. 368 */ 369 if (timeout < 0) { 370 sleep_ok = false; 371 timeout = -timeout; 372 } 373 374 /* 375 * Attempt to gain access to the mailbox. 376 */ 377 for (i = 0; i < 4; i++) { 378 ctl = t4_read_reg(adap, ctl_reg); 379 v = G_MBOWNER(ctl); 380 if (v != X_MBOWNER_NONE) 381 break; 382 } 383 384 /* 385 * If we were unable to gain access, report the error to our caller. 386 */ 387 if (v != X_MBOWNER_PL) { 388 t4_report_fw_error(adap); 389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 390 return ret; 391 } 392 393 /* 394 * If we gain ownership of the mailbox and there's a "valid" message 395 * in it, this is likely an asynchronous error message from the 396 * firmware. So we'll report that and then proceed on with attempting 397 * to issue our own command ... which may well fail if the error 398 * presaged the firmware crashing ... 399 */ 400 if (ctl & F_MBMSGVALID) { 401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 402 } 403 404 /* 405 * Copy in the new mailbox command and send it on its way ... 406 */ 407 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 408 memcpy(cmd_rpl, cmd, size); 409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 412 413 if (adap->flags & IS_VF) { 414 /* 415 * For the VFs, the Mailbox Data "registers" are 416 * actually backed by T4's "MA" interface rather than 417 * PL Registers (as is the case for the PFs). Because 418 * these are in different coherency domains, the write 419 * to the VF's PL-register-backed Mailbox Control can 420 * race in front of the writes to the MA-backed VF 421 * Mailbox Data "registers". So we need to do a 422 * read-back on at least one byte of the VF Mailbox 423 * Data registers before doing the write to the VF 424 * Mailbox Control register. 425 */ 426 t4_read_reg(adap, data_reg); 427 } 428 429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 431 next_tx_check = 1000; 432 delay_idx = 0; 433 ms = delay[0]; 434 435 /* 436 * Loop waiting for the reply; bail out if we time out or the firmware 437 * reports an error. 438 */ 439 pcie_fw = 0; 440 for (i = 0; i < timeout; i += ms) { 441 if (!(adap->flags & IS_VF)) { 442 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 443 if (pcie_fw & F_PCIE_FW_ERR) 444 break; 445 } 446 447 if (i >= next_tx_check) { 448 check_tx_state(adap, &tx_state[0]); 449 next_tx_check = i + 1000; 450 } 451 452 if (sleep_ok) { 453 ms = delay[delay_idx]; /* last element may repeat */ 454 if (delay_idx < ARRAY_SIZE(delay) - 1) 455 delay_idx++; 456 msleep(ms); 457 } else { 458 mdelay(ms); 459 } 460 461 v = t4_read_reg(adap, ctl_reg); 462 if (v == X_CIM_PF_NOACCESS) 463 continue; 464 if (G_MBOWNER(v) == X_MBOWNER_PL) { 465 if (!(v & F_MBMSGVALID)) { 466 t4_write_reg(adap, ctl_reg, 467 V_MBOWNER(X_MBOWNER_NONE)); 468 continue; 469 } 470 471 /* 472 * Retrieve the command reply and release the mailbox. 473 */ 474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 477 478 res = be64_to_cpu(cmd_rpl[0]); 479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 481 res = V_FW_CMD_RETVAL(EIO); 482 } else if (rpl) 483 memcpy(rpl, cmd_rpl, size); 484 return -G_FW_CMD_RETVAL((int)res); 485 } 486 } 487 488 /* 489 * We timed out waiting for a reply to our mailbox command. Report 490 * the error and also check to see if the firmware reported any 491 * errors ... 492 */ 493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 494 *(const u8 *)cmd, mbox, pcie_fw); 495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 497 498 if (pcie_fw & F_PCIE_FW_ERR) { 499 ret = -ENXIO; 500 t4_report_fw_error(adap); 501 } else { 502 ret = -ETIMEDOUT; 503 t4_os_dump_devlog(adap); 504 } 505 506 t4_fatal_err(adap, true); 507 return ret; 508 } 509 510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 511 void *rpl, bool sleep_ok) 512 { 513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 514 sleep_ok, FW_CMD_MAX_TIMEOUT); 515 516 } 517 518 static int t4_edc_err_read(struct adapter *adap, int idx) 519 { 520 u32 edc_ecc_err_addr_reg; 521 u32 edc_bist_status_rdata_reg; 522 523 if (is_t4(adap)) { 524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 525 return 0; 526 } 527 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 529 return 0; 530 } 531 532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 534 535 CH_WARN(adap, 536 "edc%d err addr 0x%x: 0x%x.\n", 537 idx, edc_ecc_err_addr_reg, 538 t4_read_reg(adap, edc_ecc_err_addr_reg)); 539 CH_WARN(adap, 540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 541 edc_bist_status_rdata_reg, 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 551 552 return 0; 553 } 554 555 /** 556 * t4_mc_read - read from MC through backdoor accesses 557 * @adap: the adapter 558 * @idx: which MC to access 559 * @addr: address of first byte requested 560 * @data: 64 bytes of data containing the requested address 561 * @ecc: where to store the corresponding 64-bit ECC word 562 * 563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 564 * that covers the requested address @addr. If @parity is not %NULL it 565 * is assigned the 64-bit ECC word for the read data. 566 */ 567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 568 { 569 int i; 570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 572 573 if (is_t4(adap)) { 574 mc_bist_cmd_reg = A_MC_BIST_CMD; 575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 579 } else { 580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 584 idx); 585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 586 idx); 587 } 588 589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 590 return -EBUSY; 591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 595 F_START_BIST | V_BIST_CMD_GAP(1)); 596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 597 if (i) 598 return i; 599 600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 601 602 for (i = 15; i >= 0; i--) 603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 604 if (ecc) 605 *ecc = t4_read_reg64(adap, MC_DATA(16)); 606 #undef MC_DATA 607 return 0; 608 } 609 610 /** 611 * t4_edc_read - read from EDC through backdoor accesses 612 * @adap: the adapter 613 * @idx: which EDC to access 614 * @addr: address of first byte requested 615 * @data: 64 bytes of data containing the requested address 616 * @ecc: where to store the corresponding 64-bit ECC word 617 * 618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 619 * that covers the requested address @addr. If @parity is not %NULL it 620 * is assigned the 64-bit ECC word for the read data. 621 */ 622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 623 { 624 int i; 625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 627 628 if (is_t4(adap)) { 629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 633 idx); 634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 635 idx); 636 } else { 637 /* 638 * These macro are missing in t4_regs.h file. 639 * Added temporarily for testing. 640 */ 641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 649 idx); 650 #undef EDC_REG_T5 651 #undef EDC_STRIDE_T5 652 } 653 654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 655 return -EBUSY; 656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 659 t4_write_reg(adap, edc_bist_cmd_reg, 660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 662 if (i) 663 return i; 664 665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 666 667 for (i = 15; i >= 0; i--) 668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 669 if (ecc) 670 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 671 #undef EDC_DATA 672 return 0; 673 } 674 675 /** 676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 677 * @adap: the adapter 678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 679 * @addr: address within indicated memory type 680 * @len: amount of memory to read 681 * @buf: host memory buffer 682 * 683 * Reads an [almost] arbitrary memory region in the firmware: the 684 * firmware memory address, length and host buffer must be aligned on 685 * 32-bit boudaries. The memory is returned as a raw byte sequence from 686 * the firmware's memory. If this memory contains data structures which 687 * contain multi-byte integers, it's the callers responsibility to 688 * perform appropriate byte order conversions. 689 */ 690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 691 __be32 *buf) 692 { 693 u32 pos, start, end, offset; 694 int ret; 695 696 /* 697 * Argument sanity checks ... 698 */ 699 if ((addr & 0x3) || (len & 0x3)) 700 return -EINVAL; 701 702 /* 703 * The underlaying EDC/MC read routines read 64 bytes at a time so we 704 * need to round down the start and round up the end. We'll start 705 * copying out of the first line at (addr - start) a word at a time. 706 */ 707 start = rounddown2(addr, 64); 708 end = roundup2(addr + len, 64); 709 offset = (addr - start)/sizeof(__be32); 710 711 for (pos = start; pos < end; pos += 64, offset = 0) { 712 __be32 data[16]; 713 714 /* 715 * Read the chip's memory block and bail if there's an error. 716 */ 717 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 719 else 720 ret = t4_edc_read(adap, mtype, pos, data, NULL); 721 if (ret) 722 return ret; 723 724 /* 725 * Copy the data into the caller's memory buffer. 726 */ 727 while (offset < 16 && len > 0) { 728 *buf++ = data[offset++]; 729 len -= sizeof(__be32); 730 } 731 } 732 733 return 0; 734 } 735 736 /* 737 * Return the specified PCI-E Configuration Space register from our Physical 738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 739 * since we prefer to let the firmware own all of these registers, but if that 740 * fails we go for it directly ourselves. 741 */ 742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 743 { 744 745 /* 746 * If fw_attach != 0, construct and send the Firmware LDST Command to 747 * retrieve the specified PCI-E Configuration Space register. 748 */ 749 if (drv_fw_attach != 0) { 750 struct fw_ldst_cmd ldst_cmd; 751 int ret; 752 753 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 754 ldst_cmd.op_to_addrspace = 755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 756 F_FW_CMD_REQUEST | 757 F_FW_CMD_READ | 758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 761 ldst_cmd.u.pcie.ctrl_to_fn = 762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 763 ldst_cmd.u.pcie.r = reg; 764 765 /* 766 * If the LDST Command succeeds, return the result, otherwise 767 * fall through to reading it directly ourselves ... 768 */ 769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 770 &ldst_cmd); 771 if (ret == 0) 772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 773 774 CH_WARN(adap, "Firmware failed to return " 775 "Configuration Space register %d, err = %d\n", 776 reg, -ret); 777 } 778 779 /* 780 * Read the desired Configuration Space register via the PCI-E 781 * Backdoor mechanism. 782 */ 783 return t4_hw_pci_read_cfg4(adap, reg); 784 } 785 786 /** 787 * t4_get_regs_len - return the size of the chips register set 788 * @adapter: the adapter 789 * 790 * Returns the size of the chip's BAR0 register space. 791 */ 792 unsigned int t4_get_regs_len(struct adapter *adapter) 793 { 794 unsigned int chip_version = chip_id(adapter); 795 796 switch (chip_version) { 797 case CHELSIO_T4: 798 if (adapter->flags & IS_VF) 799 return FW_T4VF_REGMAP_SIZE; 800 return T4_REGMAP_SIZE; 801 802 case CHELSIO_T5: 803 case CHELSIO_T6: 804 if (adapter->flags & IS_VF) 805 return FW_T4VF_REGMAP_SIZE; 806 return T5_REGMAP_SIZE; 807 } 808 809 CH_ERR(adapter, 810 "Unsupported chip version %d\n", chip_version); 811 return 0; 812 } 813 814 /** 815 * t4_get_regs - read chip registers into provided buffer 816 * @adap: the adapter 817 * @buf: register buffer 818 * @buf_size: size (in bytes) of register buffer 819 * 820 * If the provided register buffer isn't large enough for the chip's 821 * full register range, the register dump will be truncated to the 822 * register buffer's size. 823 */ 824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 825 { 826 static const unsigned int t4_reg_ranges[] = { 827 0x1008, 0x1108, 828 0x1180, 0x1184, 829 0x1190, 0x1194, 830 0x11a0, 0x11a4, 831 0x11b0, 0x11b4, 832 0x11fc, 0x123c, 833 0x1300, 0x173c, 834 0x1800, 0x18fc, 835 0x3000, 0x30d8, 836 0x30e0, 0x30e4, 837 0x30ec, 0x5910, 838 0x5920, 0x5924, 839 0x5960, 0x5960, 840 0x5968, 0x5968, 841 0x5970, 0x5970, 842 0x5978, 0x5978, 843 0x5980, 0x5980, 844 0x5988, 0x5988, 845 0x5990, 0x5990, 846 0x5998, 0x5998, 847 0x59a0, 0x59d4, 848 0x5a00, 0x5ae0, 849 0x5ae8, 0x5ae8, 850 0x5af0, 0x5af0, 851 0x5af8, 0x5af8, 852 0x6000, 0x6098, 853 0x6100, 0x6150, 854 0x6200, 0x6208, 855 0x6240, 0x6248, 856 0x6280, 0x62b0, 857 0x62c0, 0x6338, 858 0x6370, 0x638c, 859 0x6400, 0x643c, 860 0x6500, 0x6524, 861 0x6a00, 0x6a04, 862 0x6a14, 0x6a38, 863 0x6a60, 0x6a70, 864 0x6a78, 0x6a78, 865 0x6b00, 0x6b0c, 866 0x6b1c, 0x6b84, 867 0x6bf0, 0x6bf8, 868 0x6c00, 0x6c0c, 869 0x6c1c, 0x6c84, 870 0x6cf0, 0x6cf8, 871 0x6d00, 0x6d0c, 872 0x6d1c, 0x6d84, 873 0x6df0, 0x6df8, 874 0x6e00, 0x6e0c, 875 0x6e1c, 0x6e84, 876 0x6ef0, 0x6ef8, 877 0x6f00, 0x6f0c, 878 0x6f1c, 0x6f84, 879 0x6ff0, 0x6ff8, 880 0x7000, 0x700c, 881 0x701c, 0x7084, 882 0x70f0, 0x70f8, 883 0x7100, 0x710c, 884 0x711c, 0x7184, 885 0x71f0, 0x71f8, 886 0x7200, 0x720c, 887 0x721c, 0x7284, 888 0x72f0, 0x72f8, 889 0x7300, 0x730c, 890 0x731c, 0x7384, 891 0x73f0, 0x73f8, 892 0x7400, 0x7450, 893 0x7500, 0x7530, 894 0x7600, 0x760c, 895 0x7614, 0x761c, 896 0x7680, 0x76cc, 897 0x7700, 0x7798, 898 0x77c0, 0x77fc, 899 0x7900, 0x79fc, 900 0x7b00, 0x7b58, 901 0x7b60, 0x7b84, 902 0x7b8c, 0x7c38, 903 0x7d00, 0x7d38, 904 0x7d40, 0x7d80, 905 0x7d8c, 0x7ddc, 906 0x7de4, 0x7e04, 907 0x7e10, 0x7e1c, 908 0x7e24, 0x7e38, 909 0x7e40, 0x7e44, 910 0x7e4c, 0x7e78, 911 0x7e80, 0x7ea4, 912 0x7eac, 0x7edc, 913 0x7ee8, 0x7efc, 914 0x8dc0, 0x8e04, 915 0x8e10, 0x8e1c, 916 0x8e30, 0x8e78, 917 0x8ea0, 0x8eb8, 918 0x8ec0, 0x8f6c, 919 0x8fc0, 0x9008, 920 0x9010, 0x9058, 921 0x9060, 0x9060, 922 0x9068, 0x9074, 923 0x90fc, 0x90fc, 924 0x9400, 0x9408, 925 0x9410, 0x9458, 926 0x9600, 0x9600, 927 0x9608, 0x9638, 928 0x9640, 0x96bc, 929 0x9800, 0x9808, 930 0x9820, 0x983c, 931 0x9850, 0x9864, 932 0x9c00, 0x9c6c, 933 0x9c80, 0x9cec, 934 0x9d00, 0x9d6c, 935 0x9d80, 0x9dec, 936 0x9e00, 0x9e6c, 937 0x9e80, 0x9eec, 938 0x9f00, 0x9f6c, 939 0x9f80, 0x9fec, 940 0xd004, 0xd004, 941 0xd010, 0xd03c, 942 0xdfc0, 0xdfe0, 943 0xe000, 0xea7c, 944 0xf000, 0x11110, 945 0x11118, 0x11190, 946 0x19040, 0x1906c, 947 0x19078, 0x19080, 948 0x1908c, 0x190e4, 949 0x190f0, 0x190f8, 950 0x19100, 0x19110, 951 0x19120, 0x19124, 952 0x19150, 0x19194, 953 0x1919c, 0x191b0, 954 0x191d0, 0x191e8, 955 0x19238, 0x1924c, 956 0x193f8, 0x1943c, 957 0x1944c, 0x19474, 958 0x19490, 0x194e0, 959 0x194f0, 0x194f8, 960 0x19800, 0x19c08, 961 0x19c10, 0x19c90, 962 0x19ca0, 0x19ce4, 963 0x19cf0, 0x19d40, 964 0x19d50, 0x19d94, 965 0x19da0, 0x19de8, 966 0x19df0, 0x19e40, 967 0x19e50, 0x19e90, 968 0x19ea0, 0x19f4c, 969 0x1a000, 0x1a004, 970 0x1a010, 0x1a06c, 971 0x1a0b0, 0x1a0e4, 972 0x1a0ec, 0x1a0f4, 973 0x1a100, 0x1a108, 974 0x1a114, 0x1a120, 975 0x1a128, 0x1a130, 976 0x1a138, 0x1a138, 977 0x1a190, 0x1a1c4, 978 0x1a1fc, 0x1a1fc, 979 0x1e040, 0x1e04c, 980 0x1e284, 0x1e28c, 981 0x1e2c0, 0x1e2c0, 982 0x1e2e0, 0x1e2e0, 983 0x1e300, 0x1e384, 984 0x1e3c0, 0x1e3c8, 985 0x1e440, 0x1e44c, 986 0x1e684, 0x1e68c, 987 0x1e6c0, 0x1e6c0, 988 0x1e6e0, 0x1e6e0, 989 0x1e700, 0x1e784, 990 0x1e7c0, 0x1e7c8, 991 0x1e840, 0x1e84c, 992 0x1ea84, 0x1ea8c, 993 0x1eac0, 0x1eac0, 994 0x1eae0, 0x1eae0, 995 0x1eb00, 0x1eb84, 996 0x1ebc0, 0x1ebc8, 997 0x1ec40, 0x1ec4c, 998 0x1ee84, 0x1ee8c, 999 0x1eec0, 0x1eec0, 1000 0x1eee0, 0x1eee0, 1001 0x1ef00, 0x1ef84, 1002 0x1efc0, 0x1efc8, 1003 0x1f040, 0x1f04c, 1004 0x1f284, 0x1f28c, 1005 0x1f2c0, 0x1f2c0, 1006 0x1f2e0, 0x1f2e0, 1007 0x1f300, 0x1f384, 1008 0x1f3c0, 0x1f3c8, 1009 0x1f440, 0x1f44c, 1010 0x1f684, 0x1f68c, 1011 0x1f6c0, 0x1f6c0, 1012 0x1f6e0, 0x1f6e0, 1013 0x1f700, 0x1f784, 1014 0x1f7c0, 0x1f7c8, 1015 0x1f840, 0x1f84c, 1016 0x1fa84, 0x1fa8c, 1017 0x1fac0, 0x1fac0, 1018 0x1fae0, 0x1fae0, 1019 0x1fb00, 0x1fb84, 1020 0x1fbc0, 0x1fbc8, 1021 0x1fc40, 0x1fc4c, 1022 0x1fe84, 0x1fe8c, 1023 0x1fec0, 0x1fec0, 1024 0x1fee0, 0x1fee0, 1025 0x1ff00, 0x1ff84, 1026 0x1ffc0, 0x1ffc8, 1027 0x20000, 0x2002c, 1028 0x20100, 0x2013c, 1029 0x20190, 0x201a0, 1030 0x201a8, 0x201b8, 1031 0x201c4, 0x201c8, 1032 0x20200, 0x20318, 1033 0x20400, 0x204b4, 1034 0x204c0, 0x20528, 1035 0x20540, 0x20614, 1036 0x21000, 0x21040, 1037 0x2104c, 0x21060, 1038 0x210c0, 0x210ec, 1039 0x21200, 0x21268, 1040 0x21270, 0x21284, 1041 0x212fc, 0x21388, 1042 0x21400, 0x21404, 1043 0x21500, 0x21500, 1044 0x21510, 0x21518, 1045 0x2152c, 0x21530, 1046 0x2153c, 0x2153c, 1047 0x21550, 0x21554, 1048 0x21600, 0x21600, 1049 0x21608, 0x2161c, 1050 0x21624, 0x21628, 1051 0x21630, 0x21634, 1052 0x2163c, 0x2163c, 1053 0x21700, 0x2171c, 1054 0x21780, 0x2178c, 1055 0x21800, 0x21818, 1056 0x21820, 0x21828, 1057 0x21830, 0x21848, 1058 0x21850, 0x21854, 1059 0x21860, 0x21868, 1060 0x21870, 0x21870, 1061 0x21878, 0x21898, 1062 0x218a0, 0x218a8, 1063 0x218b0, 0x218c8, 1064 0x218d0, 0x218d4, 1065 0x218e0, 0x218e8, 1066 0x218f0, 0x218f0, 1067 0x218f8, 0x21a18, 1068 0x21a20, 0x21a28, 1069 0x21a30, 0x21a48, 1070 0x21a50, 0x21a54, 1071 0x21a60, 0x21a68, 1072 0x21a70, 0x21a70, 1073 0x21a78, 0x21a98, 1074 0x21aa0, 0x21aa8, 1075 0x21ab0, 0x21ac8, 1076 0x21ad0, 0x21ad4, 1077 0x21ae0, 0x21ae8, 1078 0x21af0, 0x21af0, 1079 0x21af8, 0x21c18, 1080 0x21c20, 0x21c20, 1081 0x21c28, 0x21c30, 1082 0x21c38, 0x21c38, 1083 0x21c80, 0x21c98, 1084 0x21ca0, 0x21ca8, 1085 0x21cb0, 0x21cc8, 1086 0x21cd0, 0x21cd4, 1087 0x21ce0, 0x21ce8, 1088 0x21cf0, 0x21cf0, 1089 0x21cf8, 0x21d7c, 1090 0x21e00, 0x21e04, 1091 0x22000, 0x2202c, 1092 0x22100, 0x2213c, 1093 0x22190, 0x221a0, 1094 0x221a8, 0x221b8, 1095 0x221c4, 0x221c8, 1096 0x22200, 0x22318, 1097 0x22400, 0x224b4, 1098 0x224c0, 0x22528, 1099 0x22540, 0x22614, 1100 0x23000, 0x23040, 1101 0x2304c, 0x23060, 1102 0x230c0, 0x230ec, 1103 0x23200, 0x23268, 1104 0x23270, 0x23284, 1105 0x232fc, 0x23388, 1106 0x23400, 0x23404, 1107 0x23500, 0x23500, 1108 0x23510, 0x23518, 1109 0x2352c, 0x23530, 1110 0x2353c, 0x2353c, 1111 0x23550, 0x23554, 1112 0x23600, 0x23600, 1113 0x23608, 0x2361c, 1114 0x23624, 0x23628, 1115 0x23630, 0x23634, 1116 0x2363c, 0x2363c, 1117 0x23700, 0x2371c, 1118 0x23780, 0x2378c, 1119 0x23800, 0x23818, 1120 0x23820, 0x23828, 1121 0x23830, 0x23848, 1122 0x23850, 0x23854, 1123 0x23860, 0x23868, 1124 0x23870, 0x23870, 1125 0x23878, 0x23898, 1126 0x238a0, 0x238a8, 1127 0x238b0, 0x238c8, 1128 0x238d0, 0x238d4, 1129 0x238e0, 0x238e8, 1130 0x238f0, 0x238f0, 1131 0x238f8, 0x23a18, 1132 0x23a20, 0x23a28, 1133 0x23a30, 0x23a48, 1134 0x23a50, 0x23a54, 1135 0x23a60, 0x23a68, 1136 0x23a70, 0x23a70, 1137 0x23a78, 0x23a98, 1138 0x23aa0, 0x23aa8, 1139 0x23ab0, 0x23ac8, 1140 0x23ad0, 0x23ad4, 1141 0x23ae0, 0x23ae8, 1142 0x23af0, 0x23af0, 1143 0x23af8, 0x23c18, 1144 0x23c20, 0x23c20, 1145 0x23c28, 0x23c30, 1146 0x23c38, 0x23c38, 1147 0x23c80, 0x23c98, 1148 0x23ca0, 0x23ca8, 1149 0x23cb0, 0x23cc8, 1150 0x23cd0, 0x23cd4, 1151 0x23ce0, 0x23ce8, 1152 0x23cf0, 0x23cf0, 1153 0x23cf8, 0x23d7c, 1154 0x23e00, 0x23e04, 1155 0x24000, 0x2402c, 1156 0x24100, 0x2413c, 1157 0x24190, 0x241a0, 1158 0x241a8, 0x241b8, 1159 0x241c4, 0x241c8, 1160 0x24200, 0x24318, 1161 0x24400, 0x244b4, 1162 0x244c0, 0x24528, 1163 0x24540, 0x24614, 1164 0x25000, 0x25040, 1165 0x2504c, 0x25060, 1166 0x250c0, 0x250ec, 1167 0x25200, 0x25268, 1168 0x25270, 0x25284, 1169 0x252fc, 0x25388, 1170 0x25400, 0x25404, 1171 0x25500, 0x25500, 1172 0x25510, 0x25518, 1173 0x2552c, 0x25530, 1174 0x2553c, 0x2553c, 1175 0x25550, 0x25554, 1176 0x25600, 0x25600, 1177 0x25608, 0x2561c, 1178 0x25624, 0x25628, 1179 0x25630, 0x25634, 1180 0x2563c, 0x2563c, 1181 0x25700, 0x2571c, 1182 0x25780, 0x2578c, 1183 0x25800, 0x25818, 1184 0x25820, 0x25828, 1185 0x25830, 0x25848, 1186 0x25850, 0x25854, 1187 0x25860, 0x25868, 1188 0x25870, 0x25870, 1189 0x25878, 0x25898, 1190 0x258a0, 0x258a8, 1191 0x258b0, 0x258c8, 1192 0x258d0, 0x258d4, 1193 0x258e0, 0x258e8, 1194 0x258f0, 0x258f0, 1195 0x258f8, 0x25a18, 1196 0x25a20, 0x25a28, 1197 0x25a30, 0x25a48, 1198 0x25a50, 0x25a54, 1199 0x25a60, 0x25a68, 1200 0x25a70, 0x25a70, 1201 0x25a78, 0x25a98, 1202 0x25aa0, 0x25aa8, 1203 0x25ab0, 0x25ac8, 1204 0x25ad0, 0x25ad4, 1205 0x25ae0, 0x25ae8, 1206 0x25af0, 0x25af0, 1207 0x25af8, 0x25c18, 1208 0x25c20, 0x25c20, 1209 0x25c28, 0x25c30, 1210 0x25c38, 0x25c38, 1211 0x25c80, 0x25c98, 1212 0x25ca0, 0x25ca8, 1213 0x25cb0, 0x25cc8, 1214 0x25cd0, 0x25cd4, 1215 0x25ce0, 0x25ce8, 1216 0x25cf0, 0x25cf0, 1217 0x25cf8, 0x25d7c, 1218 0x25e00, 0x25e04, 1219 0x26000, 0x2602c, 1220 0x26100, 0x2613c, 1221 0x26190, 0x261a0, 1222 0x261a8, 0x261b8, 1223 0x261c4, 0x261c8, 1224 0x26200, 0x26318, 1225 0x26400, 0x264b4, 1226 0x264c0, 0x26528, 1227 0x26540, 0x26614, 1228 0x27000, 0x27040, 1229 0x2704c, 0x27060, 1230 0x270c0, 0x270ec, 1231 0x27200, 0x27268, 1232 0x27270, 0x27284, 1233 0x272fc, 0x27388, 1234 0x27400, 0x27404, 1235 0x27500, 0x27500, 1236 0x27510, 0x27518, 1237 0x2752c, 0x27530, 1238 0x2753c, 0x2753c, 1239 0x27550, 0x27554, 1240 0x27600, 0x27600, 1241 0x27608, 0x2761c, 1242 0x27624, 0x27628, 1243 0x27630, 0x27634, 1244 0x2763c, 0x2763c, 1245 0x27700, 0x2771c, 1246 0x27780, 0x2778c, 1247 0x27800, 0x27818, 1248 0x27820, 0x27828, 1249 0x27830, 0x27848, 1250 0x27850, 0x27854, 1251 0x27860, 0x27868, 1252 0x27870, 0x27870, 1253 0x27878, 0x27898, 1254 0x278a0, 0x278a8, 1255 0x278b0, 0x278c8, 1256 0x278d0, 0x278d4, 1257 0x278e0, 0x278e8, 1258 0x278f0, 0x278f0, 1259 0x278f8, 0x27a18, 1260 0x27a20, 0x27a28, 1261 0x27a30, 0x27a48, 1262 0x27a50, 0x27a54, 1263 0x27a60, 0x27a68, 1264 0x27a70, 0x27a70, 1265 0x27a78, 0x27a98, 1266 0x27aa0, 0x27aa8, 1267 0x27ab0, 0x27ac8, 1268 0x27ad0, 0x27ad4, 1269 0x27ae0, 0x27ae8, 1270 0x27af0, 0x27af0, 1271 0x27af8, 0x27c18, 1272 0x27c20, 0x27c20, 1273 0x27c28, 0x27c30, 1274 0x27c38, 0x27c38, 1275 0x27c80, 0x27c98, 1276 0x27ca0, 0x27ca8, 1277 0x27cb0, 0x27cc8, 1278 0x27cd0, 0x27cd4, 1279 0x27ce0, 0x27ce8, 1280 0x27cf0, 0x27cf0, 1281 0x27cf8, 0x27d7c, 1282 0x27e00, 0x27e04, 1283 }; 1284 1285 static const unsigned int t4vf_reg_ranges[] = { 1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1287 VF_MPS_REG(A_MPS_VF_CTL), 1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1292 FW_T4VF_MBDATA_BASE_ADDR, 1293 FW_T4VF_MBDATA_BASE_ADDR + 1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1295 }; 1296 1297 static const unsigned int t5_reg_ranges[] = { 1298 0x1008, 0x10c0, 1299 0x10cc, 0x10f8, 1300 0x1100, 0x1100, 1301 0x110c, 0x1148, 1302 0x1180, 0x1184, 1303 0x1190, 0x1194, 1304 0x11a0, 0x11a4, 1305 0x11b0, 0x11b4, 1306 0x11fc, 0x123c, 1307 0x1280, 0x173c, 1308 0x1800, 0x18fc, 1309 0x3000, 0x3028, 1310 0x3060, 0x30b0, 1311 0x30b8, 0x30d8, 1312 0x30e0, 0x30fc, 1313 0x3140, 0x357c, 1314 0x35a8, 0x35cc, 1315 0x35ec, 0x35ec, 1316 0x3600, 0x5624, 1317 0x56cc, 0x56ec, 1318 0x56f4, 0x5720, 1319 0x5728, 0x575c, 1320 0x580c, 0x5814, 1321 0x5890, 0x589c, 1322 0x58a4, 0x58ac, 1323 0x58b8, 0x58bc, 1324 0x5940, 0x59c8, 1325 0x59d0, 0x59dc, 1326 0x59fc, 0x5a18, 1327 0x5a60, 0x5a70, 1328 0x5a80, 0x5a9c, 1329 0x5b94, 0x5bfc, 1330 0x6000, 0x6020, 1331 0x6028, 0x6040, 1332 0x6058, 0x609c, 1333 0x60a8, 0x614c, 1334 0x7700, 0x7798, 1335 0x77c0, 0x78fc, 1336 0x7b00, 0x7b58, 1337 0x7b60, 0x7b84, 1338 0x7b8c, 0x7c54, 1339 0x7d00, 0x7d38, 1340 0x7d40, 0x7d80, 1341 0x7d8c, 0x7ddc, 1342 0x7de4, 0x7e04, 1343 0x7e10, 0x7e1c, 1344 0x7e24, 0x7e38, 1345 0x7e40, 0x7e44, 1346 0x7e4c, 0x7e78, 1347 0x7e80, 0x7edc, 1348 0x7ee8, 0x7efc, 1349 0x8dc0, 0x8de0, 1350 0x8df8, 0x8e04, 1351 0x8e10, 0x8e84, 1352 0x8ea0, 0x8f84, 1353 0x8fc0, 0x9058, 1354 0x9060, 0x9060, 1355 0x9068, 0x90f8, 1356 0x9400, 0x9408, 1357 0x9410, 0x9470, 1358 0x9600, 0x9600, 1359 0x9608, 0x9638, 1360 0x9640, 0x96f4, 1361 0x9800, 0x9808, 1362 0x9810, 0x9864, 1363 0x9c00, 0x9c6c, 1364 0x9c80, 0x9cec, 1365 0x9d00, 0x9d6c, 1366 0x9d80, 0x9dec, 1367 0x9e00, 0x9e6c, 1368 0x9e80, 0x9eec, 1369 0x9f00, 0x9f6c, 1370 0x9f80, 0xa020, 1371 0xd000, 0xd004, 1372 0xd010, 0xd03c, 1373 0xdfc0, 0xdfe0, 1374 0xe000, 0x1106c, 1375 0x11074, 0x11088, 1376 0x1109c, 0x11110, 1377 0x11118, 0x1117c, 1378 0x11190, 0x11204, 1379 0x19040, 0x1906c, 1380 0x19078, 0x19080, 1381 0x1908c, 0x190e8, 1382 0x190f0, 0x190f8, 1383 0x19100, 0x19110, 1384 0x19120, 0x19124, 1385 0x19150, 0x19194, 1386 0x1919c, 0x191b0, 1387 0x191d0, 0x191e8, 1388 0x19238, 0x19290, 1389 0x193f8, 0x19428, 1390 0x19430, 0x19444, 1391 0x1944c, 0x1946c, 1392 0x19474, 0x19474, 1393 0x19490, 0x194cc, 1394 0x194f0, 0x194f8, 1395 0x19c00, 0x19c08, 1396 0x19c10, 0x19c60, 1397 0x19c94, 0x19ce4, 1398 0x19cf0, 0x19d40, 1399 0x19d50, 0x19d94, 1400 0x19da0, 0x19de8, 1401 0x19df0, 0x19e10, 1402 0x19e50, 0x19e90, 1403 0x19ea0, 0x19f24, 1404 0x19f34, 0x19f34, 1405 0x19f40, 0x19f50, 1406 0x19f90, 0x19fb4, 1407 0x19fc4, 0x19fe4, 1408 0x1a000, 0x1a004, 1409 0x1a010, 0x1a06c, 1410 0x1a0b0, 0x1a0e4, 1411 0x1a0ec, 0x1a0f8, 1412 0x1a100, 0x1a108, 1413 0x1a114, 0x1a130, 1414 0x1a138, 0x1a1c4, 1415 0x1a1fc, 0x1a1fc, 1416 0x1e008, 0x1e00c, 1417 0x1e040, 0x1e044, 1418 0x1e04c, 0x1e04c, 1419 0x1e284, 0x1e290, 1420 0x1e2c0, 0x1e2c0, 1421 0x1e2e0, 0x1e2e0, 1422 0x1e300, 0x1e384, 1423 0x1e3c0, 0x1e3c8, 1424 0x1e408, 0x1e40c, 1425 0x1e440, 0x1e444, 1426 0x1e44c, 0x1e44c, 1427 0x1e684, 0x1e690, 1428 0x1e6c0, 0x1e6c0, 1429 0x1e6e0, 0x1e6e0, 1430 0x1e700, 0x1e784, 1431 0x1e7c0, 0x1e7c8, 1432 0x1e808, 0x1e80c, 1433 0x1e840, 0x1e844, 1434 0x1e84c, 0x1e84c, 1435 0x1ea84, 0x1ea90, 1436 0x1eac0, 0x1eac0, 1437 0x1eae0, 0x1eae0, 1438 0x1eb00, 0x1eb84, 1439 0x1ebc0, 0x1ebc8, 1440 0x1ec08, 0x1ec0c, 1441 0x1ec40, 0x1ec44, 1442 0x1ec4c, 0x1ec4c, 1443 0x1ee84, 0x1ee90, 1444 0x1eec0, 0x1eec0, 1445 0x1eee0, 0x1eee0, 1446 0x1ef00, 0x1ef84, 1447 0x1efc0, 0x1efc8, 1448 0x1f008, 0x1f00c, 1449 0x1f040, 0x1f044, 1450 0x1f04c, 0x1f04c, 1451 0x1f284, 0x1f290, 1452 0x1f2c0, 0x1f2c0, 1453 0x1f2e0, 0x1f2e0, 1454 0x1f300, 0x1f384, 1455 0x1f3c0, 0x1f3c8, 1456 0x1f408, 0x1f40c, 1457 0x1f440, 0x1f444, 1458 0x1f44c, 0x1f44c, 1459 0x1f684, 0x1f690, 1460 0x1f6c0, 0x1f6c0, 1461 0x1f6e0, 0x1f6e0, 1462 0x1f700, 0x1f784, 1463 0x1f7c0, 0x1f7c8, 1464 0x1f808, 0x1f80c, 1465 0x1f840, 0x1f844, 1466 0x1f84c, 0x1f84c, 1467 0x1fa84, 0x1fa90, 1468 0x1fac0, 0x1fac0, 1469 0x1fae0, 0x1fae0, 1470 0x1fb00, 0x1fb84, 1471 0x1fbc0, 0x1fbc8, 1472 0x1fc08, 0x1fc0c, 1473 0x1fc40, 0x1fc44, 1474 0x1fc4c, 0x1fc4c, 1475 0x1fe84, 0x1fe90, 1476 0x1fec0, 0x1fec0, 1477 0x1fee0, 0x1fee0, 1478 0x1ff00, 0x1ff84, 1479 0x1ffc0, 0x1ffc8, 1480 0x30000, 0x30030, 1481 0x30100, 0x30144, 1482 0x30190, 0x301a0, 1483 0x301a8, 0x301b8, 1484 0x301c4, 0x301c8, 1485 0x301d0, 0x301d0, 1486 0x30200, 0x30318, 1487 0x30400, 0x304b4, 1488 0x304c0, 0x3052c, 1489 0x30540, 0x3061c, 1490 0x30800, 0x30828, 1491 0x30834, 0x30834, 1492 0x308c0, 0x30908, 1493 0x30910, 0x309ac, 1494 0x30a00, 0x30a14, 1495 0x30a1c, 0x30a2c, 1496 0x30a44, 0x30a50, 1497 0x30a74, 0x30a74, 1498 0x30a7c, 0x30afc, 1499 0x30b08, 0x30c24, 1500 0x30d00, 0x30d00, 1501 0x30d08, 0x30d14, 1502 0x30d1c, 0x30d20, 1503 0x30d3c, 0x30d3c, 1504 0x30d48, 0x30d50, 1505 0x31200, 0x3120c, 1506 0x31220, 0x31220, 1507 0x31240, 0x31240, 1508 0x31600, 0x3160c, 1509 0x31a00, 0x31a1c, 1510 0x31e00, 0x31e20, 1511 0x31e38, 0x31e3c, 1512 0x31e80, 0x31e80, 1513 0x31e88, 0x31ea8, 1514 0x31eb0, 0x31eb4, 1515 0x31ec8, 0x31ed4, 1516 0x31fb8, 0x32004, 1517 0x32200, 0x32200, 1518 0x32208, 0x32240, 1519 0x32248, 0x32280, 1520 0x32288, 0x322c0, 1521 0x322c8, 0x322fc, 1522 0x32600, 0x32630, 1523 0x32a00, 0x32abc, 1524 0x32b00, 0x32b10, 1525 0x32b20, 0x32b30, 1526 0x32b40, 0x32b50, 1527 0x32b60, 0x32b70, 1528 0x33000, 0x33028, 1529 0x33030, 0x33048, 1530 0x33060, 0x33068, 1531 0x33070, 0x3309c, 1532 0x330f0, 0x33128, 1533 0x33130, 0x33148, 1534 0x33160, 0x33168, 1535 0x33170, 0x3319c, 1536 0x331f0, 0x33238, 1537 0x33240, 0x33240, 1538 0x33248, 0x33250, 1539 0x3325c, 0x33264, 1540 0x33270, 0x332b8, 1541 0x332c0, 0x332e4, 1542 0x332f8, 0x33338, 1543 0x33340, 0x33340, 1544 0x33348, 0x33350, 1545 0x3335c, 0x33364, 1546 0x33370, 0x333b8, 1547 0x333c0, 0x333e4, 1548 0x333f8, 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1722 0x38d1c, 0x38d20, 1723 0x38d3c, 0x38d3c, 1724 0x38d48, 0x38d50, 1725 0x39200, 0x3920c, 1726 0x39220, 0x39220, 1727 0x39240, 0x39240, 1728 0x39600, 0x3960c, 1729 0x39a00, 0x39a1c, 1730 0x39e00, 0x39e20, 1731 0x39e38, 0x39e3c, 1732 0x39e80, 0x39e80, 1733 0x39e88, 0x39ea8, 1734 0x39eb0, 0x39eb4, 1735 0x39ec8, 0x39ed4, 1736 0x39fb8, 0x3a004, 1737 0x3a200, 0x3a200, 1738 0x3a208, 0x3a240, 1739 0x3a248, 0x3a280, 1740 0x3a288, 0x3a2c0, 1741 0x3a2c8, 0x3a2fc, 1742 0x3a600, 0x3a630, 1743 0x3aa00, 0x3aabc, 1744 0x3ab00, 0x3ab10, 1745 0x3ab20, 0x3ab30, 1746 0x3ab40, 0x3ab50, 1747 0x3ab60, 0x3ab70, 1748 0x3b000, 0x3b028, 1749 0x3b030, 0x3b048, 1750 0x3b060, 0x3b068, 1751 0x3b070, 0x3b09c, 1752 0x3b0f0, 0x3b128, 1753 0x3b130, 0x3b148, 1754 0x3b160, 0x3b168, 1755 0x3b170, 0x3b19c, 1756 0x3b1f0, 0x3b238, 1757 0x3b240, 0x3b240, 1758 0x3b248, 0x3b250, 1759 0x3b25c, 0x3b264, 1760 0x3b270, 0x3b2b8, 1761 0x3b2c0, 0x3b2e4, 1762 0x3b2f8, 0x3b338, 1763 0x3b340, 0x3b340, 1764 0x3b348, 0x3b350, 1765 0x3b35c, 0x3b364, 1766 0x3b370, 0x3b3b8, 1767 0x3b3c0, 0x3b3e4, 1768 0x3b3f8, 0x3b428, 1769 0x3b430, 0x3b448, 1770 0x3b460, 0x3b468, 1771 0x3b470, 0x3b49c, 1772 0x3b4f0, 0x3b528, 1773 0x3b530, 0x3b548, 1774 0x3b560, 0x3b568, 1775 0x3b570, 0x3b59c, 1776 0x3b5f0, 0x3b638, 1777 0x3b640, 0x3b640, 1778 0x3b648, 0x3b650, 1779 0x3b65c, 0x3b664, 1780 0x3b670, 0x3b6b8, 1781 0x3b6c0, 0x3b6e4, 1782 0x3b6f8, 0x3b738, 1783 0x3b740, 0x3b740, 1784 0x3b748, 0x3b750, 1785 0x3b75c, 0x3b764, 1786 0x3b770, 0x3b7b8, 1787 0x3b7c0, 0x3b7e4, 1788 0x3b7f8, 0x3b7fc, 1789 0x3b814, 0x3b814, 1790 0x3b82c, 0x3b82c, 1791 0x3b880, 0x3b88c, 1792 0x3b8e8, 0x3b8ec, 1793 0x3b900, 0x3b928, 1794 0x3b930, 0x3b948, 1795 0x3b960, 0x3b968, 1796 0x3b970, 0x3b99c, 1797 0x3b9f0, 0x3ba38, 1798 0x3ba40, 0x3ba40, 1799 0x3ba48, 0x3ba50, 1800 0x3ba5c, 0x3ba64, 1801 0x3ba70, 0x3bab8, 1802 0x3bac0, 0x3bae4, 1803 0x3baf8, 0x3bb10, 1804 0x3bb28, 0x3bb28, 1805 0x3bb3c, 0x3bb50, 1806 0x3bbf0, 0x3bc10, 1807 0x3bc28, 0x3bc28, 1808 0x3bc3c, 0x3bc50, 1809 0x3bcf0, 0x3bcfc, 1810 0x3c000, 0x3c030, 1811 0x3c100, 0x3c144, 1812 0x3c190, 0x3c1a0, 1813 0x3c1a8, 0x3c1b8, 1814 0x3c1c4, 0x3c1c8, 1815 0x3c1d0, 0x3c1d0, 1816 0x3c200, 0x3c318, 1817 0x3c400, 0x3c4b4, 1818 0x3c4c0, 0x3c52c, 1819 0x3c540, 0x3c61c, 1820 0x3c800, 0x3c828, 1821 0x3c834, 0x3c834, 1822 0x3c8c0, 0x3c908, 1823 0x3c910, 0x3c9ac, 1824 0x3ca00, 0x3ca14, 1825 0x3ca1c, 0x3ca2c, 1826 0x3ca44, 0x3ca50, 1827 0x3ca74, 0x3ca74, 1828 0x3ca7c, 0x3cafc, 1829 0x3cb08, 0x3cc24, 1830 0x3cd00, 0x3cd00, 1831 0x3cd08, 0x3cd14, 1832 0x3cd1c, 0x3cd20, 1833 0x3cd3c, 0x3cd3c, 1834 0x3cd48, 0x3cd50, 1835 0x3d200, 0x3d20c, 1836 0x3d220, 0x3d220, 1837 0x3d240, 0x3d240, 1838 0x3d600, 0x3d60c, 1839 0x3da00, 0x3da1c, 1840 0x3de00, 0x3de20, 1841 0x3de38, 0x3de3c, 1842 0x3de80, 0x3de80, 1843 0x3de88, 0x3dea8, 1844 0x3deb0, 0x3deb4, 1845 0x3dec8, 0x3ded4, 1846 0x3dfb8, 0x3e004, 1847 0x3e200, 0x3e200, 1848 0x3e208, 0x3e240, 1849 0x3e248, 0x3e280, 1850 0x3e288, 0x3e2c0, 1851 0x3e2c8, 0x3e2fc, 1852 0x3e600, 0x3e630, 1853 0x3ea00, 0x3eabc, 1854 0x3eb00, 0x3eb10, 1855 0x3eb20, 0x3eb30, 1856 0x3eb40, 0x3eb50, 1857 0x3eb60, 0x3eb70, 1858 0x3f000, 0x3f028, 1859 0x3f030, 0x3f048, 1860 0x3f060, 0x3f068, 1861 0x3f070, 0x3f09c, 1862 0x3f0f0, 0x3f128, 1863 0x3f130, 0x3f148, 1864 0x3f160, 0x3f168, 1865 0x3f170, 0x3f19c, 1866 0x3f1f0, 0x3f238, 1867 0x3f240, 0x3f240, 1868 0x3f248, 0x3f250, 1869 0x3f25c, 0x3f264, 1870 0x3f270, 0x3f2b8, 1871 0x3f2c0, 0x3f2e4, 1872 0x3f2f8, 0x3f338, 1873 0x3f340, 0x3f340, 1874 0x3f348, 0x3f350, 1875 0x3f35c, 0x3f364, 1876 0x3f370, 0x3f3b8, 1877 0x3f3c0, 0x3f3e4, 1878 0x3f3f8, 0x3f428, 1879 0x3f430, 0x3f448, 1880 0x3f460, 0x3f468, 1881 0x3f470, 0x3f49c, 1882 0x3f4f0, 0x3f528, 1883 0x3f530, 0x3f548, 1884 0x3f560, 0x3f568, 1885 0x3f570, 0x3f59c, 1886 0x3f5f0, 0x3f638, 1887 0x3f640, 0x3f640, 1888 0x3f648, 0x3f650, 1889 0x3f65c, 0x3f664, 1890 0x3f670, 0x3f6b8, 1891 0x3f6c0, 0x3f6e4, 1892 0x3f6f8, 0x3f738, 1893 0x3f740, 0x3f740, 1894 0x3f748, 0x3f750, 1895 0x3f75c, 0x3f764, 1896 0x3f770, 0x3f7b8, 1897 0x3f7c0, 0x3f7e4, 1898 0x3f7f8, 0x3f7fc, 1899 0x3f814, 0x3f814, 1900 0x3f82c, 0x3f82c, 1901 0x3f880, 0x3f88c, 1902 0x3f8e8, 0x3f8ec, 1903 0x3f900, 0x3f928, 1904 0x3f930, 0x3f948, 1905 0x3f960, 0x3f968, 1906 0x3f970, 0x3f99c, 1907 0x3f9f0, 0x3fa38, 1908 0x3fa40, 0x3fa40, 1909 0x3fa48, 0x3fa50, 1910 0x3fa5c, 0x3fa64, 1911 0x3fa70, 0x3fab8, 1912 0x3fac0, 0x3fae4, 1913 0x3faf8, 0x3fb10, 1914 0x3fb28, 0x3fb28, 1915 0x3fb3c, 0x3fb50, 1916 0x3fbf0, 0x3fc10, 1917 0x3fc28, 0x3fc28, 1918 0x3fc3c, 0x3fc50, 1919 0x3fcf0, 0x3fcfc, 1920 0x40000, 0x4000c, 1921 0x40040, 0x40050, 1922 0x40060, 0x40068, 1923 0x4007c, 0x4008c, 1924 0x40094, 0x400b0, 1925 0x400c0, 0x40144, 1926 0x40180, 0x4018c, 1927 0x40200, 0x40254, 1928 0x40260, 0x40264, 1929 0x40270, 0x40288, 1930 0x40290, 0x40298, 1931 0x402ac, 0x402c8, 1932 0x402d0, 0x402e0, 1933 0x402f0, 0x402f0, 1934 0x40300, 0x4033c, 1935 0x403f8, 0x403fc, 1936 0x41304, 0x413c4, 1937 0x41400, 0x4140c, 1938 0x41414, 0x4141c, 1939 0x41480, 0x414d0, 1940 0x44000, 0x44054, 1941 0x4405c, 0x44078, 1942 0x440c0, 0x44174, 1943 0x44180, 0x441ac, 1944 0x441b4, 0x441b8, 1945 0x441c0, 0x44254, 1946 0x4425c, 0x44278, 1947 0x442c0, 0x44374, 1948 0x44380, 0x443ac, 1949 0x443b4, 0x443b8, 1950 0x443c0, 0x44454, 1951 0x4445c, 0x44478, 1952 0x444c0, 0x44574, 1953 0x44580, 0x445ac, 1954 0x445b4, 0x445b8, 1955 0x445c0, 0x44654, 1956 0x4465c, 0x44678, 1957 0x446c0, 0x44774, 1958 0x44780, 0x447ac, 1959 0x447b4, 0x447b8, 1960 0x447c0, 0x44854, 1961 0x4485c, 0x44878, 1962 0x448c0, 0x44974, 1963 0x44980, 0x449ac, 1964 0x449b4, 0x449b8, 1965 0x449c0, 0x449fc, 1966 0x45000, 0x45004, 1967 0x45010, 0x45030, 1968 0x45040, 0x45060, 1969 0x45068, 0x45068, 1970 0x45080, 0x45084, 1971 0x450a0, 0x450b0, 1972 0x45200, 0x45204, 1973 0x45210, 0x45230, 1974 0x45240, 0x45260, 1975 0x45268, 0x45268, 1976 0x45280, 0x45284, 1977 0x452a0, 0x452b0, 1978 0x460c0, 0x460e4, 1979 0x47000, 0x4703c, 1980 0x47044, 0x4708c, 1981 0x47200, 0x47250, 1982 0x47400, 0x47408, 1983 0x47414, 0x47420, 1984 0x47600, 0x47618, 1985 0x47800, 0x47814, 1986 0x48000, 0x4800c, 1987 0x48040, 0x48050, 1988 0x48060, 0x48068, 1989 0x4807c, 0x4808c, 1990 0x48094, 0x480b0, 1991 0x480c0, 0x48144, 1992 0x48180, 0x4818c, 1993 0x48200, 0x48254, 1994 0x48260, 0x48264, 1995 0x48270, 0x48288, 1996 0x48290, 0x48298, 1997 0x482ac, 0x482c8, 1998 0x482d0, 0x482e0, 1999 0x482f0, 0x482f0, 2000 0x48300, 0x4833c, 2001 0x483f8, 0x483fc, 2002 0x49304, 0x493c4, 2003 0x49400, 0x4940c, 2004 0x49414, 0x4941c, 2005 0x49480, 0x494d0, 2006 0x4c000, 0x4c054, 2007 0x4c05c, 0x4c078, 2008 0x4c0c0, 0x4c174, 2009 0x4c180, 0x4c1ac, 2010 0x4c1b4, 0x4c1b8, 2011 0x4c1c0, 0x4c254, 2012 0x4c25c, 0x4c278, 2013 0x4c2c0, 0x4c374, 2014 0x4c380, 0x4c3ac, 2015 0x4c3b4, 0x4c3b8, 2016 0x4c3c0, 0x4c454, 2017 0x4c45c, 0x4c478, 2018 0x4c4c0, 0x4c574, 2019 0x4c580, 0x4c5ac, 2020 0x4c5b4, 0x4c5b8, 2021 0x4c5c0, 0x4c654, 2022 0x4c65c, 0x4c678, 2023 0x4c6c0, 0x4c774, 2024 0x4c780, 0x4c7ac, 2025 0x4c7b4, 0x4c7b8, 2026 0x4c7c0, 0x4c854, 2027 0x4c85c, 0x4c878, 2028 0x4c8c0, 0x4c974, 2029 0x4c980, 0x4c9ac, 2030 0x4c9b4, 0x4c9b8, 2031 0x4c9c0, 0x4c9fc, 2032 0x4d000, 0x4d004, 2033 0x4d010, 0x4d030, 2034 0x4d040, 0x4d060, 2035 0x4d068, 0x4d068, 2036 0x4d080, 0x4d084, 2037 0x4d0a0, 0x4d0b0, 2038 0x4d200, 0x4d204, 2039 0x4d210, 0x4d230, 2040 0x4d240, 0x4d260, 2041 0x4d268, 0x4d268, 2042 0x4d280, 0x4d284, 2043 0x4d2a0, 0x4d2b0, 2044 0x4e0c0, 0x4e0e4, 2045 0x4f000, 0x4f03c, 2046 0x4f044, 0x4f08c, 2047 0x4f200, 0x4f250, 2048 0x4f400, 0x4f408, 2049 0x4f414, 0x4f420, 2050 0x4f600, 0x4f618, 2051 0x4f800, 0x4f814, 2052 0x50000, 0x50084, 2053 0x50090, 0x500cc, 2054 0x50400, 0x50400, 2055 0x50800, 0x50884, 2056 0x50890, 0x508cc, 2057 0x50c00, 0x50c00, 2058 0x51000, 0x5101c, 2059 0x51300, 0x51308, 2060 }; 2061 2062 static const unsigned int t5vf_reg_ranges[] = { 2063 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2064 VF_MPS_REG(A_MPS_VF_CTL), 2065 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2066 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2067 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2068 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2069 FW_T4VF_MBDATA_BASE_ADDR, 2070 FW_T4VF_MBDATA_BASE_ADDR + 2071 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2072 }; 2073 2074 static const unsigned int t6_reg_ranges[] = { 2075 0x1008, 0x101c, 2076 0x1024, 0x10a8, 2077 0x10b4, 0x10f8, 2078 0x1100, 0x1114, 2079 0x111c, 0x112c, 2080 0x1138, 0x113c, 2081 0x1144, 0x114c, 2082 0x1180, 0x1184, 2083 0x1190, 0x1194, 2084 0x11a0, 0x11a4, 2085 0x11b0, 0x11c4, 2086 0x11fc, 0x123c, 2087 0x1254, 0x1274, 2088 0x1280, 0x133c, 2089 0x1800, 0x18fc, 2090 0x3000, 0x302c, 2091 0x3060, 0x30b0, 2092 0x30b8, 0x30d8, 2093 0x30e0, 0x30fc, 2094 0x3140, 0x357c, 2095 0x35a8, 0x35cc, 2096 0x35ec, 0x35ec, 2097 0x3600, 0x5624, 2098 0x56cc, 0x56ec, 2099 0x56f4, 0x5720, 2100 0x5728, 0x575c, 2101 0x580c, 0x5814, 2102 0x5890, 0x589c, 2103 0x58a4, 0x58ac, 2104 0x58b8, 0x58bc, 2105 0x5940, 0x595c, 2106 0x5980, 0x598c, 2107 0x59b0, 0x59c8, 2108 0x59d0, 0x59dc, 2109 0x59fc, 0x5a18, 2110 0x5a60, 0x5a6c, 2111 0x5a80, 0x5a8c, 2112 0x5a94, 0x5a9c, 2113 0x5b94, 0x5bfc, 2114 0x5c10, 0x5e48, 2115 0x5e50, 0x5e94, 2116 0x5ea0, 0x5eb0, 2117 0x5ec0, 0x5ec0, 2118 0x5ec8, 0x5ed0, 2119 0x5ee0, 0x5ee0, 2120 0x5ef0, 0x5ef0, 2121 0x5f00, 0x5f00, 2122 0x6000, 0x6020, 2123 0x6028, 0x6040, 2124 0x6058, 0x609c, 2125 0x60a8, 0x619c, 2126 0x7700, 0x7798, 2127 0x77c0, 0x7880, 2128 0x78cc, 0x78fc, 2129 0x7b00, 0x7b58, 2130 0x7b60, 0x7b84, 2131 0x7b8c, 0x7c54, 2132 0x7d00, 0x7d38, 2133 0x7d40, 0x7d84, 2134 0x7d8c, 0x7ddc, 2135 0x7de4, 0x7e04, 2136 0x7e10, 0x7e1c, 2137 0x7e24, 0x7e38, 2138 0x7e40, 0x7e44, 2139 0x7e4c, 0x7e78, 2140 0x7e80, 0x7edc, 2141 0x7ee8, 0x7efc, 2142 0x8dc0, 0x8de0, 2143 0x8df8, 0x8e04, 2144 0x8e10, 0x8e84, 2145 0x8ea0, 0x8f88, 2146 0x8fb8, 0x9058, 2147 0x9060, 0x9060, 2148 0x9068, 0x90f8, 2149 0x9100, 0x9124, 2150 0x9400, 0x9470, 2151 0x9600, 0x9600, 2152 0x9608, 0x9638, 2153 0x9640, 0x9704, 2154 0x9710, 0x971c, 2155 0x9800, 0x9808, 2156 0x9810, 0x9864, 2157 0x9c00, 0x9c6c, 2158 0x9c80, 0x9cec, 2159 0x9d00, 0x9d6c, 2160 0x9d80, 0x9dec, 2161 0x9e00, 0x9e6c, 2162 0x9e80, 0x9eec, 2163 0x9f00, 0x9f6c, 2164 0x9f80, 0xa020, 2165 0xd000, 0xd03c, 2166 0xd100, 0xd118, 2167 0xd200, 0xd214, 2168 0xd220, 0xd234, 2169 0xd240, 0xd254, 2170 0xd260, 0xd274, 2171 0xd280, 0xd294, 2172 0xd2a0, 0xd2b4, 2173 0xd2c0, 0xd2d4, 2174 0xd2e0, 0xd2f4, 2175 0xd300, 0xd31c, 2176 0xdfc0, 0xdfe0, 2177 0xe000, 0xf008, 2178 0xf010, 0xf018, 2179 0xf020, 0xf028, 2180 0x11000, 0x11014, 2181 0x11048, 0x1106c, 2182 0x11074, 0x11088, 2183 0x11098, 0x11120, 2184 0x1112c, 0x1117c, 2185 0x11190, 0x112e0, 2186 0x11300, 0x1130c, 2187 0x12000, 0x1206c, 2188 0x19040, 0x1906c, 2189 0x19078, 0x19080, 2190 0x1908c, 0x190e8, 2191 0x190f0, 0x190f8, 2192 0x19100, 0x19110, 2193 0x19120, 0x19124, 2194 0x19150, 0x19194, 2195 0x1919c, 0x191b0, 2196 0x191d0, 0x191e8, 2197 0x19238, 0x19290, 2198 0x192a4, 0x192b0, 2199 0x19348, 0x1934c, 2200 0x193f8, 0x19418, 2201 0x19420, 0x19428, 2202 0x19430, 0x19444, 2203 0x1944c, 0x1946c, 2204 0x19474, 0x19474, 2205 0x19490, 0x194cc, 2206 0x194f0, 0x194f8, 2207 0x19c00, 0x19c48, 2208 0x19c50, 0x19c80, 2209 0x19c94, 0x19c98, 2210 0x19ca0, 0x19cbc, 2211 0x19ce4, 0x19ce4, 2212 0x19cf0, 0x19cf8, 2213 0x19d00, 0x19d28, 2214 0x19d50, 0x19d78, 2215 0x19d94, 0x19d98, 2216 0x19da0, 0x19de0, 2217 0x19df0, 0x19e10, 2218 0x19e50, 0x19e6c, 2219 0x19ea0, 0x19ebc, 2220 0x19ec4, 0x19ef4, 2221 0x19f04, 0x19f2c, 2222 0x19f34, 0x19f34, 2223 0x19f40, 0x19f50, 2224 0x19f90, 0x19fac, 2225 0x19fc4, 0x19fc8, 2226 0x19fd0, 0x19fe4, 2227 0x1a000, 0x1a004, 2228 0x1a010, 0x1a06c, 2229 0x1a0b0, 0x1a0e4, 2230 0x1a0ec, 0x1a0f8, 2231 0x1a100, 0x1a108, 2232 0x1a114, 0x1a130, 2233 0x1a138, 0x1a1c4, 2234 0x1a1fc, 0x1a1fc, 2235 0x1e008, 0x1e00c, 2236 0x1e040, 0x1e044, 2237 0x1e04c, 0x1e04c, 2238 0x1e284, 0x1e290, 2239 0x1e2c0, 0x1e2c0, 2240 0x1e2e0, 0x1e2e0, 2241 0x1e300, 0x1e384, 2242 0x1e3c0, 0x1e3c8, 2243 0x1e408, 0x1e40c, 2244 0x1e440, 0x1e444, 2245 0x1e44c, 0x1e44c, 2246 0x1e684, 0x1e690, 2247 0x1e6c0, 0x1e6c0, 2248 0x1e6e0, 0x1e6e0, 2249 0x1e700, 0x1e784, 2250 0x1e7c0, 0x1e7c8, 2251 0x1e808, 0x1e80c, 2252 0x1e840, 0x1e844, 2253 0x1e84c, 0x1e84c, 2254 0x1ea84, 0x1ea90, 2255 0x1eac0, 0x1eac0, 2256 0x1eae0, 0x1eae0, 2257 0x1eb00, 0x1eb84, 2258 0x1ebc0, 0x1ebc8, 2259 0x1ec08, 0x1ec0c, 2260 0x1ec40, 0x1ec44, 2261 0x1ec4c, 0x1ec4c, 2262 0x1ee84, 0x1ee90, 2263 0x1eec0, 0x1eec0, 2264 0x1eee0, 0x1eee0, 2265 0x1ef00, 0x1ef84, 2266 0x1efc0, 0x1efc8, 2267 0x1f008, 0x1f00c, 2268 0x1f040, 0x1f044, 2269 0x1f04c, 0x1f04c, 2270 0x1f284, 0x1f290, 2271 0x1f2c0, 0x1f2c0, 2272 0x1f2e0, 0x1f2e0, 2273 0x1f300, 0x1f384, 2274 0x1f3c0, 0x1f3c8, 2275 0x1f408, 0x1f40c, 2276 0x1f440, 0x1f444, 2277 0x1f44c, 0x1f44c, 2278 0x1f684, 0x1f690, 2279 0x1f6c0, 0x1f6c0, 2280 0x1f6e0, 0x1f6e0, 2281 0x1f700, 0x1f784, 2282 0x1f7c0, 0x1f7c8, 2283 0x1f808, 0x1f80c, 2284 0x1f840, 0x1f844, 2285 0x1f84c, 0x1f84c, 2286 0x1fa84, 0x1fa90, 2287 0x1fac0, 0x1fac0, 2288 0x1fae0, 0x1fae0, 2289 0x1fb00, 0x1fb84, 2290 0x1fbc0, 0x1fbc8, 2291 0x1fc08, 0x1fc0c, 2292 0x1fc40, 0x1fc44, 2293 0x1fc4c, 0x1fc4c, 2294 0x1fe84, 0x1fe90, 2295 0x1fec0, 0x1fec0, 2296 0x1fee0, 0x1fee0, 2297 0x1ff00, 0x1ff84, 2298 0x1ffc0, 0x1ffc8, 2299 0x30000, 0x30030, 2300 0x30100, 0x30168, 2301 0x30190, 0x301a0, 2302 0x301a8, 0x301b8, 2303 0x301c4, 0x301c8, 2304 0x301d0, 0x301d0, 2305 0x30200, 0x30320, 2306 0x30400, 0x304b4, 2307 0x304c0, 0x3052c, 2308 0x30540, 0x3061c, 2309 0x30800, 0x308a0, 2310 0x308c0, 0x30908, 2311 0x30910, 0x309b8, 2312 0x30a00, 0x30a04, 2313 0x30a0c, 0x30a14, 2314 0x30a1c, 0x30a2c, 2315 0x30a44, 0x30a50, 2316 0x30a74, 0x30a74, 2317 0x30a7c, 0x30afc, 2318 0x30b08, 0x30c24, 2319 0x30d00, 0x30d14, 2320 0x30d1c, 0x30d3c, 2321 0x30d44, 0x30d4c, 2322 0x30d54, 0x30d74, 2323 0x30d7c, 0x30d7c, 2324 0x30de0, 0x30de0, 2325 0x30e00, 0x30ed4, 2326 0x30f00, 0x30fa4, 2327 0x30fc0, 0x30fc4, 2328 0x31000, 0x31004, 2329 0x31080, 0x310fc, 2330 0x31208, 0x31220, 2331 0x3123c, 0x31254, 2332 0x31300, 0x31300, 2333 0x31308, 0x3131c, 2334 0x31338, 0x3133c, 2335 0x31380, 0x31380, 2336 0x31388, 0x313a8, 2337 0x313b4, 0x313b4, 2338 0x31400, 0x31420, 2339 0x31438, 0x3143c, 2340 0x31480, 0x31480, 2341 0x314a8, 0x314a8, 2342 0x314b0, 0x314b4, 2343 0x314c8, 0x314d4, 2344 0x31a40, 0x31a4c, 2345 0x31af0, 0x31b20, 2346 0x31b38, 0x31b3c, 2347 0x31b80, 0x31b80, 2348 0x31ba8, 0x31ba8, 2349 0x31bb0, 0x31bb4, 2350 0x31bc8, 0x31bd4, 2351 0x32140, 0x3218c, 2352 0x321f0, 0x321f4, 2353 0x32200, 0x32200, 2354 0x32218, 0x32218, 2355 0x32400, 0x32400, 2356 0x32408, 0x3241c, 2357 0x32618, 0x32620, 2358 0x32664, 0x32664, 2359 0x326a8, 0x326a8, 2360 0x326ec, 0x326ec, 2361 0x32a00, 0x32abc, 2362 0x32b00, 0x32b18, 2363 0x32b20, 0x32b38, 2364 0x32b40, 0x32b58, 2365 0x32b60, 0x32b78, 2366 0x32c00, 0x32c00, 2367 0x32c08, 0x32c3c, 2368 0x33000, 0x3302c, 2369 0x33034, 0x33050, 2370 0x33058, 0x33058, 2371 0x33060, 0x3308c, 2372 0x3309c, 0x330ac, 2373 0x330c0, 0x330c0, 2374 0x330c8, 0x330d0, 2375 0x330d8, 0x330e0, 2376 0x330ec, 0x3312c, 2377 0x33134, 0x33150, 2378 0x33158, 0x33158, 2379 0x33160, 0x3318c, 2380 0x3319c, 0x331ac, 2381 0x331c0, 0x331c0, 2382 0x331c8, 0x331d0, 2383 0x331d8, 0x331e0, 2384 0x331ec, 0x33290, 2385 0x33298, 0x332c4, 2386 0x332e4, 0x33390, 2387 0x33398, 0x333c4, 2388 0x333e4, 0x3342c, 2389 0x33434, 0x33450, 2390 0x33458, 0x33458, 2391 0x33460, 0x3348c, 2392 0x3349c, 0x334ac, 2393 0x334c0, 0x334c0, 2394 0x334c8, 0x334d0, 2395 0x334d8, 0x334e0, 2396 0x334ec, 0x3352c, 2397 0x33534, 0x33550, 2398 0x33558, 0x33558, 2399 0x33560, 0x3358c, 2400 0x3359c, 0x335ac, 2401 0x335c0, 0x335c0, 2402 0x335c8, 0x335d0, 2403 0x335d8, 0x335e0, 2404 0x335ec, 0x33690, 2405 0x33698, 0x336c4, 2406 0x336e4, 0x33790, 2407 0x33798, 0x337c4, 2408 0x337e4, 0x337fc, 2409 0x33814, 0x33814, 2410 0x33854, 0x33868, 2411 0x33880, 0x3388c, 2412 0x338c0, 0x338d0, 2413 0x338e8, 0x338ec, 2414 0x33900, 0x3392c, 2415 0x33934, 0x33950, 2416 0x33958, 0x33958, 2417 0x33960, 0x3398c, 2418 0x3399c, 0x339ac, 2419 0x339c0, 0x339c0, 2420 0x339c8, 0x339d0, 2421 0x339d8, 0x339e0, 2422 0x339ec, 0x33a90, 2423 0x33a98, 0x33ac4, 2424 0x33ae4, 0x33b10, 2425 0x33b24, 0x33b28, 2426 0x33b38, 0x33b50, 2427 0x33bf0, 0x33c10, 2428 0x33c24, 0x33c28, 2429 0x33c38, 0x33c50, 2430 0x33cf0, 0x33cfc, 2431 0x34000, 0x34030, 2432 0x34100, 0x34168, 2433 0x34190, 0x341a0, 2434 0x341a8, 0x341b8, 2435 0x341c4, 0x341c8, 2436 0x341d0, 0x341d0, 2437 0x34200, 0x34320, 2438 0x34400, 0x344b4, 2439 0x344c0, 0x3452c, 2440 0x34540, 0x3461c, 2441 0x34800, 0x348a0, 2442 0x348c0, 0x34908, 2443 0x34910, 0x349b8, 2444 0x34a00, 0x34a04, 2445 0x34a0c, 0x34a14, 2446 0x34a1c, 0x34a2c, 2447 0x34a44, 0x34a50, 2448 0x34a74, 0x34a74, 2449 0x34a7c, 0x34afc, 2450 0x34b08, 0x34c24, 2451 0x34d00, 0x34d14, 2452 0x34d1c, 0x34d3c, 2453 0x34d44, 0x34d4c, 2454 0x34d54, 0x34d74, 2455 0x34d7c, 0x34d7c, 2456 0x34de0, 0x34de0, 2457 0x34e00, 0x34ed4, 2458 0x34f00, 0x34fa4, 2459 0x34fc0, 0x34fc4, 2460 0x35000, 0x35004, 2461 0x35080, 0x350fc, 2462 0x35208, 0x35220, 2463 0x3523c, 0x35254, 2464 0x35300, 0x35300, 2465 0x35308, 0x3531c, 2466 0x35338, 0x3533c, 2467 0x35380, 0x35380, 2468 0x35388, 0x353a8, 2469 0x353b4, 0x353b4, 2470 0x35400, 0x35420, 2471 0x35438, 0x3543c, 2472 0x35480, 0x35480, 2473 0x354a8, 0x354a8, 2474 0x354b0, 0x354b4, 2475 0x354c8, 0x354d4, 2476 0x35a40, 0x35a4c, 2477 0x35af0, 0x35b20, 2478 0x35b38, 0x35b3c, 2479 0x35b80, 0x35b80, 2480 0x35ba8, 0x35ba8, 2481 0x35bb0, 0x35bb4, 2482 0x35bc8, 0x35bd4, 2483 0x36140, 0x3618c, 2484 0x361f0, 0x361f4, 2485 0x36200, 0x36200, 2486 0x36218, 0x36218, 2487 0x36400, 0x36400, 2488 0x36408, 0x3641c, 2489 0x36618, 0x36620, 2490 0x36664, 0x36664, 2491 0x366a8, 0x366a8, 2492 0x366ec, 0x366ec, 2493 0x36a00, 0x36abc, 2494 0x36b00, 0x36b18, 2495 0x36b20, 0x36b38, 2496 0x36b40, 0x36b58, 2497 0x36b60, 0x36b78, 2498 0x36c00, 0x36c00, 2499 0x36c08, 0x36c3c, 2500 0x37000, 0x3702c, 2501 0x37034, 0x37050, 2502 0x37058, 0x37058, 2503 0x37060, 0x3708c, 2504 0x3709c, 0x370ac, 2505 0x370c0, 0x370c0, 2506 0x370c8, 0x370d0, 2507 0x370d8, 0x370e0, 2508 0x370ec, 0x3712c, 2509 0x37134, 0x37150, 2510 0x37158, 0x37158, 2511 0x37160, 0x3718c, 2512 0x3719c, 0x371ac, 2513 0x371c0, 0x371c0, 2514 0x371c8, 0x371d0, 2515 0x371d8, 0x371e0, 2516 0x371ec, 0x37290, 2517 0x37298, 0x372c4, 2518 0x372e4, 0x37390, 2519 0x37398, 0x373c4, 2520 0x373e4, 0x3742c, 2521 0x37434, 0x37450, 2522 0x37458, 0x37458, 2523 0x37460, 0x3748c, 2524 0x3749c, 0x374ac, 2525 0x374c0, 0x374c0, 2526 0x374c8, 0x374d0, 2527 0x374d8, 0x374e0, 2528 0x374ec, 0x3752c, 2529 0x37534, 0x37550, 2530 0x37558, 0x37558, 2531 0x37560, 0x3758c, 2532 0x3759c, 0x375ac, 2533 0x375c0, 0x375c0, 2534 0x375c8, 0x375d0, 2535 0x375d8, 0x375e0, 2536 0x375ec, 0x37690, 2537 0x37698, 0x376c4, 2538 0x376e4, 0x37790, 2539 0x37798, 0x377c4, 2540 0x377e4, 0x377fc, 2541 0x37814, 0x37814, 2542 0x37854, 0x37868, 2543 0x37880, 0x3788c, 2544 0x378c0, 0x378d0, 2545 0x378e8, 0x378ec, 2546 0x37900, 0x3792c, 2547 0x37934, 0x37950, 2548 0x37958, 0x37958, 2549 0x37960, 0x3798c, 2550 0x3799c, 0x379ac, 2551 0x379c0, 0x379c0, 2552 0x379c8, 0x379d0, 2553 0x379d8, 0x379e0, 2554 0x379ec, 0x37a90, 2555 0x37a98, 0x37ac4, 2556 0x37ae4, 0x37b10, 2557 0x37b24, 0x37b28, 2558 0x37b38, 0x37b50, 2559 0x37bf0, 0x37c10, 2560 0x37c24, 0x37c28, 2561 0x37c38, 0x37c50, 2562 0x37cf0, 0x37cfc, 2563 0x40040, 0x40040, 2564 0x40080, 0x40084, 2565 0x40100, 0x40100, 2566 0x40140, 0x401bc, 2567 0x40200, 0x40214, 2568 0x40228, 0x40228, 2569 0x40240, 0x40258, 2570 0x40280, 0x40280, 2571 0x40304, 0x40304, 2572 0x40330, 0x4033c, 2573 0x41304, 0x413c8, 2574 0x413d0, 0x413dc, 2575 0x413f0, 0x413f0, 2576 0x41400, 0x4140c, 2577 0x41414, 0x4141c, 2578 0x41480, 0x414d0, 2579 0x44000, 0x4407c, 2580 0x440c0, 0x441ac, 2581 0x441b4, 0x4427c, 2582 0x442c0, 0x443ac, 2583 0x443b4, 0x4447c, 2584 0x444c0, 0x445ac, 2585 0x445b4, 0x4467c, 2586 0x446c0, 0x447ac, 2587 0x447b4, 0x4487c, 2588 0x448c0, 0x449ac, 2589 0x449b4, 0x44a7c, 2590 0x44ac0, 0x44bac, 2591 0x44bb4, 0x44c7c, 2592 0x44cc0, 0x44dac, 2593 0x44db4, 0x44e7c, 2594 0x44ec0, 0x44fac, 2595 0x44fb4, 0x4507c, 2596 0x450c0, 0x451ac, 2597 0x451b4, 0x451fc, 2598 0x45800, 0x45804, 2599 0x45810, 0x45830, 2600 0x45840, 0x45860, 2601 0x45868, 0x45868, 2602 0x45880, 0x45884, 2603 0x458a0, 0x458b0, 2604 0x45a00, 0x45a04, 2605 0x45a10, 0x45a30, 2606 0x45a40, 0x45a60, 2607 0x45a68, 0x45a68, 2608 0x45a80, 0x45a84, 2609 0x45aa0, 0x45ab0, 2610 0x460c0, 0x460e4, 2611 0x47000, 0x4703c, 2612 0x47044, 0x4708c, 2613 0x47200, 0x47250, 2614 0x47400, 0x47408, 2615 0x47414, 0x47420, 2616 0x47600, 0x47618, 2617 0x47800, 0x47814, 2618 0x47820, 0x4782c, 2619 0x50000, 0x50084, 2620 0x50090, 0x500cc, 2621 0x50300, 0x50384, 2622 0x50400, 0x50400, 2623 0x50800, 0x50884, 2624 0x50890, 0x508cc, 2625 0x50b00, 0x50b84, 2626 0x50c00, 0x50c00, 2627 0x51000, 0x51020, 2628 0x51028, 0x510b0, 2629 0x51300, 0x51324, 2630 }; 2631 2632 static const unsigned int t6vf_reg_ranges[] = { 2633 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2634 VF_MPS_REG(A_MPS_VF_CTL), 2635 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2636 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2637 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2638 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2639 FW_T6VF_MBDATA_BASE_ADDR, 2640 FW_T6VF_MBDATA_BASE_ADDR + 2641 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2642 }; 2643 2644 u32 *buf_end = (u32 *)(buf + buf_size); 2645 const unsigned int *reg_ranges; 2646 int reg_ranges_size, range; 2647 unsigned int chip_version = chip_id(adap); 2648 2649 /* 2650 * Select the right set of register ranges to dump depending on the 2651 * adapter chip type. 2652 */ 2653 switch (chip_version) { 2654 case CHELSIO_T4: 2655 if (adap->flags & IS_VF) { 2656 reg_ranges = t4vf_reg_ranges; 2657 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2658 } else { 2659 reg_ranges = t4_reg_ranges; 2660 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2661 } 2662 break; 2663 2664 case CHELSIO_T5: 2665 if (adap->flags & IS_VF) { 2666 reg_ranges = t5vf_reg_ranges; 2667 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2668 } else { 2669 reg_ranges = t5_reg_ranges; 2670 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2671 } 2672 break; 2673 2674 case CHELSIO_T6: 2675 if (adap->flags & IS_VF) { 2676 reg_ranges = t6vf_reg_ranges; 2677 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2678 } else { 2679 reg_ranges = t6_reg_ranges; 2680 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2681 } 2682 break; 2683 2684 default: 2685 CH_ERR(adap, 2686 "Unsupported chip version %d\n", chip_version); 2687 return; 2688 } 2689 2690 /* 2691 * Clear the register buffer and insert the appropriate register 2692 * values selected by the above register ranges. 2693 */ 2694 memset(buf, 0, buf_size); 2695 for (range = 0; range < reg_ranges_size; range += 2) { 2696 unsigned int reg = reg_ranges[range]; 2697 unsigned int last_reg = reg_ranges[range + 1]; 2698 u32 *bufp = (u32 *)(buf + reg); 2699 2700 /* 2701 * Iterate across the register range filling in the register 2702 * buffer but don't write past the end of the register buffer. 2703 */ 2704 while (reg <= last_reg && bufp < buf_end) { 2705 *bufp++ = t4_read_reg(adap, reg); 2706 reg += sizeof(u32); 2707 } 2708 } 2709 } 2710 2711 /* 2712 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2713 * header followed by one or more VPD-R sections, each with its own header. 2714 */ 2715 struct t4_vpd_hdr { 2716 u8 id_tag; 2717 u8 id_len[2]; 2718 u8 id_data[ID_LEN]; 2719 }; 2720 2721 struct t4_vpdr_hdr { 2722 u8 vpdr_tag; 2723 u8 vpdr_len[2]; 2724 }; 2725 2726 /* 2727 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2728 */ 2729 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2730 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2731 2732 #define EEPROM_STAT_ADDR 0x7bfc 2733 #define VPD_SIZE 0x800 2734 #define VPD_BASE 0x400 2735 #define VPD_BASE_OLD 0 2736 #define VPD_LEN 1024 2737 #define VPD_INFO_FLD_HDR_SIZE 3 2738 #define CHELSIO_VPD_UNIQUE_ID 0x82 2739 2740 /* 2741 * Small utility function to wait till any outstanding VPD Access is complete. 2742 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2743 * VPD Access in flight. This allows us to handle the problem of having a 2744 * previous VPD Access time out and prevent an attempt to inject a new VPD 2745 * Request before any in-flight VPD reguest has completed. 2746 */ 2747 static int t4_seeprom_wait(struct adapter *adapter) 2748 { 2749 unsigned int base = adapter->params.pci.vpd_cap_addr; 2750 int max_poll; 2751 2752 /* 2753 * If no VPD Access is in flight, we can just return success right 2754 * away. 2755 */ 2756 if (!adapter->vpd_busy) 2757 return 0; 2758 2759 /* 2760 * Poll the VPD Capability Address/Flag register waiting for it 2761 * to indicate that the operation is complete. 2762 */ 2763 max_poll = EEPROM_MAX_POLL; 2764 do { 2765 u16 val; 2766 2767 udelay(EEPROM_DELAY); 2768 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2769 2770 /* 2771 * If the operation is complete, mark the VPD as no longer 2772 * busy and return success. 2773 */ 2774 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2775 adapter->vpd_busy = 0; 2776 return 0; 2777 } 2778 } while (--max_poll); 2779 2780 /* 2781 * Failure! Note that we leave the VPD Busy status set in order to 2782 * avoid pushing a new VPD Access request into the VPD Capability till 2783 * the current operation eventually succeeds. It's a bug to issue a 2784 * new request when an existing request is in flight and will result 2785 * in corrupt hardware state. 2786 */ 2787 return -ETIMEDOUT; 2788 } 2789 2790 /** 2791 * t4_seeprom_read - read a serial EEPROM location 2792 * @adapter: adapter to read 2793 * @addr: EEPROM virtual address 2794 * @data: where to store the read data 2795 * 2796 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2797 * VPD capability. Note that this function must be called with a virtual 2798 * address. 2799 */ 2800 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2801 { 2802 unsigned int base = adapter->params.pci.vpd_cap_addr; 2803 int ret; 2804 2805 /* 2806 * VPD Accesses must alway be 4-byte aligned! 2807 */ 2808 if (addr >= EEPROMVSIZE || (addr & 3)) 2809 return -EINVAL; 2810 2811 /* 2812 * Wait for any previous operation which may still be in flight to 2813 * complete. 2814 */ 2815 ret = t4_seeprom_wait(adapter); 2816 if (ret) { 2817 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2818 return ret; 2819 } 2820 2821 /* 2822 * Issue our new VPD Read request, mark the VPD as being busy and wait 2823 * for our request to complete. If it doesn't complete, note the 2824 * error and return it to our caller. Note that we do not reset the 2825 * VPD Busy status! 2826 */ 2827 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2828 adapter->vpd_busy = 1; 2829 adapter->vpd_flag = PCI_VPD_ADDR_F; 2830 ret = t4_seeprom_wait(adapter); 2831 if (ret) { 2832 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2833 return ret; 2834 } 2835 2836 /* 2837 * Grab the returned data, swizzle it into our endianness and 2838 * return success. 2839 */ 2840 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2841 *data = le32_to_cpu(*data); 2842 return 0; 2843 } 2844 2845 /** 2846 * t4_seeprom_write - write a serial EEPROM location 2847 * @adapter: adapter to write 2848 * @addr: virtual EEPROM address 2849 * @data: value to write 2850 * 2851 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2852 * VPD capability. Note that this function must be called with a virtual 2853 * address. 2854 */ 2855 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2856 { 2857 unsigned int base = adapter->params.pci.vpd_cap_addr; 2858 int ret; 2859 u32 stats_reg; 2860 int max_poll; 2861 2862 /* 2863 * VPD Accesses must alway be 4-byte aligned! 2864 */ 2865 if (addr >= EEPROMVSIZE || (addr & 3)) 2866 return -EINVAL; 2867 2868 /* 2869 * Wait for any previous operation which may still be in flight to 2870 * complete. 2871 */ 2872 ret = t4_seeprom_wait(adapter); 2873 if (ret) { 2874 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2875 return ret; 2876 } 2877 2878 /* 2879 * Issue our new VPD Read request, mark the VPD as being busy and wait 2880 * for our request to complete. If it doesn't complete, note the 2881 * error and return it to our caller. Note that we do not reset the 2882 * VPD Busy status! 2883 */ 2884 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2885 cpu_to_le32(data)); 2886 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2887 (u16)addr | PCI_VPD_ADDR_F); 2888 adapter->vpd_busy = 1; 2889 adapter->vpd_flag = 0; 2890 ret = t4_seeprom_wait(adapter); 2891 if (ret) { 2892 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2893 return ret; 2894 } 2895 2896 /* 2897 * Reset PCI_VPD_DATA register after a transaction and wait for our 2898 * request to complete. If it doesn't complete, return error. 2899 */ 2900 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2901 max_poll = EEPROM_MAX_POLL; 2902 do { 2903 udelay(EEPROM_DELAY); 2904 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2905 } while ((stats_reg & 0x1) && --max_poll); 2906 if (!max_poll) 2907 return -ETIMEDOUT; 2908 2909 /* Return success! */ 2910 return 0; 2911 } 2912 2913 /** 2914 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2915 * @phys_addr: the physical EEPROM address 2916 * @fn: the PCI function number 2917 * @sz: size of function-specific area 2918 * 2919 * Translate a physical EEPROM address to virtual. The first 1K is 2920 * accessed through virtual addresses starting at 31K, the rest is 2921 * accessed through virtual addresses starting at 0. 2922 * 2923 * The mapping is as follows: 2924 * [0..1K) -> [31K..32K) 2925 * [1K..1K+A) -> [ES-A..ES) 2926 * [1K+A..ES) -> [0..ES-A-1K) 2927 * 2928 * where A = @fn * @sz, and ES = EEPROM size. 2929 */ 2930 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2931 { 2932 fn *= sz; 2933 if (phys_addr < 1024) 2934 return phys_addr + (31 << 10); 2935 if (phys_addr < 1024 + fn) 2936 return EEPROMSIZE - fn + phys_addr - 1024; 2937 if (phys_addr < EEPROMSIZE) 2938 return phys_addr - 1024 - fn; 2939 return -EINVAL; 2940 } 2941 2942 /** 2943 * t4_seeprom_wp - enable/disable EEPROM write protection 2944 * @adapter: the adapter 2945 * @enable: whether to enable or disable write protection 2946 * 2947 * Enables or disables write protection on the serial EEPROM. 2948 */ 2949 int t4_seeprom_wp(struct adapter *adapter, int enable) 2950 { 2951 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2952 } 2953 2954 /** 2955 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2956 * @vpd: Pointer to buffered vpd data structure 2957 * @kw: The keyword to search for 2958 * @region: VPD region to search (starting from 0) 2959 * 2960 * Returns the value of the information field keyword or 2961 * -ENOENT otherwise. 2962 */ 2963 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2964 { 2965 int i, tag; 2966 unsigned int offset, len; 2967 const struct t4_vpdr_hdr *vpdr; 2968 2969 offset = sizeof(struct t4_vpd_hdr); 2970 vpdr = (const void *)(vpd + offset); 2971 tag = vpdr->vpdr_tag; 2972 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2973 while (region--) { 2974 offset += sizeof(struct t4_vpdr_hdr) + len; 2975 vpdr = (const void *)(vpd + offset); 2976 if (++tag != vpdr->vpdr_tag) 2977 return -ENOENT; 2978 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2979 } 2980 offset += sizeof(struct t4_vpdr_hdr); 2981 2982 if (offset + len > VPD_LEN) { 2983 return -ENOENT; 2984 } 2985 2986 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2987 if (memcmp(vpd + i , kw , 2) == 0){ 2988 i += VPD_INFO_FLD_HDR_SIZE; 2989 return i; 2990 } 2991 2992 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2993 } 2994 2995 return -ENOENT; 2996 } 2997 2998 2999 /** 3000 * get_vpd_params - read VPD parameters from VPD EEPROM 3001 * @adapter: adapter to read 3002 * @p: where to store the parameters 3003 * @vpd: caller provided temporary space to read the VPD into 3004 * 3005 * Reads card parameters stored in VPD EEPROM. 3006 */ 3007 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3008 uint16_t device_id, u32 *buf) 3009 { 3010 int i, ret, addr; 3011 int ec, sn, pn, na, md; 3012 u8 csum; 3013 const u8 *vpd = (const u8 *)buf; 3014 3015 /* 3016 * Card information normally starts at VPD_BASE but early cards had 3017 * it at 0. 3018 */ 3019 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3020 if (ret) 3021 return (ret); 3022 3023 /* 3024 * The VPD shall have a unique identifier specified by the PCI SIG. 3025 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3026 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3027 * is expected to automatically put this entry at the 3028 * beginning of the VPD. 3029 */ 3030 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3031 3032 for (i = 0; i < VPD_LEN; i += 4) { 3033 ret = t4_seeprom_read(adapter, addr + i, buf++); 3034 if (ret) 3035 return ret; 3036 } 3037 3038 #define FIND_VPD_KW(var,name) do { \ 3039 var = get_vpd_keyword_val(vpd, name, 0); \ 3040 if (var < 0) { \ 3041 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3042 return -EINVAL; \ 3043 } \ 3044 } while (0) 3045 3046 FIND_VPD_KW(i, "RV"); 3047 for (csum = 0; i >= 0; i--) 3048 csum += vpd[i]; 3049 3050 if (csum) { 3051 CH_ERR(adapter, 3052 "corrupted VPD EEPROM, actual csum %u\n", csum); 3053 return -EINVAL; 3054 } 3055 3056 FIND_VPD_KW(ec, "EC"); 3057 FIND_VPD_KW(sn, "SN"); 3058 FIND_VPD_KW(pn, "PN"); 3059 FIND_VPD_KW(na, "NA"); 3060 #undef FIND_VPD_KW 3061 3062 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3063 strstrip(p->id); 3064 memcpy(p->ec, vpd + ec, EC_LEN); 3065 strstrip(p->ec); 3066 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3067 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3068 strstrip(p->sn); 3069 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3070 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3071 strstrip((char *)p->pn); 3072 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3073 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3074 strstrip((char *)p->na); 3075 3076 if (device_id & 0x80) 3077 return 0; /* Custom card */ 3078 3079 md = get_vpd_keyword_val(vpd, "VF", 1); 3080 if (md < 0) { 3081 snprintf(p->md, sizeof(p->md), "unknown"); 3082 } else { 3083 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3084 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3085 strstrip((char *)p->md); 3086 } 3087 3088 return 0; 3089 } 3090 3091 /* serial flash and firmware constants and flash config file constants */ 3092 enum { 3093 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3094 3095 /* flash command opcodes */ 3096 SF_PROG_PAGE = 2, /* program 256B page */ 3097 SF_WR_DISABLE = 4, /* disable writes */ 3098 SF_RD_STATUS = 5, /* read status register */ 3099 SF_WR_ENABLE = 6, /* enable writes */ 3100 SF_RD_DATA_FAST = 0xb, /* read flash */ 3101 SF_RD_ID = 0x9f, /* read ID */ 3102 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3103 }; 3104 3105 /** 3106 * sf1_read - read data from the serial flash 3107 * @adapter: the adapter 3108 * @byte_cnt: number of bytes to read 3109 * @cont: whether another operation will be chained 3110 * @lock: whether to lock SF for PL access only 3111 * @valp: where to store the read data 3112 * 3113 * Reads up to 4 bytes of data from the serial flash. The location of 3114 * the read needs to be specified prior to calling this by issuing the 3115 * appropriate commands to the serial flash. 3116 */ 3117 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3118 int lock, u32 *valp) 3119 { 3120 int ret; 3121 3122 if (!byte_cnt || byte_cnt > 4) 3123 return -EINVAL; 3124 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3125 return -EBUSY; 3126 t4_write_reg(adapter, A_SF_OP, 3127 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3128 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3129 if (!ret) 3130 *valp = t4_read_reg(adapter, A_SF_DATA); 3131 return ret; 3132 } 3133 3134 /** 3135 * sf1_write - write data to the serial flash 3136 * @adapter: the adapter 3137 * @byte_cnt: number of bytes to write 3138 * @cont: whether another operation will be chained 3139 * @lock: whether to lock SF for PL access only 3140 * @val: value to write 3141 * 3142 * Writes up to 4 bytes of data to the serial flash. The location of 3143 * the write needs to be specified prior to calling this by issuing the 3144 * appropriate commands to the serial flash. 3145 */ 3146 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3147 int lock, u32 val) 3148 { 3149 if (!byte_cnt || byte_cnt > 4) 3150 return -EINVAL; 3151 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3152 return -EBUSY; 3153 t4_write_reg(adapter, A_SF_DATA, val); 3154 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3155 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3156 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3157 } 3158 3159 /** 3160 * flash_wait_op - wait for a flash operation to complete 3161 * @adapter: the adapter 3162 * @attempts: max number of polls of the status register 3163 * @delay: delay between polls in ms 3164 * 3165 * Wait for a flash operation to complete by polling the status register. 3166 */ 3167 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3168 { 3169 int ret; 3170 u32 status; 3171 3172 while (1) { 3173 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3174 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3175 return ret; 3176 if (!(status & 1)) 3177 return 0; 3178 if (--attempts == 0) 3179 return -EAGAIN; 3180 if (delay) 3181 msleep(delay); 3182 } 3183 } 3184 3185 /** 3186 * t4_read_flash - read words from serial flash 3187 * @adapter: the adapter 3188 * @addr: the start address for the read 3189 * @nwords: how many 32-bit words to read 3190 * @data: where to store the read data 3191 * @byte_oriented: whether to store data as bytes or as words 3192 * 3193 * Read the specified number of 32-bit words from the serial flash. 3194 * If @byte_oriented is set the read data is stored as a byte array 3195 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3196 * natural endianness. 3197 */ 3198 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3199 unsigned int nwords, u32 *data, int byte_oriented) 3200 { 3201 int ret; 3202 3203 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3204 return -EINVAL; 3205 3206 addr = swab32(addr) | SF_RD_DATA_FAST; 3207 3208 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3209 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3210 return ret; 3211 3212 for ( ; nwords; nwords--, data++) { 3213 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3214 if (nwords == 1) 3215 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3216 if (ret) 3217 return ret; 3218 if (byte_oriented) 3219 *data = (__force __u32)(cpu_to_be32(*data)); 3220 } 3221 return 0; 3222 } 3223 3224 /** 3225 * t4_write_flash - write up to a page of data to the serial flash 3226 * @adapter: the adapter 3227 * @addr: the start address to write 3228 * @n: length of data to write in bytes 3229 * @data: the data to write 3230 * @byte_oriented: whether to store data as bytes or as words 3231 * 3232 * Writes up to a page of data (256 bytes) to the serial flash starting 3233 * at the given address. All the data must be written to the same page. 3234 * If @byte_oriented is set the write data is stored as byte stream 3235 * (i.e. matches what on disk), otherwise in big-endian. 3236 */ 3237 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3238 unsigned int n, const u8 *data, int byte_oriented) 3239 { 3240 int ret; 3241 u32 buf[SF_PAGE_SIZE / 4]; 3242 unsigned int i, c, left, val, offset = addr & 0xff; 3243 3244 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3245 return -EINVAL; 3246 3247 val = swab32(addr) | SF_PROG_PAGE; 3248 3249 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3250 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3251 goto unlock; 3252 3253 for (left = n; left; left -= c) { 3254 c = min(left, 4U); 3255 for (val = 0, i = 0; i < c; ++i) 3256 val = (val << 8) + *data++; 3257 3258 if (!byte_oriented) 3259 val = cpu_to_be32(val); 3260 3261 ret = sf1_write(adapter, c, c != left, 1, val); 3262 if (ret) 3263 goto unlock; 3264 } 3265 ret = flash_wait_op(adapter, 8, 1); 3266 if (ret) 3267 goto unlock; 3268 3269 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3270 3271 /* Read the page to verify the write succeeded */ 3272 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3273 byte_oriented); 3274 if (ret) 3275 return ret; 3276 3277 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3278 CH_ERR(adapter, 3279 "failed to correctly write the flash page at %#x\n", 3280 addr); 3281 return -EIO; 3282 } 3283 return 0; 3284 3285 unlock: 3286 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3287 return ret; 3288 } 3289 3290 /** 3291 * t4_get_fw_version - read the firmware version 3292 * @adapter: the adapter 3293 * @vers: where to place the version 3294 * 3295 * Reads the FW version from flash. 3296 */ 3297 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3298 { 3299 return t4_read_flash(adapter, FLASH_FW_START + 3300 offsetof(struct fw_hdr, fw_ver), 1, 3301 vers, 0); 3302 } 3303 3304 /** 3305 * t4_get_fw_hdr - read the firmware header 3306 * @adapter: the adapter 3307 * @hdr: where to place the version 3308 * 3309 * Reads the FW header from flash into caller provided buffer. 3310 */ 3311 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3312 { 3313 return t4_read_flash(adapter, FLASH_FW_START, 3314 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3315 } 3316 3317 /** 3318 * t4_get_bs_version - read the firmware bootstrap version 3319 * @adapter: the adapter 3320 * @vers: where to place the version 3321 * 3322 * Reads the FW Bootstrap version from flash. 3323 */ 3324 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3325 { 3326 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3327 offsetof(struct fw_hdr, fw_ver), 1, 3328 vers, 0); 3329 } 3330 3331 /** 3332 * t4_get_tp_version - read the TP microcode version 3333 * @adapter: the adapter 3334 * @vers: where to place the version 3335 * 3336 * Reads the TP microcode version from flash. 3337 */ 3338 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3339 { 3340 return t4_read_flash(adapter, FLASH_FW_START + 3341 offsetof(struct fw_hdr, tp_microcode_ver), 3342 1, vers, 0); 3343 } 3344 3345 /** 3346 * t4_get_exprom_version - return the Expansion ROM version (if any) 3347 * @adapter: the adapter 3348 * @vers: where to place the version 3349 * 3350 * Reads the Expansion ROM header from FLASH and returns the version 3351 * number (if present) through the @vers return value pointer. We return 3352 * this in the Firmware Version Format since it's convenient. Return 3353 * 0 on success, -ENOENT if no Expansion ROM is present. 3354 */ 3355 int t4_get_exprom_version(struct adapter *adapter, u32 *vers) 3356 { 3357 struct exprom_header { 3358 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3359 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3360 } *hdr; 3361 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3362 sizeof(u32))]; 3363 int ret; 3364 3365 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START, 3366 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3367 0); 3368 if (ret) 3369 return ret; 3370 3371 hdr = (struct exprom_header *)exprom_header_buf; 3372 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3373 return -ENOENT; 3374 3375 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3376 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3377 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3378 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3379 return 0; 3380 } 3381 3382 /** 3383 * t4_get_scfg_version - return the Serial Configuration version 3384 * @adapter: the adapter 3385 * @vers: where to place the version 3386 * 3387 * Reads the Serial Configuration Version via the Firmware interface 3388 * (thus this can only be called once we're ready to issue Firmware 3389 * commands). The format of the Serial Configuration version is 3390 * adapter specific. Returns 0 on success, an error on failure. 3391 * 3392 * Note that early versions of the Firmware didn't include the ability 3393 * to retrieve the Serial Configuration version, so we zero-out the 3394 * return-value parameter in that case to avoid leaving it with 3395 * garbage in it. 3396 * 3397 * Also note that the Firmware will return its cached copy of the Serial 3398 * Initialization Revision ID, not the actual Revision ID as written in 3399 * the Serial EEPROM. This is only an issue if a new VPD has been written 3400 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3401 * it's best to defer calling this routine till after a FW_RESET_CMD has 3402 * been issued if the Host Driver will be performing a full adapter 3403 * initialization. 3404 */ 3405 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3406 { 3407 u32 scfgrev_param; 3408 int ret; 3409 3410 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3411 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3412 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3413 1, &scfgrev_param, vers); 3414 if (ret) 3415 *vers = 0; 3416 return ret; 3417 } 3418 3419 /** 3420 * t4_get_vpd_version - return the VPD version 3421 * @adapter: the adapter 3422 * @vers: where to place the version 3423 * 3424 * Reads the VPD via the Firmware interface (thus this can only be called 3425 * once we're ready to issue Firmware commands). The format of the 3426 * VPD version is adapter specific. Returns 0 on success, an error on 3427 * failure. 3428 * 3429 * Note that early versions of the Firmware didn't include the ability 3430 * to retrieve the VPD version, so we zero-out the return-value parameter 3431 * in that case to avoid leaving it with garbage in it. 3432 * 3433 * Also note that the Firmware will return its cached copy of the VPD 3434 * Revision ID, not the actual Revision ID as written in the Serial 3435 * EEPROM. This is only an issue if a new VPD has been written and the 3436 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3437 * to defer calling this routine till after a FW_RESET_CMD has been issued 3438 * if the Host Driver will be performing a full adapter initialization. 3439 */ 3440 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3441 { 3442 u32 vpdrev_param; 3443 int ret; 3444 3445 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3446 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3447 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3448 1, &vpdrev_param, vers); 3449 if (ret) 3450 *vers = 0; 3451 return ret; 3452 } 3453 3454 /** 3455 * t4_get_version_info - extract various chip/firmware version information 3456 * @adapter: the adapter 3457 * 3458 * Reads various chip/firmware version numbers and stores them into the 3459 * adapter Adapter Parameters structure. If any of the efforts fails 3460 * the first failure will be returned, but all of the version numbers 3461 * will be read. 3462 */ 3463 int t4_get_version_info(struct adapter *adapter) 3464 { 3465 int ret = 0; 3466 3467 #define FIRST_RET(__getvinfo) \ 3468 do { \ 3469 int __ret = __getvinfo; \ 3470 if (__ret && !ret) \ 3471 ret = __ret; \ 3472 } while (0) 3473 3474 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3475 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3476 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3477 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3478 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3479 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3480 3481 #undef FIRST_RET 3482 3483 return ret; 3484 } 3485 3486 /** 3487 * t4_flash_erase_sectors - erase a range of flash sectors 3488 * @adapter: the adapter 3489 * @start: the first sector to erase 3490 * @end: the last sector to erase 3491 * 3492 * Erases the sectors in the given inclusive range. 3493 */ 3494 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3495 { 3496 int ret = 0; 3497 3498 if (end >= adapter->params.sf_nsec) 3499 return -EINVAL; 3500 3501 while (start <= end) { 3502 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3503 (ret = sf1_write(adapter, 4, 0, 1, 3504 SF_ERASE_SECTOR | (start << 8))) != 0 || 3505 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3506 CH_ERR(adapter, 3507 "erase of flash sector %d failed, error %d\n", 3508 start, ret); 3509 break; 3510 } 3511 start++; 3512 } 3513 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3514 return ret; 3515 } 3516 3517 /** 3518 * t4_flash_cfg_addr - return the address of the flash configuration file 3519 * @adapter: the adapter 3520 * 3521 * Return the address within the flash where the Firmware Configuration 3522 * File is stored, or an error if the device FLASH is too small to contain 3523 * a Firmware Configuration File. 3524 */ 3525 int t4_flash_cfg_addr(struct adapter *adapter) 3526 { 3527 /* 3528 * If the device FLASH isn't large enough to hold a Firmware 3529 * Configuration File, return an error. 3530 */ 3531 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3532 return -ENOSPC; 3533 3534 return FLASH_CFG_START; 3535 } 3536 3537 /* 3538 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3539 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3540 * and emit an error message for mismatched firmware to save our caller the 3541 * effort ... 3542 */ 3543 static int t4_fw_matches_chip(struct adapter *adap, 3544 const struct fw_hdr *hdr) 3545 { 3546 /* 3547 * The expression below will return FALSE for any unsupported adapter 3548 * which will keep us "honest" in the future ... 3549 */ 3550 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3551 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3552 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3553 return 1; 3554 3555 CH_ERR(adap, 3556 "FW image (%d) is not suitable for this adapter (%d)\n", 3557 hdr->chip, chip_id(adap)); 3558 return 0; 3559 } 3560 3561 /** 3562 * t4_load_fw - download firmware 3563 * @adap: the adapter 3564 * @fw_data: the firmware image to write 3565 * @size: image size 3566 * 3567 * Write the supplied firmware image to the card's serial flash. 3568 */ 3569 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3570 { 3571 u32 csum; 3572 int ret, addr; 3573 unsigned int i; 3574 u8 first_page[SF_PAGE_SIZE]; 3575 const u32 *p = (const u32 *)fw_data; 3576 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3577 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3578 unsigned int fw_start_sec; 3579 unsigned int fw_start; 3580 unsigned int fw_size; 3581 3582 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3583 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3584 fw_start = FLASH_FWBOOTSTRAP_START; 3585 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3586 } else { 3587 fw_start_sec = FLASH_FW_START_SEC; 3588 fw_start = FLASH_FW_START; 3589 fw_size = FLASH_FW_MAX_SIZE; 3590 } 3591 3592 if (!size) { 3593 CH_ERR(adap, "FW image has no data\n"); 3594 return -EINVAL; 3595 } 3596 if (size & 511) { 3597 CH_ERR(adap, 3598 "FW image size not multiple of 512 bytes\n"); 3599 return -EINVAL; 3600 } 3601 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3602 CH_ERR(adap, 3603 "FW image size differs from size in FW header\n"); 3604 return -EINVAL; 3605 } 3606 if (size > fw_size) { 3607 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3608 fw_size); 3609 return -EFBIG; 3610 } 3611 if (!t4_fw_matches_chip(adap, hdr)) 3612 return -EINVAL; 3613 3614 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3615 csum += be32_to_cpu(p[i]); 3616 3617 if (csum != 0xffffffff) { 3618 CH_ERR(adap, 3619 "corrupted firmware image, checksum %#x\n", csum); 3620 return -EINVAL; 3621 } 3622 3623 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3624 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3625 if (ret) 3626 goto out; 3627 3628 /* 3629 * We write the correct version at the end so the driver can see a bad 3630 * version if the FW write fails. Start by writing a copy of the 3631 * first page with a bad version. 3632 */ 3633 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3634 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3635 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3636 if (ret) 3637 goto out; 3638 3639 addr = fw_start; 3640 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3641 addr += SF_PAGE_SIZE; 3642 fw_data += SF_PAGE_SIZE; 3643 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3644 if (ret) 3645 goto out; 3646 } 3647 3648 ret = t4_write_flash(adap, 3649 fw_start + offsetof(struct fw_hdr, fw_ver), 3650 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3651 out: 3652 if (ret) 3653 CH_ERR(adap, "firmware download failed, error %d\n", 3654 ret); 3655 return ret; 3656 } 3657 3658 /** 3659 * t4_fwcache - firmware cache operation 3660 * @adap: the adapter 3661 * @op : the operation (flush or flush and invalidate) 3662 */ 3663 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3664 { 3665 struct fw_params_cmd c; 3666 3667 memset(&c, 0, sizeof(c)); 3668 c.op_to_vfn = 3669 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3670 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3671 V_FW_PARAMS_CMD_PFN(adap->pf) | 3672 V_FW_PARAMS_CMD_VFN(0)); 3673 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3674 c.param[0].mnem = 3675 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3676 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3677 c.param[0].val = (__force __be32)op; 3678 3679 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3680 } 3681 3682 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3683 unsigned int *pif_req_wrptr, 3684 unsigned int *pif_rsp_wrptr) 3685 { 3686 int i, j; 3687 u32 cfg, val, req, rsp; 3688 3689 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3690 if (cfg & F_LADBGEN) 3691 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3692 3693 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3694 req = G_POLADBGWRPTR(val); 3695 rsp = G_PILADBGWRPTR(val); 3696 if (pif_req_wrptr) 3697 *pif_req_wrptr = req; 3698 if (pif_rsp_wrptr) 3699 *pif_rsp_wrptr = rsp; 3700 3701 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3702 for (j = 0; j < 6; j++) { 3703 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3704 V_PILADBGRDPTR(rsp)); 3705 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3706 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3707 req++; 3708 rsp++; 3709 } 3710 req = (req + 2) & M_POLADBGRDPTR; 3711 rsp = (rsp + 2) & M_PILADBGRDPTR; 3712 } 3713 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3714 } 3715 3716 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3717 { 3718 u32 cfg; 3719 int i, j, idx; 3720 3721 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3722 if (cfg & F_LADBGEN) 3723 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3724 3725 for (i = 0; i < CIM_MALA_SIZE; i++) { 3726 for (j = 0; j < 5; j++) { 3727 idx = 8 * i + j; 3728 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3729 V_PILADBGRDPTR(idx)); 3730 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3731 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3732 } 3733 } 3734 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3735 } 3736 3737 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3738 { 3739 unsigned int i, j; 3740 3741 for (i = 0; i < 8; i++) { 3742 u32 *p = la_buf + i; 3743 3744 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3745 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3746 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3747 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3748 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3749 } 3750 } 3751 3752 /** 3753 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3754 * @caps16: a 16-bit Port Capabilities value 3755 * 3756 * Returns the equivalent 32-bit Port Capabilities value. 3757 */ 3758 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3759 { 3760 uint32_t caps32 = 0; 3761 3762 #define CAP16_TO_CAP32(__cap) \ 3763 do { \ 3764 if (caps16 & FW_PORT_CAP_##__cap) \ 3765 caps32 |= FW_PORT_CAP32_##__cap; \ 3766 } while (0) 3767 3768 CAP16_TO_CAP32(SPEED_100M); 3769 CAP16_TO_CAP32(SPEED_1G); 3770 CAP16_TO_CAP32(SPEED_25G); 3771 CAP16_TO_CAP32(SPEED_10G); 3772 CAP16_TO_CAP32(SPEED_40G); 3773 CAP16_TO_CAP32(SPEED_100G); 3774 CAP16_TO_CAP32(FC_RX); 3775 CAP16_TO_CAP32(FC_TX); 3776 CAP16_TO_CAP32(ANEG); 3777 CAP16_TO_CAP32(FORCE_PAUSE); 3778 CAP16_TO_CAP32(MDIAUTO); 3779 CAP16_TO_CAP32(MDISTRAIGHT); 3780 CAP16_TO_CAP32(FEC_RS); 3781 CAP16_TO_CAP32(FEC_BASER_RS); 3782 CAP16_TO_CAP32(802_3_PAUSE); 3783 CAP16_TO_CAP32(802_3_ASM_DIR); 3784 3785 #undef CAP16_TO_CAP32 3786 3787 return caps32; 3788 } 3789 3790 /** 3791 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3792 * @caps32: a 32-bit Port Capabilities value 3793 * 3794 * Returns the equivalent 16-bit Port Capabilities value. Note that 3795 * not all 32-bit Port Capabilities can be represented in the 16-bit 3796 * Port Capabilities and some fields/values may not make it. 3797 */ 3798 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3799 { 3800 uint16_t caps16 = 0; 3801 3802 #define CAP32_TO_CAP16(__cap) \ 3803 do { \ 3804 if (caps32 & FW_PORT_CAP32_##__cap) \ 3805 caps16 |= FW_PORT_CAP_##__cap; \ 3806 } while (0) 3807 3808 CAP32_TO_CAP16(SPEED_100M); 3809 CAP32_TO_CAP16(SPEED_1G); 3810 CAP32_TO_CAP16(SPEED_10G); 3811 CAP32_TO_CAP16(SPEED_25G); 3812 CAP32_TO_CAP16(SPEED_40G); 3813 CAP32_TO_CAP16(SPEED_100G); 3814 CAP32_TO_CAP16(FC_RX); 3815 CAP32_TO_CAP16(FC_TX); 3816 CAP32_TO_CAP16(802_3_PAUSE); 3817 CAP32_TO_CAP16(802_3_ASM_DIR); 3818 CAP32_TO_CAP16(ANEG); 3819 CAP32_TO_CAP16(FORCE_PAUSE); 3820 CAP32_TO_CAP16(MDIAUTO); 3821 CAP32_TO_CAP16(MDISTRAIGHT); 3822 CAP32_TO_CAP16(FEC_RS); 3823 CAP32_TO_CAP16(FEC_BASER_RS); 3824 3825 #undef CAP32_TO_CAP16 3826 3827 return caps16; 3828 } 3829 3830 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none) 3831 { 3832 int8_t fec = 0; 3833 3834 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0) 3835 return (unset_means_none ? FEC_NONE : 0); 3836 3837 if (caps & FW_PORT_CAP32_FEC_RS) 3838 fec |= FEC_RS; 3839 if (caps & FW_PORT_CAP32_FEC_BASER_RS) 3840 fec |= FEC_BASER_RS; 3841 if (caps & FW_PORT_CAP32_FEC_NO_FEC) 3842 fec |= FEC_NONE; 3843 3844 return (fec); 3845 } 3846 3847 /* 3848 * Note that 0 is not translated to NO_FEC. 3849 */ 3850 static uint32_t fec_to_fwcap(int8_t fec) 3851 { 3852 uint32_t caps = 0; 3853 3854 /* Only real FECs allowed. */ 3855 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0); 3856 3857 if (fec & FEC_RS) 3858 caps |= FW_PORT_CAP32_FEC_RS; 3859 if (fec & FEC_BASER_RS) 3860 caps |= FW_PORT_CAP32_FEC_BASER_RS; 3861 if (fec & FEC_NONE) 3862 caps |= FW_PORT_CAP32_FEC_NO_FEC; 3863 3864 return (caps); 3865 } 3866 3867 /** 3868 * t4_link_l1cfg - apply link configuration to MAC/PHY 3869 * @phy: the PHY to setup 3870 * @mac: the MAC to setup 3871 * @lc: the requested link configuration 3872 * 3873 * Set up a port's MAC and PHY according to a desired link configuration. 3874 * - If the PHY can auto-negotiate first decide what to advertise, then 3875 * enable/disable auto-negotiation as desired, and reset. 3876 * - If the PHY does not auto-negotiate just reset it. 3877 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3878 * otherwise do it later based on the outcome of auto-negotiation. 3879 */ 3880 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3881 struct link_config *lc) 3882 { 3883 struct fw_port_cmd c; 3884 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3885 unsigned int aneg, fc, fec, speed, rcap; 3886 3887 fc = 0; 3888 if (lc->requested_fc & PAUSE_RX) 3889 fc |= FW_PORT_CAP32_FC_RX; 3890 if (lc->requested_fc & PAUSE_TX) 3891 fc |= FW_PORT_CAP32_FC_TX; 3892 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3893 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3894 3895 if (lc->requested_aneg == AUTONEG_DISABLE) 3896 aneg = 0; 3897 else if (lc->requested_aneg == AUTONEG_ENABLE) 3898 aneg = FW_PORT_CAP32_ANEG; 3899 else 3900 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3901 3902 if (aneg) { 3903 speed = lc->pcaps & 3904 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3905 } else if (lc->requested_speed != 0) 3906 speed = speed_to_fwcap(lc->requested_speed); 3907 else 3908 speed = fwcap_top_speed(lc->pcaps); 3909 3910 fec = 0; 3911 #ifdef INVARIANTS 3912 if (lc->force_fec != 0) 3913 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_FEC); 3914 #endif 3915 if (fec_supported(speed)) { 3916 if (lc->requested_fec == FEC_AUTO) { 3917 if (lc->force_fec > 0) { 3918 /* 3919 * Must use FORCE_FEC even though requested FEC 3920 * is AUTO. Set all the FEC bits valid for the 3921 * speed and let the firmware pick one. 3922 */ 3923 fec |= FW_PORT_CAP32_FORCE_FEC; 3924 if (speed & FW_PORT_CAP32_SPEED_100G) { 3925 fec |= FW_PORT_CAP32_FEC_RS; 3926 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3927 } else if (speed & FW_PORT_CAP32_SPEED_50G) { 3928 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3929 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3930 } else { 3931 fec |= FW_PORT_CAP32_FEC_RS; 3932 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3933 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3934 } 3935 } else { 3936 /* 3937 * Set only 1b. Old firmwares can't deal with 3938 * multiple bits and new firmwares are free to 3939 * ignore this and try whatever FECs they want 3940 * because we aren't setting FORCE_FEC here. 3941 */ 3942 fec |= fec_to_fwcap(lc->fec_hint); 3943 MPASS(powerof2(fec)); 3944 3945 /* 3946 * Override the hint if the FEC is not valid for 3947 * the potential top speed. Request the best 3948 * FEC at that speed instead. 3949 */ 3950 if (speed & FW_PORT_CAP32_SPEED_100G && 3951 fec == FW_PORT_CAP32_FEC_BASER_RS) 3952 fec = FW_PORT_CAP32_FEC_RS; 3953 else if (speed & FW_PORT_CAP32_SPEED_50G && 3954 fec == FW_PORT_CAP32_FEC_RS) 3955 fec = FW_PORT_CAP32_FEC_BASER_RS; 3956 } 3957 } else { 3958 /* 3959 * User has explicitly requested some FEC(s). Set 3960 * FORCE_FEC unless prohibited from using it. 3961 */ 3962 if (lc->force_fec != 0) 3963 fec |= FW_PORT_CAP32_FORCE_FEC; 3964 fec |= fec_to_fwcap(lc->requested_fec & 3965 M_FW_PORT_CAP32_FEC); 3966 if (lc->requested_fec & FEC_MODULE) 3967 fec |= fec_to_fwcap(lc->fec_hint); 3968 } 3969 3970 /* 3971 * This is for compatibility with old firmwares. The original 3972 * way to request NO_FEC was to not set any of the FEC bits. New 3973 * firmwares understand this too. 3974 */ 3975 if (fec == FW_PORT_CAP32_FEC_NO_FEC) 3976 fec = 0; 3977 } 3978 3979 /* Force AN on for BT cards. */ 3980 if (isset(&adap->bt_map, port)) 3981 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3982 3983 rcap = aneg | speed | fc | fec; 3984 if ((rcap | lc->pcaps) != lc->pcaps) { 3985 #ifdef INVARIANTS 3986 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap, 3987 lc->pcaps, rcap & (rcap ^ lc->pcaps)); 3988 #endif 3989 rcap &= lc->pcaps; 3990 } 3991 rcap |= mdi; 3992 3993 memset(&c, 0, sizeof(c)); 3994 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3995 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3996 V_FW_PORT_CMD_PORTID(port)); 3997 if (adap->params.port_caps32) { 3998 c.action_to_len16 = 3999 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 4000 FW_LEN16(c)); 4001 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 4002 } else { 4003 c.action_to_len16 = 4004 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4005 FW_LEN16(c)); 4006 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 4007 } 4008 4009 lc->requested_caps = rcap; 4010 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 4011 } 4012 4013 /** 4014 * t4_restart_aneg - restart autonegotiation 4015 * @adap: the adapter 4016 * @mbox: mbox to use for the FW command 4017 * @port: the port id 4018 * 4019 * Restarts autonegotiation for the selected port. 4020 */ 4021 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 4022 { 4023 struct fw_port_cmd c; 4024 4025 memset(&c, 0, sizeof(c)); 4026 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 4027 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 4028 V_FW_PORT_CMD_PORTID(port)); 4029 c.action_to_len16 = 4030 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4031 FW_LEN16(c)); 4032 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 4033 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4034 } 4035 4036 struct intr_details { 4037 u32 mask; 4038 const char *msg; 4039 }; 4040 4041 struct intr_action { 4042 u32 mask; 4043 int arg; 4044 bool (*action)(struct adapter *, int, bool); 4045 }; 4046 4047 #define NONFATAL_IF_DISABLED 1 4048 struct intr_info { 4049 const char *name; /* name of the INT_CAUSE register */ 4050 int cause_reg; /* INT_CAUSE register */ 4051 int enable_reg; /* INT_ENABLE register */ 4052 u32 fatal; /* bits that are fatal */ 4053 int flags; /* hints */ 4054 const struct intr_details *details; 4055 const struct intr_action *actions; 4056 }; 4057 4058 static inline char 4059 intr_alert_char(u32 cause, u32 enable, u32 fatal) 4060 { 4061 4062 if (cause & fatal) 4063 return ('!'); 4064 if (cause & enable) 4065 return ('*'); 4066 return ('-'); 4067 } 4068 4069 static void 4070 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 4071 { 4072 u32 enable, fatal, leftover; 4073 const struct intr_details *details; 4074 char alert; 4075 4076 enable = t4_read_reg(adap, ii->enable_reg); 4077 if (ii->flags & NONFATAL_IF_DISABLED) 4078 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); 4079 else 4080 fatal = ii->fatal; 4081 alert = intr_alert_char(cause, enable, fatal); 4082 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 4083 alert, ii->name, ii->cause_reg, cause, enable, fatal); 4084 4085 leftover = cause; 4086 for (details = ii->details; details && details->mask != 0; details++) { 4087 u32 msgbits = details->mask & cause; 4088 if (msgbits == 0) 4089 continue; 4090 alert = intr_alert_char(msgbits, enable, ii->fatal); 4091 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 4092 details->msg); 4093 leftover &= ~msgbits; 4094 } 4095 if (leftover != 0 && leftover != cause) 4096 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 4097 } 4098 4099 /* 4100 * Returns true for fatal error. 4101 */ 4102 static bool 4103 t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4104 u32 additional_cause, bool verbose) 4105 { 4106 u32 cause, fatal; 4107 bool rc; 4108 const struct intr_action *action; 4109 4110 /* 4111 * Read and display cause. Note that the top level PL_INT_CAUSE is a 4112 * bit special and we need to completely ignore the bits that are not in 4113 * PL_INT_ENABLE. 4114 */ 4115 cause = t4_read_reg(adap, ii->cause_reg); 4116 if (ii->cause_reg == A_PL_INT_CAUSE) 4117 cause &= t4_read_reg(adap, ii->enable_reg); 4118 if (verbose || cause != 0) 4119 t4_show_intr_info(adap, ii, cause); 4120 fatal = cause & ii->fatal; 4121 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) 4122 fatal &= t4_read_reg(adap, ii->enable_reg); 4123 cause |= additional_cause; 4124 if (cause == 0) 4125 return (false); 4126 4127 rc = fatal != 0; 4128 for (action = ii->actions; action && action->mask != 0; action++) { 4129 if (!(action->mask & cause)) 4130 continue; 4131 rc |= (action->action)(adap, action->arg, verbose); 4132 } 4133 4134 /* clear */ 4135 t4_write_reg(adap, ii->cause_reg, cause); 4136 (void)t4_read_reg(adap, ii->cause_reg); 4137 4138 return (rc); 4139 } 4140 4141 /* 4142 * Interrupt handler for the PCIE module. 4143 */ 4144 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4145 { 4146 static const struct intr_details sysbus_intr_details[] = { 4147 { F_RNPP, "RXNP array parity error" }, 4148 { F_RPCP, "RXPC array parity error" }, 4149 { F_RCIP, "RXCIF array parity error" }, 4150 { F_RCCP, "Rx completions control array parity error" }, 4151 { F_RFTP, "RXFT array parity error" }, 4152 { 0 } 4153 }; 4154 static const struct intr_info sysbus_intr_info = { 4155 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4156 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4157 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4158 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4159 .flags = 0, 4160 .details = sysbus_intr_details, 4161 .actions = NULL, 4162 }; 4163 static const struct intr_details pcie_port_intr_details[] = { 4164 { F_TPCP, "TXPC array parity error" }, 4165 { F_TNPP, "TXNP array parity error" }, 4166 { F_TFTP, "TXFT array parity error" }, 4167 { F_TCAP, "TXCA array parity error" }, 4168 { F_TCIP, "TXCIF array parity error" }, 4169 { F_RCAP, "RXCA array parity error" }, 4170 { F_OTDD, "outbound request TLP discarded" }, 4171 { F_RDPE, "Rx data parity error" }, 4172 { F_TDUE, "Tx uncorrectable data error" }, 4173 { 0 } 4174 }; 4175 static const struct intr_info pcie_port_intr_info = { 4176 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4177 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4178 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4179 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4180 F_OTDD | F_RDPE | F_TDUE, 4181 .flags = 0, 4182 .details = pcie_port_intr_details, 4183 .actions = NULL, 4184 }; 4185 static const struct intr_details pcie_intr_details[] = { 4186 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4187 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4188 { F_MSIDATAPERR, "MSI data parity error" }, 4189 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4190 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4191 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4192 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4193 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4194 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4195 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4196 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4197 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4198 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4199 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4200 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4201 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4202 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4203 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4204 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4205 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4206 { F_FIDPERR, "PCIe FID parity error" }, 4207 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4208 { F_MATAGPERR, "PCIe MA tag parity error" }, 4209 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4210 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4211 { F_RXWRPERR, "PCIe Rx write parity error" }, 4212 { F_RPLPERR, "PCIe replay buffer parity error" }, 4213 { F_PCIESINT, "PCIe core secondary fault" }, 4214 { F_PCIEPINT, "PCIe core primary fault" }, 4215 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4216 { 0 } 4217 }; 4218 static const struct intr_details t5_pcie_intr_details[] = { 4219 { F_IPGRPPERR, "Parity errors observed by IP" }, 4220 { F_NONFATALERR, "PCIe non-fatal error" }, 4221 { F_READRSPERR, "Outbound read error" }, 4222 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4223 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4224 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4225 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4226 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4227 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4228 { F_MAGRPPERR, "MA group FIFO parity error" }, 4229 { F_VFIDPERR, "VFID SRAM parity error" }, 4230 { F_FIDPERR, "FID SRAM parity error" }, 4231 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4232 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4233 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4234 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4235 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4236 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4237 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4238 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4239 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4240 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4241 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4242 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4243 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4244 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4245 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4246 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4247 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4248 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4249 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4250 { 0 } 4251 }; 4252 struct intr_info pcie_intr_info = { 4253 .name = "PCIE_INT_CAUSE", 4254 .cause_reg = A_PCIE_INT_CAUSE, 4255 .enable_reg = A_PCIE_INT_ENABLE, 4256 .fatal = 0xffffffff, 4257 .flags = NONFATAL_IF_DISABLED, 4258 .details = NULL, 4259 .actions = NULL, 4260 }; 4261 bool fatal = false; 4262 4263 if (is_t4(adap)) { 4264 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4265 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4266 4267 pcie_intr_info.details = pcie_intr_details; 4268 } else { 4269 pcie_intr_info.details = t5_pcie_intr_details; 4270 } 4271 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4272 4273 return (fatal); 4274 } 4275 4276 /* 4277 * TP interrupt handler. 4278 */ 4279 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4280 { 4281 static const struct intr_details tp_intr_details[] = { 4282 { 0x3fffffff, "TP parity error" }, 4283 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4284 { 0 } 4285 }; 4286 static const struct intr_info tp_intr_info = { 4287 .name = "TP_INT_CAUSE", 4288 .cause_reg = A_TP_INT_CAUSE, 4289 .enable_reg = A_TP_INT_ENABLE, 4290 .fatal = 0x7fffffff, 4291 .flags = NONFATAL_IF_DISABLED, 4292 .details = tp_intr_details, 4293 .actions = NULL, 4294 }; 4295 4296 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4297 } 4298 4299 /* 4300 * SGE interrupt handler. 4301 */ 4302 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4303 { 4304 static const struct intr_info sge_int1_info = { 4305 .name = "SGE_INT_CAUSE1", 4306 .cause_reg = A_SGE_INT_CAUSE1, 4307 .enable_reg = A_SGE_INT_ENABLE1, 4308 .fatal = 0xffffffff, 4309 .flags = NONFATAL_IF_DISABLED, 4310 .details = NULL, 4311 .actions = NULL, 4312 }; 4313 static const struct intr_info sge_int2_info = { 4314 .name = "SGE_INT_CAUSE2", 4315 .cause_reg = A_SGE_INT_CAUSE2, 4316 .enable_reg = A_SGE_INT_ENABLE2, 4317 .fatal = 0xffffffff, 4318 .flags = NONFATAL_IF_DISABLED, 4319 .details = NULL, 4320 .actions = NULL, 4321 }; 4322 static const struct intr_details sge_int3_details[] = { 4323 { F_ERR_FLM_DBP, 4324 "DBP pointer delivery for invalid context or QID" }, 4325 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4326 "Invalid QID or header request by IDMA" }, 4327 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4328 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4329 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4330 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4331 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4332 { F_ERR_TIMER_ABOVE_MAX_QID, 4333 "SGE GTS with timer 0-5 for IQID > 1023" }, 4334 { F_ERR_CPL_EXCEED_IQE_SIZE, 4335 "SGE received CPL exceeding IQE size" }, 4336 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4337 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4338 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4339 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4340 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4341 "SGE IQID > 1023 received CPL for FL" }, 4342 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4343 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4344 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4345 { F_ERR_ING_CTXT_PRIO, 4346 "Ingress context manager priority user error" }, 4347 { F_ERR_EGR_CTXT_PRIO, 4348 "Egress context manager priority user error" }, 4349 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4350 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4351 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4352 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4353 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4354 { 0x0000000f, "SGE context access for invalid queue" }, 4355 { 0 } 4356 }; 4357 static const struct intr_details t6_sge_int3_details[] = { 4358 { F_ERR_FLM_DBP, 4359 "DBP pointer delivery for invalid context or QID" }, 4360 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4361 "Invalid QID or header request by IDMA" }, 4362 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4363 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4364 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4365 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4366 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4367 { F_ERR_TIMER_ABOVE_MAX_QID, 4368 "SGE GTS with timer 0-5 for IQID > 1023" }, 4369 { F_ERR_CPL_EXCEED_IQE_SIZE, 4370 "SGE received CPL exceeding IQE size" }, 4371 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4372 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4373 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4374 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4375 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4376 "SGE IQID > 1023 received CPL for FL" }, 4377 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4378 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4379 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4380 { F_ERR_ING_CTXT_PRIO, 4381 "Ingress context manager priority user error" }, 4382 { F_ERR_EGR_CTXT_PRIO, 4383 "Egress context manager priority user error" }, 4384 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4385 { F_FATAL_WRE_LEN, 4386 "SGE WRE packet less than advertized length" }, 4387 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4388 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4389 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4390 { 0x0000000f, "SGE context access for invalid queue" }, 4391 { 0 } 4392 }; 4393 struct intr_info sge_int3_info = { 4394 .name = "SGE_INT_CAUSE3", 4395 .cause_reg = A_SGE_INT_CAUSE3, 4396 .enable_reg = A_SGE_INT_ENABLE3, 4397 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4398 .flags = 0, 4399 .details = NULL, 4400 .actions = NULL, 4401 }; 4402 static const struct intr_info sge_int4_info = { 4403 .name = "SGE_INT_CAUSE4", 4404 .cause_reg = A_SGE_INT_CAUSE4, 4405 .enable_reg = A_SGE_INT_ENABLE4, 4406 .fatal = 0, 4407 .flags = 0, 4408 .details = NULL, 4409 .actions = NULL, 4410 }; 4411 static const struct intr_info sge_int5_info = { 4412 .name = "SGE_INT_CAUSE5", 4413 .cause_reg = A_SGE_INT_CAUSE5, 4414 .enable_reg = A_SGE_INT_ENABLE5, 4415 .fatal = 0xffffffff, 4416 .flags = NONFATAL_IF_DISABLED, 4417 .details = NULL, 4418 .actions = NULL, 4419 }; 4420 static const struct intr_info sge_int6_info = { 4421 .name = "SGE_INT_CAUSE6", 4422 .cause_reg = A_SGE_INT_CAUSE6, 4423 .enable_reg = A_SGE_INT_ENABLE6, 4424 .fatal = 0, 4425 .flags = 0, 4426 .details = NULL, 4427 .actions = NULL, 4428 }; 4429 4430 bool fatal; 4431 u32 v; 4432 4433 if (chip_id(adap) <= CHELSIO_T5) { 4434 sge_int3_info.details = sge_int3_details; 4435 } else { 4436 sge_int3_info.details = t6_sge_int3_details; 4437 } 4438 4439 fatal = false; 4440 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4441 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4442 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4443 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4444 if (chip_id(adap) >= CHELSIO_T5) 4445 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4446 if (chip_id(adap) >= CHELSIO_T6) 4447 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4448 4449 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4450 if (v & F_ERROR_QID_VALID) { 4451 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4452 if (v & F_UNCAPTURED_ERROR) 4453 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4454 t4_write_reg(adap, A_SGE_ERROR_STATS, 4455 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4456 } 4457 4458 return (fatal); 4459 } 4460 4461 /* 4462 * CIM interrupt handler. 4463 */ 4464 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4465 { 4466 static const struct intr_action cim_host_intr_actions[] = { 4467 { F_TIMER0INT, 0, t4_os_dump_cimla }, 4468 { 0 }, 4469 }; 4470 static const struct intr_details cim_host_intr_details[] = { 4471 /* T6+ */ 4472 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4473 4474 /* T5+ */ 4475 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4476 { F_PLCIM_MSTRSPDATAPARERR, 4477 "PL2CIM master response data parity error" }, 4478 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4479 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4480 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4481 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4482 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4483 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4484 4485 /* T4+ */ 4486 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4487 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4488 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4489 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4490 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4491 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4492 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4493 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4494 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4495 "CIM IBQ PCIe/SGE_HI parity error" }, 4496 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4497 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4498 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4499 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4500 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4501 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4502 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4503 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4504 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4505 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4506 { 0} 4507 }; 4508 static const struct intr_info cim_host_intr_info = { 4509 .name = "CIM_HOST_INT_CAUSE", 4510 .cause_reg = A_CIM_HOST_INT_CAUSE, 4511 .enable_reg = A_CIM_HOST_INT_ENABLE, 4512 .fatal = 0x007fffe6, 4513 .flags = NONFATAL_IF_DISABLED, 4514 .details = cim_host_intr_details, 4515 .actions = cim_host_intr_actions, 4516 }; 4517 static const struct intr_details cim_host_upacc_intr_details[] = { 4518 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4519 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4520 { F_TIMEOUTINT, "CIM PIF timeout" }, 4521 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4522 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4523 { F_BLKWRPLINT, "CIM block write to PL space" }, 4524 { F_BLKRDPLINT, "CIM block read from PL space" }, 4525 { F_SGLWRPLINT, 4526 "CIM single write to PL space with illegal BEs" }, 4527 { F_SGLRDPLINT, 4528 "CIM single read from PL space with illegal BEs" }, 4529 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4530 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4531 { F_SGLWRCTLINT, 4532 "CIM single write to CTL space with illegal BEs" }, 4533 { F_SGLRDCTLINT, 4534 "CIM single read from CTL space with illegal BEs" }, 4535 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4536 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4537 { F_SGLWREEPROMINT, 4538 "CIM single write to EEPROM space with illegal BEs" }, 4539 { F_SGLRDEEPROMINT, 4540 "CIM single read from EEPROM space with illegal BEs" }, 4541 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4542 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4543 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4544 { F_SGLRDFLASHINT, 4545 "CIM single read from flash space with illegal BEs" }, 4546 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4547 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4548 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4549 { F_SGLRDBOOTINT, 4550 "CIM single read from boot space with illegal BEs" }, 4551 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4552 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4553 { F_ILLRDINT, "CIM illegal read" }, 4554 { F_ILLWRINT, "CIM illegal write" }, 4555 { F_ILLTRANSINT, "CIM illegal transaction" }, 4556 { F_RSVDSPACEINT, "CIM reserved space access" }, 4557 {0} 4558 }; 4559 static const struct intr_info cim_host_upacc_intr_info = { 4560 .name = "CIM_HOST_UPACC_INT_CAUSE", 4561 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4562 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4563 .fatal = 0x3fffeeff, 4564 .flags = NONFATAL_IF_DISABLED, 4565 .details = cim_host_upacc_intr_details, 4566 .actions = NULL, 4567 }; 4568 static const struct intr_info cim_pf_host_intr_info = { 4569 .name = "CIM_PF_HOST_INT_CAUSE", 4570 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4571 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4572 .fatal = 0, 4573 .flags = 0, 4574 .details = NULL, 4575 .actions = NULL, 4576 }; 4577 u32 val, fw_err; 4578 bool fatal; 4579 4580 fw_err = t4_read_reg(adap, A_PCIE_FW); 4581 if (fw_err & F_PCIE_FW_ERR) 4582 t4_report_fw_error(adap); 4583 4584 /* 4585 * When the Firmware detects an internal error which normally wouldn't 4586 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4587 * to make sure the Host sees the Firmware Crash. So if we have a 4588 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4589 * interrupt. 4590 */ 4591 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4592 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4593 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4594 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4595 } 4596 4597 fatal = false; 4598 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4599 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4600 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4601 4602 return (fatal); 4603 } 4604 4605 /* 4606 * ULP RX interrupt handler. 4607 */ 4608 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4609 { 4610 static const struct intr_details ulprx_intr_details[] = { 4611 /* T5+ */ 4612 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4613 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4614 4615 /* T4+ */ 4616 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4617 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4618 { 0x007fffff, "ULPRX parity error" }, 4619 { 0 } 4620 }; 4621 static const struct intr_info ulprx_intr_info = { 4622 .name = "ULP_RX_INT_CAUSE", 4623 .cause_reg = A_ULP_RX_INT_CAUSE, 4624 .enable_reg = A_ULP_RX_INT_ENABLE, 4625 .fatal = 0x07ffffff, 4626 .flags = NONFATAL_IF_DISABLED, 4627 .details = ulprx_intr_details, 4628 .actions = NULL, 4629 }; 4630 static const struct intr_info ulprx_intr2_info = { 4631 .name = "ULP_RX_INT_CAUSE_2", 4632 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4633 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4634 .fatal = 0, 4635 .flags = 0, 4636 .details = NULL, 4637 .actions = NULL, 4638 }; 4639 bool fatal = false; 4640 4641 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4642 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4643 4644 return (fatal); 4645 } 4646 4647 /* 4648 * ULP TX interrupt handler. 4649 */ 4650 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4651 { 4652 static const struct intr_details ulptx_intr_details[] = { 4653 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4654 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4655 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4656 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4657 { 0x0fffffff, "ULPTX parity error" }, 4658 { 0 } 4659 }; 4660 static const struct intr_info ulptx_intr_info = { 4661 .name = "ULP_TX_INT_CAUSE", 4662 .cause_reg = A_ULP_TX_INT_CAUSE, 4663 .enable_reg = A_ULP_TX_INT_ENABLE, 4664 .fatal = 0x0fffffff, 4665 .flags = NONFATAL_IF_DISABLED, 4666 .details = ulptx_intr_details, 4667 .actions = NULL, 4668 }; 4669 static const struct intr_info ulptx_intr2_info = { 4670 .name = "ULP_TX_INT_CAUSE_2", 4671 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4672 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4673 .fatal = 0xf0, 4674 .flags = NONFATAL_IF_DISABLED, 4675 .details = NULL, 4676 .actions = NULL, 4677 }; 4678 bool fatal = false; 4679 4680 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4681 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4682 4683 return (fatal); 4684 } 4685 4686 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4687 { 4688 int i; 4689 u32 data[17]; 4690 4691 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4692 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4693 for (i = 0; i < ARRAY_SIZE(data); i++) { 4694 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4695 A_PM_TX_DBG_STAT0 + i, data[i]); 4696 } 4697 4698 return (false); 4699 } 4700 4701 /* 4702 * PM TX interrupt handler. 4703 */ 4704 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4705 { 4706 static const struct intr_action pmtx_intr_actions[] = { 4707 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4708 { 0 }, 4709 }; 4710 static const struct intr_details pmtx_intr_details[] = { 4711 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4712 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4713 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4714 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4715 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4716 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4717 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4718 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4719 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4720 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4721 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4722 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4723 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4724 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4725 { 0 } 4726 }; 4727 static const struct intr_info pmtx_intr_info = { 4728 .name = "PM_TX_INT_CAUSE", 4729 .cause_reg = A_PM_TX_INT_CAUSE, 4730 .enable_reg = A_PM_TX_INT_ENABLE, 4731 .fatal = 0xffffffff, 4732 .flags = 0, 4733 .details = pmtx_intr_details, 4734 .actions = pmtx_intr_actions, 4735 }; 4736 4737 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4738 } 4739 4740 /* 4741 * PM RX interrupt handler. 4742 */ 4743 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4744 { 4745 static const struct intr_details pmrx_intr_details[] = { 4746 /* T6+ */ 4747 { 0x18000000, "PMRX ospi overflow" }, 4748 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4749 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4750 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4751 { F_SDC_ERR, "PMRX SDC error" }, 4752 4753 /* T4+ */ 4754 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4755 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4756 { 0x0003c000, "PMRX iespi Rx framing error" }, 4757 { 0x00003c00, "PMRX iespi Tx framing error" }, 4758 { 0x00000300, "PMRX ocspi Rx framing error" }, 4759 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4760 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4761 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4762 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4763 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4764 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4765 { 0 } 4766 }; 4767 static const struct intr_info pmrx_intr_info = { 4768 .name = "PM_RX_INT_CAUSE", 4769 .cause_reg = A_PM_RX_INT_CAUSE, 4770 .enable_reg = A_PM_RX_INT_ENABLE, 4771 .fatal = 0x1fffffff, 4772 .flags = NONFATAL_IF_DISABLED, 4773 .details = pmrx_intr_details, 4774 .actions = NULL, 4775 }; 4776 4777 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4778 } 4779 4780 /* 4781 * CPL switch interrupt handler. 4782 */ 4783 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4784 { 4785 static const struct intr_details cplsw_intr_details[] = { 4786 /* T5+ */ 4787 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4788 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4789 4790 /* T4+ */ 4791 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4792 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4793 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4794 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4795 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4796 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4797 { 0 } 4798 }; 4799 static const struct intr_info cplsw_intr_info = { 4800 .name = "CPL_INTR_CAUSE", 4801 .cause_reg = A_CPL_INTR_CAUSE, 4802 .enable_reg = A_CPL_INTR_ENABLE, 4803 .fatal = 0xff, 4804 .flags = NONFATAL_IF_DISABLED, 4805 .details = cplsw_intr_details, 4806 .actions = NULL, 4807 }; 4808 4809 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4810 } 4811 4812 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4813 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR) 4814 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4815 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4816 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4817 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4818 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4819 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4820 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4821 4822 /* 4823 * LE interrupt handler. 4824 */ 4825 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4826 { 4827 static const struct intr_details le_intr_details[] = { 4828 { F_REQQPARERR, "LE request queue parity error" }, 4829 { F_UNKNOWNCMD, "LE unknown command" }, 4830 { F_ACTRGNFULL, "LE active region full" }, 4831 { F_PARITYERR, "LE parity error" }, 4832 { F_LIPMISS, "LE LIP miss" }, 4833 { F_LIP0, "LE 0 LIP error" }, 4834 { 0 } 4835 }; 4836 static const struct intr_details t6_le_intr_details[] = { 4837 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4838 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4839 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4840 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4841 { F_TOTCNTERR, "LE total active < TCAM count" }, 4842 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4843 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4844 { F_T6_ACTRGNFULL, "LE active region full" }, 4845 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4846 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4847 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4848 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4849 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4850 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4851 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4852 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4853 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4854 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4855 { 0 } 4856 }; 4857 struct intr_info le_intr_info = { 4858 .name = "LE_DB_INT_CAUSE", 4859 .cause_reg = A_LE_DB_INT_CAUSE, 4860 .enable_reg = A_LE_DB_INT_ENABLE, 4861 .fatal = 0, 4862 .flags = NONFATAL_IF_DISABLED, 4863 .details = NULL, 4864 .actions = NULL, 4865 }; 4866 4867 if (chip_id(adap) <= CHELSIO_T5) { 4868 le_intr_info.details = le_intr_details; 4869 le_intr_info.fatal = T5_LE_FATAL_MASK; 4870 } else { 4871 le_intr_info.details = t6_le_intr_details; 4872 le_intr_info.fatal = T6_LE_FATAL_MASK; 4873 } 4874 4875 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4876 } 4877 4878 /* 4879 * MPS interrupt handler. 4880 */ 4881 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4882 { 4883 static const struct intr_details mps_rx_perr_intr_details[] = { 4884 { 0xffffffff, "MPS Rx parity error" }, 4885 { 0 } 4886 }; 4887 static const struct intr_info mps_rx_perr_intr_info = { 4888 .name = "MPS_RX_PERR_INT_CAUSE", 4889 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4890 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4891 .fatal = 0xffffffff, 4892 .flags = NONFATAL_IF_DISABLED, 4893 .details = mps_rx_perr_intr_details, 4894 .actions = NULL, 4895 }; 4896 static const struct intr_details mps_tx_intr_details[] = { 4897 { F_PORTERR, "MPS Tx destination port is disabled" }, 4898 { F_FRMERR, "MPS Tx framing error" }, 4899 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4900 { F_BUBBLE, "MPS Tx underflow" }, 4901 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4902 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4903 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4904 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4905 { 0 } 4906 }; 4907 static const struct intr_info mps_tx_intr_info = { 4908 .name = "MPS_TX_INT_CAUSE", 4909 .cause_reg = A_MPS_TX_INT_CAUSE, 4910 .enable_reg = A_MPS_TX_INT_ENABLE, 4911 .fatal = 0x1ffff, 4912 .flags = NONFATAL_IF_DISABLED, 4913 .details = mps_tx_intr_details, 4914 .actions = NULL, 4915 }; 4916 static const struct intr_details mps_trc_intr_details[] = { 4917 { F_MISCPERR, "MPS TRC misc parity error" }, 4918 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4919 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4920 { 0 } 4921 }; 4922 static const struct intr_info mps_trc_intr_info = { 4923 .name = "MPS_TRC_INT_CAUSE", 4924 .cause_reg = A_MPS_TRC_INT_CAUSE, 4925 .enable_reg = A_MPS_TRC_INT_ENABLE, 4926 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4927 .flags = 0, 4928 .details = mps_trc_intr_details, 4929 .actions = NULL, 4930 }; 4931 static const struct intr_details mps_stat_sram_intr_details[] = { 4932 { 0xffffffff, "MPS statistics SRAM parity error" }, 4933 { 0 } 4934 }; 4935 static const struct intr_info mps_stat_sram_intr_info = { 4936 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4937 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4938 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4939 .fatal = 0x1fffffff, 4940 .flags = NONFATAL_IF_DISABLED, 4941 .details = mps_stat_sram_intr_details, 4942 .actions = NULL, 4943 }; 4944 static const struct intr_details mps_stat_tx_intr_details[] = { 4945 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4946 { 0 } 4947 }; 4948 static const struct intr_info mps_stat_tx_intr_info = { 4949 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4950 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4951 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4952 .fatal = 0xffffff, 4953 .flags = NONFATAL_IF_DISABLED, 4954 .details = mps_stat_tx_intr_details, 4955 .actions = NULL, 4956 }; 4957 static const struct intr_details mps_stat_rx_intr_details[] = { 4958 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4959 { 0 } 4960 }; 4961 static const struct intr_info mps_stat_rx_intr_info = { 4962 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4963 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4964 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4965 .fatal = 0xffffff, 4966 .flags = 0, 4967 .details = mps_stat_rx_intr_details, 4968 .actions = NULL, 4969 }; 4970 static const struct intr_details mps_cls_intr_details[] = { 4971 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4972 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4973 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4974 { 0 } 4975 }; 4976 static const struct intr_info mps_cls_intr_info = { 4977 .name = "MPS_CLS_INT_CAUSE", 4978 .cause_reg = A_MPS_CLS_INT_CAUSE, 4979 .enable_reg = A_MPS_CLS_INT_ENABLE, 4980 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4981 .flags = 0, 4982 .details = mps_cls_intr_details, 4983 .actions = NULL, 4984 }; 4985 static const struct intr_details mps_stat_sram1_intr_details[] = { 4986 { 0xff, "MPS statistics SRAM1 parity error" }, 4987 { 0 } 4988 }; 4989 static const struct intr_info mps_stat_sram1_intr_info = { 4990 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4991 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4992 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4993 .fatal = 0xff, 4994 .flags = 0, 4995 .details = mps_stat_sram1_intr_details, 4996 .actions = NULL, 4997 }; 4998 4999 bool fatal; 5000 5001 fatal = false; 5002 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 5003 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 5004 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 5005 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 5006 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 5007 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 5008 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 5009 if (chip_id(adap) > CHELSIO_T4) { 5010 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 5011 verbose); 5012 } 5013 5014 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5015 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 5016 5017 return (fatal); 5018 5019 } 5020 5021 /* 5022 * EDC/MC interrupt handler. 5023 */ 5024 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 5025 { 5026 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 5027 unsigned int count_reg, v; 5028 static const struct intr_details mem_intr_details[] = { 5029 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 5030 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 5031 { F_PERR_INT_CAUSE, "FIFO parity error" }, 5032 { 0 } 5033 }; 5034 struct intr_info ii = { 5035 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 5036 .details = mem_intr_details, 5037 .flags = 0, 5038 .actions = NULL, 5039 }; 5040 bool fatal; 5041 5042 switch (idx) { 5043 case MEM_EDC0: 5044 ii.name = "EDC0_INT_CAUSE"; 5045 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 5046 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 5047 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 5048 break; 5049 case MEM_EDC1: 5050 ii.name = "EDC1_INT_CAUSE"; 5051 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 5052 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 5053 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 5054 break; 5055 case MEM_MC0: 5056 ii.name = "MC0_INT_CAUSE"; 5057 if (is_t4(adap)) { 5058 ii.cause_reg = A_MC_INT_CAUSE; 5059 ii.enable_reg = A_MC_INT_ENABLE; 5060 count_reg = A_MC_ECC_STATUS; 5061 } else { 5062 ii.cause_reg = A_MC_P_INT_CAUSE; 5063 ii.enable_reg = A_MC_P_INT_ENABLE; 5064 count_reg = A_MC_P_ECC_STATUS; 5065 } 5066 break; 5067 case MEM_MC1: 5068 ii.name = "MC1_INT_CAUSE"; 5069 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 5070 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 5071 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 5072 break; 5073 } 5074 5075 fatal = t4_handle_intr(adap, &ii, 0, verbose); 5076 5077 v = t4_read_reg(adap, count_reg); 5078 if (v != 0) { 5079 if (G_ECC_UECNT(v) != 0) { 5080 CH_ALERT(adap, 5081 "%s: %u uncorrectable ECC data error(s)\n", 5082 name[idx], G_ECC_UECNT(v)); 5083 } 5084 if (G_ECC_CECNT(v) != 0) { 5085 if (idx <= MEM_EDC1) 5086 t4_edc_err_read(adap, idx); 5087 CH_WARN_RATELIMIT(adap, 5088 "%s: %u correctable ECC data error(s)\n", 5089 name[idx], G_ECC_CECNT(v)); 5090 } 5091 t4_write_reg(adap, count_reg, 0xffffffff); 5092 } 5093 5094 return (fatal); 5095 } 5096 5097 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 5098 { 5099 u32 v; 5100 5101 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 5102 CH_ALERT(adap, 5103 "MA address wrap-around error by client %u to address %#x\n", 5104 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 5105 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 5106 5107 return (false); 5108 } 5109 5110 5111 /* 5112 * MA interrupt handler. 5113 */ 5114 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 5115 { 5116 static const struct intr_action ma_intr_actions[] = { 5117 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 5118 { 0 }, 5119 }; 5120 static const struct intr_info ma_intr_info = { 5121 .name = "MA_INT_CAUSE", 5122 .cause_reg = A_MA_INT_CAUSE, 5123 .enable_reg = A_MA_INT_ENABLE, 5124 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE, 5125 .flags = NONFATAL_IF_DISABLED, 5126 .details = NULL, 5127 .actions = ma_intr_actions, 5128 }; 5129 static const struct intr_info ma_perr_status1 = { 5130 .name = "MA_PARITY_ERROR_STATUS1", 5131 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5132 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5133 .fatal = 0xffffffff, 5134 .flags = 0, 5135 .details = NULL, 5136 .actions = NULL, 5137 }; 5138 static const struct intr_info ma_perr_status2 = { 5139 .name = "MA_PARITY_ERROR_STATUS2", 5140 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5141 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5142 .fatal = 0xffffffff, 5143 .flags = 0, 5144 .details = NULL, 5145 .actions = NULL, 5146 }; 5147 bool fatal; 5148 5149 fatal = false; 5150 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5151 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5152 if (chip_id(adap) > CHELSIO_T4) 5153 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5154 5155 return (fatal); 5156 } 5157 5158 /* 5159 * SMB interrupt handler. 5160 */ 5161 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5162 { 5163 static const struct intr_details smb_intr_details[] = { 5164 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5165 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5166 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5167 { 0 } 5168 }; 5169 static const struct intr_info smb_intr_info = { 5170 .name = "SMB_INT_CAUSE", 5171 .cause_reg = A_SMB_INT_CAUSE, 5172 .enable_reg = A_SMB_INT_ENABLE, 5173 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5174 .flags = 0, 5175 .details = smb_intr_details, 5176 .actions = NULL, 5177 }; 5178 5179 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5180 } 5181 5182 /* 5183 * NC-SI interrupt handler. 5184 */ 5185 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5186 { 5187 static const struct intr_details ncsi_intr_details[] = { 5188 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5189 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5190 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5191 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5192 { 0 } 5193 }; 5194 static const struct intr_info ncsi_intr_info = { 5195 .name = "NCSI_INT_CAUSE", 5196 .cause_reg = A_NCSI_INT_CAUSE, 5197 .enable_reg = A_NCSI_INT_ENABLE, 5198 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5199 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5200 .flags = 0, 5201 .details = ncsi_intr_details, 5202 .actions = NULL, 5203 }; 5204 5205 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5206 } 5207 5208 /* 5209 * MAC interrupt handler. 5210 */ 5211 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5212 { 5213 static const struct intr_details mac_intr_details[] = { 5214 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5215 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5216 { 0 } 5217 }; 5218 char name[32]; 5219 struct intr_info ii; 5220 bool fatal = false; 5221 5222 if (is_t4(adap)) { 5223 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5224 ii.name = &name[0]; 5225 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5226 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5227 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5228 ii.flags = 0; 5229 ii.details = mac_intr_details; 5230 ii.actions = NULL; 5231 } else { 5232 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5233 ii.name = &name[0]; 5234 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5235 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5236 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5237 ii.flags = 0; 5238 ii.details = mac_intr_details; 5239 ii.actions = NULL; 5240 } 5241 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5242 5243 if (chip_id(adap) >= CHELSIO_T5) { 5244 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5245 ii.name = &name[0]; 5246 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5247 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5248 ii.fatal = 0; 5249 ii.flags = 0; 5250 ii.details = NULL; 5251 ii.actions = NULL; 5252 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5253 } 5254 5255 if (chip_id(adap) >= CHELSIO_T6) { 5256 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5257 ii.name = &name[0]; 5258 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5259 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5260 ii.fatal = 0; 5261 ii.flags = 0; 5262 ii.details = NULL; 5263 ii.actions = NULL; 5264 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5265 } 5266 5267 return (fatal); 5268 } 5269 5270 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5271 { 5272 static const struct intr_details plpl_intr_details[] = { 5273 { F_FATALPERR, "Fatal parity error" }, 5274 { F_PERRVFID, "VFID_MAP parity error" }, 5275 { 0 } 5276 }; 5277 static const struct intr_info plpl_intr_info = { 5278 .name = "PL_PL_INT_CAUSE", 5279 .cause_reg = A_PL_PL_INT_CAUSE, 5280 .enable_reg = A_PL_PL_INT_ENABLE, 5281 .fatal = F_FATALPERR | F_PERRVFID, 5282 .flags = NONFATAL_IF_DISABLED, 5283 .details = plpl_intr_details, 5284 .actions = NULL, 5285 }; 5286 5287 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5288 } 5289 5290 /** 5291 * t4_slow_intr_handler - control path interrupt handler 5292 * @adap: the adapter 5293 * @verbose: increased verbosity, for debug 5294 * 5295 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5296 * The designation 'slow' is because it involves register reads, while 5297 * data interrupts typically don't involve any MMIOs. 5298 */ 5299 int t4_slow_intr_handler(struct adapter *adap, bool verbose) 5300 { 5301 static const struct intr_details pl_intr_details[] = { 5302 { F_MC1, "MC1" }, 5303 { F_UART, "UART" }, 5304 { F_ULP_TX, "ULP TX" }, 5305 { F_SGE, "SGE" }, 5306 { F_HMA, "HMA" }, 5307 { F_CPL_SWITCH, "CPL Switch" }, 5308 { F_ULP_RX, "ULP RX" }, 5309 { F_PM_RX, "PM RX" }, 5310 { F_PM_TX, "PM TX" }, 5311 { F_MA, "MA" }, 5312 { F_TP, "TP" }, 5313 { F_LE, "LE" }, 5314 { F_EDC1, "EDC1" }, 5315 { F_EDC0, "EDC0" }, 5316 { F_MC, "MC0" }, 5317 { F_PCIE, "PCIE" }, 5318 { F_PMU, "PMU" }, 5319 { F_MAC3, "MAC3" }, 5320 { F_MAC2, "MAC2" }, 5321 { F_MAC1, "MAC1" }, 5322 { F_MAC0, "MAC0" }, 5323 { F_SMB, "SMB" }, 5324 { F_SF, "SF" }, 5325 { F_PL, "PL" }, 5326 { F_NCSI, "NC-SI" }, 5327 { F_MPS, "MPS" }, 5328 { F_MI, "MI" }, 5329 { F_DBG, "DBG" }, 5330 { F_I2CM, "I2CM" }, 5331 { F_CIM, "CIM" }, 5332 { 0 } 5333 }; 5334 static const struct intr_info pl_perr_cause = { 5335 .name = "PL_PERR_CAUSE", 5336 .cause_reg = A_PL_PERR_CAUSE, 5337 .enable_reg = A_PL_PERR_ENABLE, 5338 .fatal = 0xffffffff, 5339 .flags = 0, 5340 .details = pl_intr_details, 5341 .actions = NULL, 5342 }; 5343 static const struct intr_action pl_intr_action[] = { 5344 { F_MC1, MEM_MC1, mem_intr_handler }, 5345 { F_ULP_TX, -1, ulptx_intr_handler }, 5346 { F_SGE, -1, sge_intr_handler }, 5347 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5348 { F_ULP_RX, -1, ulprx_intr_handler }, 5349 { F_PM_RX, -1, pmrx_intr_handler}, 5350 { F_PM_TX, -1, pmtx_intr_handler}, 5351 { F_MA, -1, ma_intr_handler }, 5352 { F_TP, -1, tp_intr_handler }, 5353 { F_LE, -1, le_intr_handler }, 5354 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5355 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5356 { F_MC0, MEM_MC0, mem_intr_handler }, 5357 { F_PCIE, -1, pcie_intr_handler }, 5358 { F_MAC3, 3, mac_intr_handler}, 5359 { F_MAC2, 2, mac_intr_handler}, 5360 { F_MAC1, 1, mac_intr_handler}, 5361 { F_MAC0, 0, mac_intr_handler}, 5362 { F_SMB, -1, smb_intr_handler}, 5363 { F_PL, -1, plpl_intr_handler }, 5364 { F_NCSI, -1, ncsi_intr_handler}, 5365 { F_MPS, -1, mps_intr_handler }, 5366 { F_CIM, -1, cim_intr_handler }, 5367 { 0 } 5368 }; 5369 static const struct intr_info pl_intr_info = { 5370 .name = "PL_INT_CAUSE", 5371 .cause_reg = A_PL_INT_CAUSE, 5372 .enable_reg = A_PL_INT_ENABLE, 5373 .fatal = 0, 5374 .flags = 0, 5375 .details = pl_intr_details, 5376 .actions = pl_intr_action, 5377 }; 5378 bool fatal; 5379 u32 perr; 5380 5381 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5382 if (verbose || perr != 0) { 5383 t4_show_intr_info(adap, &pl_perr_cause, perr); 5384 if (perr != 0) 5385 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5386 if (verbose) 5387 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5388 } 5389 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose); 5390 if (fatal) 5391 t4_fatal_err(adap, false); 5392 5393 return (0); 5394 } 5395 5396 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 5397 5398 /** 5399 * t4_intr_enable - enable interrupts 5400 * @adapter: the adapter whose interrupts should be enabled 5401 * 5402 * Enable PF-specific interrupts for the calling function and the top-level 5403 * interrupt concentrator for global interrupts. Interrupts are already 5404 * enabled at each module, here we just enable the roots of the interrupt 5405 * hierarchies. 5406 * 5407 * Note: this function should be called only when the driver manages 5408 * non PF-specific interrupts from the various HW modules. Only one PCI 5409 * function at a time should be doing this. 5410 */ 5411 void t4_intr_enable(struct adapter *adap) 5412 { 5413 u32 val = 0; 5414 5415 if (chip_id(adap) <= CHELSIO_T5) 5416 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5417 else 5418 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5419 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5420 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5421 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5422 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5423 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5424 F_EGRESS_SIZE_ERR; 5425 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5426 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5427 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); 5428 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5429 } 5430 5431 /** 5432 * t4_intr_disable - disable interrupts 5433 * @adap: the adapter whose interrupts should be disabled 5434 * 5435 * Disable interrupts. We only disable the top-level interrupt 5436 * concentrators. The caller must be a PCI function managing global 5437 * interrupts. 5438 */ 5439 void t4_intr_disable(struct adapter *adap) 5440 { 5441 5442 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5443 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5444 } 5445 5446 /** 5447 * t4_intr_clear - clear all interrupts 5448 * @adap: the adapter whose interrupts should be cleared 5449 * 5450 * Clears all interrupts. The caller must be a PCI function managing 5451 * global interrupts. 5452 */ 5453 void t4_intr_clear(struct adapter *adap) 5454 { 5455 static const u32 cause_reg[] = { 5456 A_CIM_HOST_INT_CAUSE, 5457 A_CIM_HOST_UPACC_INT_CAUSE, 5458 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5459 A_CPL_INTR_CAUSE, 5460 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5461 A_LE_DB_INT_CAUSE, 5462 A_MA_INT_WRAP_STATUS, 5463 A_MA_PARITY_ERROR_STATUS1, 5464 A_MA_INT_CAUSE, 5465 A_MPS_CLS_INT_CAUSE, 5466 A_MPS_RX_PERR_INT_CAUSE, 5467 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5468 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5469 A_MPS_TRC_INT_CAUSE, 5470 A_MPS_TX_INT_CAUSE, 5471 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5472 A_NCSI_INT_CAUSE, 5473 A_PCIE_INT_CAUSE, 5474 A_PCIE_NONFAT_ERR, 5475 A_PL_PL_INT_CAUSE, 5476 A_PM_RX_INT_CAUSE, 5477 A_PM_TX_INT_CAUSE, 5478 A_SGE_INT_CAUSE1, 5479 A_SGE_INT_CAUSE2, 5480 A_SGE_INT_CAUSE3, 5481 A_SGE_INT_CAUSE4, 5482 A_SMB_INT_CAUSE, 5483 A_TP_INT_CAUSE, 5484 A_ULP_RX_INT_CAUSE, 5485 A_ULP_RX_INT_CAUSE_2, 5486 A_ULP_TX_INT_CAUSE, 5487 A_ULP_TX_INT_CAUSE_2, 5488 5489 MYPF_REG(A_PL_PF_INT_CAUSE), 5490 }; 5491 int i; 5492 const int nchan = adap->chip_params->nchan; 5493 5494 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5495 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5496 5497 if (is_t4(adap)) { 5498 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5499 0xffffffff); 5500 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5501 0xffffffff); 5502 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5503 for (i = 0; i < nchan; i++) { 5504 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5505 0xffffffff); 5506 } 5507 } 5508 if (chip_id(adap) >= CHELSIO_T5) { 5509 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5510 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5511 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5512 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5513 if (is_t5(adap)) { 5514 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5515 0xffffffff); 5516 } 5517 for (i = 0; i < nchan; i++) { 5518 t4_write_reg(adap, T5_PORT_REG(i, 5519 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5520 if (chip_id(adap) > CHELSIO_T5) { 5521 t4_write_reg(adap, T5_PORT_REG(i, 5522 A_MAC_PORT_PERR_INT_CAUSE_100G), 5523 0xffffffff); 5524 } 5525 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5526 0xffffffff); 5527 } 5528 } 5529 if (chip_id(adap) >= CHELSIO_T6) { 5530 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5531 } 5532 5533 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5534 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5535 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5536 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5537 } 5538 5539 /** 5540 * hash_mac_addr - return the hash value of a MAC address 5541 * @addr: the 48-bit Ethernet MAC address 5542 * 5543 * Hashes a MAC address according to the hash function used by HW inexact 5544 * (hash) address matching. 5545 */ 5546 static int hash_mac_addr(const u8 *addr) 5547 { 5548 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5549 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5550 a ^= b; 5551 a ^= (a >> 12); 5552 a ^= (a >> 6); 5553 return a & 0x3f; 5554 } 5555 5556 /** 5557 * t4_config_rss_range - configure a portion of the RSS mapping table 5558 * @adapter: the adapter 5559 * @mbox: mbox to use for the FW command 5560 * @viid: virtual interface whose RSS subtable is to be written 5561 * @start: start entry in the table to write 5562 * @n: how many table entries to write 5563 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5564 * @nrspq: number of values in @rspq 5565 * 5566 * Programs the selected part of the VI's RSS mapping table with the 5567 * provided values. If @nrspq < @n the supplied values are used repeatedly 5568 * until the full table range is populated. 5569 * 5570 * The caller must ensure the values in @rspq are in the range allowed for 5571 * @viid. 5572 */ 5573 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5574 int start, int n, const u16 *rspq, unsigned int nrspq) 5575 { 5576 int ret; 5577 const u16 *rsp = rspq; 5578 const u16 *rsp_end = rspq + nrspq; 5579 struct fw_rss_ind_tbl_cmd cmd; 5580 5581 memset(&cmd, 0, sizeof(cmd)); 5582 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5583 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5584 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5585 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5586 5587 /* 5588 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5589 * Queue Identifiers. These Ingress Queue IDs are packed three to 5590 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5591 * reserved. 5592 */ 5593 while (n > 0) { 5594 int nq = min(n, 32); 5595 int nq_packed = 0; 5596 __be32 *qp = &cmd.iq0_to_iq2; 5597 5598 /* 5599 * Set up the firmware RSS command header to send the next 5600 * "nq" Ingress Queue IDs to the firmware. 5601 */ 5602 cmd.niqid = cpu_to_be16(nq); 5603 cmd.startidx = cpu_to_be16(start); 5604 5605 /* 5606 * "nq" more done for the start of the next loop. 5607 */ 5608 start += nq; 5609 n -= nq; 5610 5611 /* 5612 * While there are still Ingress Queue IDs to stuff into the 5613 * current firmware RSS command, retrieve them from the 5614 * Ingress Queue ID array and insert them into the command. 5615 */ 5616 while (nq > 0) { 5617 /* 5618 * Grab up to the next 3 Ingress Queue IDs (wrapping 5619 * around the Ingress Queue ID array if necessary) and 5620 * insert them into the firmware RSS command at the 5621 * current 3-tuple position within the commad. 5622 */ 5623 u16 qbuf[3]; 5624 u16 *qbp = qbuf; 5625 int nqbuf = min(3, nq); 5626 5627 nq -= nqbuf; 5628 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5629 while (nqbuf && nq_packed < 32) { 5630 nqbuf--; 5631 nq_packed++; 5632 *qbp++ = *rsp++; 5633 if (rsp >= rsp_end) 5634 rsp = rspq; 5635 } 5636 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5637 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5638 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5639 } 5640 5641 /* 5642 * Send this portion of the RRS table update to the firmware; 5643 * bail out on any errors. 5644 */ 5645 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5646 if (ret) 5647 return ret; 5648 } 5649 return 0; 5650 } 5651 5652 /** 5653 * t4_config_glbl_rss - configure the global RSS mode 5654 * @adapter: the adapter 5655 * @mbox: mbox to use for the FW command 5656 * @mode: global RSS mode 5657 * @flags: mode-specific flags 5658 * 5659 * Sets the global RSS mode. 5660 */ 5661 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5662 unsigned int flags) 5663 { 5664 struct fw_rss_glb_config_cmd c; 5665 5666 memset(&c, 0, sizeof(c)); 5667 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5668 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5669 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5670 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5671 c.u.manual.mode_pkd = 5672 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5673 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5674 c.u.basicvirtual.mode_keymode = 5675 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5676 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5677 } else 5678 return -EINVAL; 5679 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5680 } 5681 5682 /** 5683 * t4_config_vi_rss - configure per VI RSS settings 5684 * @adapter: the adapter 5685 * @mbox: mbox to use for the FW command 5686 * @viid: the VI id 5687 * @flags: RSS flags 5688 * @defq: id of the default RSS queue for the VI. 5689 * @skeyidx: RSS secret key table index for non-global mode 5690 * @skey: RSS vf_scramble key for VI. 5691 * 5692 * Configures VI-specific RSS properties. 5693 */ 5694 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5695 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5696 unsigned int skey) 5697 { 5698 struct fw_rss_vi_config_cmd c; 5699 5700 memset(&c, 0, sizeof(c)); 5701 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5702 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5703 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5704 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5705 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5706 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5707 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5708 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5709 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5710 5711 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5712 } 5713 5714 /* Read an RSS table row */ 5715 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5716 { 5717 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5718 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5719 5, 0, val); 5720 } 5721 5722 /** 5723 * t4_read_rss - read the contents of the RSS mapping table 5724 * @adapter: the adapter 5725 * @map: holds the contents of the RSS mapping table 5726 * 5727 * Reads the contents of the RSS hash->queue mapping table. 5728 */ 5729 int t4_read_rss(struct adapter *adapter, u16 *map) 5730 { 5731 u32 val; 5732 int i, ret; 5733 int rss_nentries = adapter->chip_params->rss_nentries; 5734 5735 for (i = 0; i < rss_nentries / 2; ++i) { 5736 ret = rd_rss_row(adapter, i, &val); 5737 if (ret) 5738 return ret; 5739 *map++ = G_LKPTBLQUEUE0(val); 5740 *map++ = G_LKPTBLQUEUE1(val); 5741 } 5742 return 0; 5743 } 5744 5745 /** 5746 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5747 * @adap: the adapter 5748 * @cmd: TP fw ldst address space type 5749 * @vals: where the indirect register values are stored/written 5750 * @nregs: how many indirect registers to read/write 5751 * @start_idx: index of first indirect register to read/write 5752 * @rw: Read (1) or Write (0) 5753 * @sleep_ok: if true we may sleep while awaiting command completion 5754 * 5755 * Access TP indirect registers through LDST 5756 **/ 5757 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5758 unsigned int nregs, unsigned int start_index, 5759 unsigned int rw, bool sleep_ok) 5760 { 5761 int ret = 0; 5762 unsigned int i; 5763 struct fw_ldst_cmd c; 5764 5765 for (i = 0; i < nregs; i++) { 5766 memset(&c, 0, sizeof(c)); 5767 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5768 F_FW_CMD_REQUEST | 5769 (rw ? F_FW_CMD_READ : 5770 F_FW_CMD_WRITE) | 5771 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5772 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5773 5774 c.u.addrval.addr = cpu_to_be32(start_index + i); 5775 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5776 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5777 sleep_ok); 5778 if (ret) 5779 return ret; 5780 5781 if (rw) 5782 vals[i] = be32_to_cpu(c.u.addrval.val); 5783 } 5784 return 0; 5785 } 5786 5787 /** 5788 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5789 * @adap: the adapter 5790 * @reg_addr: Address Register 5791 * @reg_data: Data register 5792 * @buff: where the indirect register values are stored/written 5793 * @nregs: how many indirect registers to read/write 5794 * @start_index: index of first indirect register to read/write 5795 * @rw: READ(1) or WRITE(0) 5796 * @sleep_ok: if true we may sleep while awaiting command completion 5797 * 5798 * Read/Write TP indirect registers through LDST if possible. 5799 * Else, use backdoor access 5800 **/ 5801 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5802 u32 *buff, u32 nregs, u32 start_index, int rw, 5803 bool sleep_ok) 5804 { 5805 int rc = -EINVAL; 5806 int cmd; 5807 5808 switch (reg_addr) { 5809 case A_TP_PIO_ADDR: 5810 cmd = FW_LDST_ADDRSPC_TP_PIO; 5811 break; 5812 case A_TP_TM_PIO_ADDR: 5813 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5814 break; 5815 case A_TP_MIB_INDEX: 5816 cmd = FW_LDST_ADDRSPC_TP_MIB; 5817 break; 5818 default: 5819 goto indirect_access; 5820 } 5821 5822 if (t4_use_ldst(adap)) 5823 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5824 sleep_ok); 5825 5826 indirect_access: 5827 5828 if (rc) { 5829 if (rw) 5830 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5831 start_index); 5832 else 5833 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5834 start_index); 5835 } 5836 } 5837 5838 /** 5839 * t4_tp_pio_read - Read TP PIO registers 5840 * @adap: the adapter 5841 * @buff: where the indirect register values are written 5842 * @nregs: how many indirect registers to read 5843 * @start_index: index of first indirect register to read 5844 * @sleep_ok: if true we may sleep while awaiting command completion 5845 * 5846 * Read TP PIO Registers 5847 **/ 5848 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5849 u32 start_index, bool sleep_ok) 5850 { 5851 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5852 start_index, 1, sleep_ok); 5853 } 5854 5855 /** 5856 * t4_tp_pio_write - Write TP PIO registers 5857 * @adap: the adapter 5858 * @buff: where the indirect register values are stored 5859 * @nregs: how many indirect registers to write 5860 * @start_index: index of first indirect register to write 5861 * @sleep_ok: if true we may sleep while awaiting command completion 5862 * 5863 * Write TP PIO Registers 5864 **/ 5865 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5866 u32 start_index, bool sleep_ok) 5867 { 5868 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5869 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5870 } 5871 5872 /** 5873 * t4_tp_tm_pio_read - Read TP TM PIO registers 5874 * @adap: the adapter 5875 * @buff: where the indirect register values are written 5876 * @nregs: how many indirect registers to read 5877 * @start_index: index of first indirect register to read 5878 * @sleep_ok: if true we may sleep while awaiting command completion 5879 * 5880 * Read TP TM PIO Registers 5881 **/ 5882 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5883 u32 start_index, bool sleep_ok) 5884 { 5885 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5886 nregs, start_index, 1, sleep_ok); 5887 } 5888 5889 /** 5890 * t4_tp_mib_read - Read TP MIB registers 5891 * @adap: the adapter 5892 * @buff: where the indirect register values are written 5893 * @nregs: how many indirect registers to read 5894 * @start_index: index of first indirect register to read 5895 * @sleep_ok: if true we may sleep while awaiting command completion 5896 * 5897 * Read TP MIB Registers 5898 **/ 5899 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5900 bool sleep_ok) 5901 { 5902 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5903 start_index, 1, sleep_ok); 5904 } 5905 5906 /** 5907 * t4_read_rss_key - read the global RSS key 5908 * @adap: the adapter 5909 * @key: 10-entry array holding the 320-bit RSS key 5910 * @sleep_ok: if true we may sleep while awaiting command completion 5911 * 5912 * Reads the global 320-bit RSS key. 5913 */ 5914 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5915 { 5916 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5917 } 5918 5919 /** 5920 * t4_write_rss_key - program one of the RSS keys 5921 * @adap: the adapter 5922 * @key: 10-entry array holding the 320-bit RSS key 5923 * @idx: which RSS key to write 5924 * @sleep_ok: if true we may sleep while awaiting command completion 5925 * 5926 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5927 * 0..15 the corresponding entry in the RSS key table is written, 5928 * otherwise the global RSS key is written. 5929 */ 5930 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5931 bool sleep_ok) 5932 { 5933 u8 rss_key_addr_cnt = 16; 5934 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5935 5936 /* 5937 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5938 * allows access to key addresses 16-63 by using KeyWrAddrX 5939 * as index[5:4](upper 2) into key table 5940 */ 5941 if ((chip_id(adap) > CHELSIO_T5) && 5942 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5943 rss_key_addr_cnt = 32; 5944 5945 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5946 5947 if (idx >= 0 && idx < rss_key_addr_cnt) { 5948 if (rss_key_addr_cnt > 16) 5949 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5950 vrt | V_KEYWRADDRX(idx >> 4) | 5951 V_T6_VFWRADDR(idx) | F_KEYWREN); 5952 else 5953 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5954 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5955 } 5956 } 5957 5958 /** 5959 * t4_read_rss_pf_config - read PF RSS Configuration Table 5960 * @adapter: the adapter 5961 * @index: the entry in the PF RSS table to read 5962 * @valp: where to store the returned value 5963 * @sleep_ok: if true we may sleep while awaiting command completion 5964 * 5965 * Reads the PF RSS Configuration Table at the specified index and returns 5966 * the value found there. 5967 */ 5968 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5969 u32 *valp, bool sleep_ok) 5970 { 5971 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5972 } 5973 5974 /** 5975 * t4_write_rss_pf_config - write PF RSS Configuration Table 5976 * @adapter: the adapter 5977 * @index: the entry in the VF RSS table to read 5978 * @val: the value to store 5979 * @sleep_ok: if true we may sleep while awaiting command completion 5980 * 5981 * Writes the PF RSS Configuration Table at the specified index with the 5982 * specified value. 5983 */ 5984 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5985 u32 val, bool sleep_ok) 5986 { 5987 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5988 sleep_ok); 5989 } 5990 5991 /** 5992 * t4_read_rss_vf_config - read VF RSS Configuration Table 5993 * @adapter: the adapter 5994 * @index: the entry in the VF RSS table to read 5995 * @vfl: where to store the returned VFL 5996 * @vfh: where to store the returned VFH 5997 * @sleep_ok: if true we may sleep while awaiting command completion 5998 * 5999 * Reads the VF RSS Configuration Table at the specified index and returns 6000 * the (VFL, VFH) values found there. 6001 */ 6002 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 6003 u32 *vfl, u32 *vfh, bool sleep_ok) 6004 { 6005 u32 vrt, mask, data; 6006 6007 if (chip_id(adapter) <= CHELSIO_T5) { 6008 mask = V_VFWRADDR(M_VFWRADDR); 6009 data = V_VFWRADDR(index); 6010 } else { 6011 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6012 data = V_T6_VFWRADDR(index); 6013 } 6014 /* 6015 * Request that the index'th VF Table values be read into VFL/VFH. 6016 */ 6017 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6018 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6019 vrt |= data | F_VFRDEN; 6020 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6021 6022 /* 6023 * Grab the VFL/VFH values ... 6024 */ 6025 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6026 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6027 } 6028 6029 /** 6030 * t4_write_rss_vf_config - write VF RSS Configuration Table 6031 * 6032 * @adapter: the adapter 6033 * @index: the entry in the VF RSS table to write 6034 * @vfl: the VFL to store 6035 * @vfh: the VFH to store 6036 * 6037 * Writes the VF RSS Configuration Table at the specified index with the 6038 * specified (VFL, VFH) values. 6039 */ 6040 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 6041 u32 vfl, u32 vfh, bool sleep_ok) 6042 { 6043 u32 vrt, mask, data; 6044 6045 if (chip_id(adapter) <= CHELSIO_T5) { 6046 mask = V_VFWRADDR(M_VFWRADDR); 6047 data = V_VFWRADDR(index); 6048 } else { 6049 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6050 data = V_T6_VFWRADDR(index); 6051 } 6052 6053 /* 6054 * Load up VFL/VFH with the values to be written ... 6055 */ 6056 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6057 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6058 6059 /* 6060 * Write the VFL/VFH into the VF Table at index'th location. 6061 */ 6062 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6063 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6064 vrt |= data | F_VFRDEN; 6065 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6066 } 6067 6068 /** 6069 * t4_read_rss_pf_map - read PF RSS Map 6070 * @adapter: the adapter 6071 * @sleep_ok: if true we may sleep while awaiting command completion 6072 * 6073 * Reads the PF RSS Map register and returns its value. 6074 */ 6075 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 6076 { 6077 u32 pfmap; 6078 6079 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6080 6081 return pfmap; 6082 } 6083 6084 /** 6085 * t4_write_rss_pf_map - write PF RSS Map 6086 * @adapter: the adapter 6087 * @pfmap: PF RSS Map value 6088 * 6089 * Writes the specified value to the PF RSS Map register. 6090 */ 6091 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 6092 { 6093 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6094 } 6095 6096 /** 6097 * t4_read_rss_pf_mask - read PF RSS Mask 6098 * @adapter: the adapter 6099 * @sleep_ok: if true we may sleep while awaiting command completion 6100 * 6101 * Reads the PF RSS Mask register and returns its value. 6102 */ 6103 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 6104 { 6105 u32 pfmask; 6106 6107 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6108 6109 return pfmask; 6110 } 6111 6112 /** 6113 * t4_write_rss_pf_mask - write PF RSS Mask 6114 * @adapter: the adapter 6115 * @pfmask: PF RSS Mask value 6116 * 6117 * Writes the specified value to the PF RSS Mask register. 6118 */ 6119 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 6120 { 6121 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6122 } 6123 6124 /** 6125 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 6126 * @adap: the adapter 6127 * @v4: holds the TCP/IP counter values 6128 * @v6: holds the TCP/IPv6 counter values 6129 * @sleep_ok: if true we may sleep while awaiting command completion 6130 * 6131 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6132 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6133 */ 6134 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6135 struct tp_tcp_stats *v6, bool sleep_ok) 6136 { 6137 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6138 6139 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6140 #define STAT(x) val[STAT_IDX(x)] 6141 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6142 6143 if (v4) { 6144 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6145 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6146 v4->tcp_out_rsts = STAT(OUT_RST); 6147 v4->tcp_in_segs = STAT64(IN_SEG); 6148 v4->tcp_out_segs = STAT64(OUT_SEG); 6149 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6150 } 6151 if (v6) { 6152 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6153 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6154 v6->tcp_out_rsts = STAT(OUT_RST); 6155 v6->tcp_in_segs = STAT64(IN_SEG); 6156 v6->tcp_out_segs = STAT64(OUT_SEG); 6157 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6158 } 6159 #undef STAT64 6160 #undef STAT 6161 #undef STAT_IDX 6162 } 6163 6164 /** 6165 * t4_tp_get_err_stats - read TP's error MIB counters 6166 * @adap: the adapter 6167 * @st: holds the counter values 6168 * @sleep_ok: if true we may sleep while awaiting command completion 6169 * 6170 * Returns the values of TP's error counters. 6171 */ 6172 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6173 bool sleep_ok) 6174 { 6175 int nchan = adap->chip_params->nchan; 6176 6177 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6178 sleep_ok); 6179 6180 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6181 sleep_ok); 6182 6183 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6184 sleep_ok); 6185 6186 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6187 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6188 6189 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6190 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6191 6192 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6193 sleep_ok); 6194 6195 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6196 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6197 6198 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6199 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6200 6201 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6202 sleep_ok); 6203 } 6204 6205 /** 6206 * t4_tp_get_err_stats - read TP's error MIB counters 6207 * @adap: the adapter 6208 * @st: holds the counter values 6209 * @sleep_ok: if true we may sleep while awaiting command completion 6210 * 6211 * Returns the values of TP's error counters. 6212 */ 6213 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st, 6214 bool sleep_ok) 6215 { 6216 int nchan = adap->chip_params->nchan; 6217 6218 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, 6219 sleep_ok); 6220 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, 6221 sleep_ok); 6222 } 6223 6224 /** 6225 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6226 * @adap: the adapter 6227 * @st: holds the counter values 6228 * 6229 * Returns the values of TP's proxy counters. 6230 */ 6231 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6232 bool sleep_ok) 6233 { 6234 int nchan = adap->chip_params->nchan; 6235 6236 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6237 } 6238 6239 /** 6240 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6241 * @adap: the adapter 6242 * @st: holds the counter values 6243 * @sleep_ok: if true we may sleep while awaiting command completion 6244 * 6245 * Returns the values of TP's CPL counters. 6246 */ 6247 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6248 bool sleep_ok) 6249 { 6250 int nchan = adap->chip_params->nchan; 6251 6252 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6253 6254 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6255 } 6256 6257 /** 6258 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6259 * @adap: the adapter 6260 * @st: holds the counter values 6261 * 6262 * Returns the values of TP's RDMA counters. 6263 */ 6264 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6265 bool sleep_ok) 6266 { 6267 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6268 sleep_ok); 6269 } 6270 6271 /** 6272 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6273 * @adap: the adapter 6274 * @idx: the port index 6275 * @st: holds the counter values 6276 * @sleep_ok: if true we may sleep while awaiting command completion 6277 * 6278 * Returns the values of TP's FCoE counters for the selected port. 6279 */ 6280 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6281 struct tp_fcoe_stats *st, bool sleep_ok) 6282 { 6283 u32 val[2]; 6284 6285 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6286 sleep_ok); 6287 6288 t4_tp_mib_read(adap, &st->frames_drop, 1, 6289 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6290 6291 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6292 sleep_ok); 6293 6294 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6295 } 6296 6297 /** 6298 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6299 * @adap: the adapter 6300 * @st: holds the counter values 6301 * @sleep_ok: if true we may sleep while awaiting command completion 6302 * 6303 * Returns the values of TP's counters for non-TCP directly-placed packets. 6304 */ 6305 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6306 bool sleep_ok) 6307 { 6308 u32 val[4]; 6309 6310 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6311 6312 st->frames = val[0]; 6313 st->drops = val[1]; 6314 st->octets = ((u64)val[2] << 32) | val[3]; 6315 } 6316 6317 /** 6318 * t4_tp_get_tid_stats - read TP's tid MIB counters. 6319 * @adap: the adapter 6320 * @st: holds the counter values 6321 * @sleep_ok: if true we may sleep while awaiting command completion 6322 * 6323 * Returns the values of TP's counters for tids. 6324 */ 6325 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st, 6326 bool sleep_ok) 6327 { 6328 6329 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); 6330 } 6331 6332 /** 6333 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6334 * @adap: the adapter 6335 * @mtus: where to store the MTU values 6336 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6337 * 6338 * Reads the HW path MTU table. 6339 */ 6340 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6341 { 6342 u32 v; 6343 int i; 6344 6345 for (i = 0; i < NMTUS; ++i) { 6346 t4_write_reg(adap, A_TP_MTU_TABLE, 6347 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6348 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6349 mtus[i] = G_MTUVALUE(v); 6350 if (mtu_log) 6351 mtu_log[i] = G_MTUWIDTH(v); 6352 } 6353 } 6354 6355 /** 6356 * t4_read_cong_tbl - reads the congestion control table 6357 * @adap: the adapter 6358 * @incr: where to store the alpha values 6359 * 6360 * Reads the additive increments programmed into the HW congestion 6361 * control table. 6362 */ 6363 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6364 { 6365 unsigned int mtu, w; 6366 6367 for (mtu = 0; mtu < NMTUS; ++mtu) 6368 for (w = 0; w < NCCTRL_WIN; ++w) { 6369 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6370 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6371 incr[mtu][w] = (u16)t4_read_reg(adap, 6372 A_TP_CCTRL_TABLE) & 0x1fff; 6373 } 6374 } 6375 6376 /** 6377 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6378 * @adap: the adapter 6379 * @addr: the indirect TP register address 6380 * @mask: specifies the field within the register to modify 6381 * @val: new value for the field 6382 * 6383 * Sets a field of an indirect TP register to the given value. 6384 */ 6385 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6386 unsigned int mask, unsigned int val) 6387 { 6388 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6389 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6390 t4_write_reg(adap, A_TP_PIO_DATA, val); 6391 } 6392 6393 /** 6394 * init_cong_ctrl - initialize congestion control parameters 6395 * @a: the alpha values for congestion control 6396 * @b: the beta values for congestion control 6397 * 6398 * Initialize the congestion control parameters. 6399 */ 6400 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6401 { 6402 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6403 a[9] = 2; 6404 a[10] = 3; 6405 a[11] = 4; 6406 a[12] = 5; 6407 a[13] = 6; 6408 a[14] = 7; 6409 a[15] = 8; 6410 a[16] = 9; 6411 a[17] = 10; 6412 a[18] = 14; 6413 a[19] = 17; 6414 a[20] = 21; 6415 a[21] = 25; 6416 a[22] = 30; 6417 a[23] = 35; 6418 a[24] = 45; 6419 a[25] = 60; 6420 a[26] = 80; 6421 a[27] = 100; 6422 a[28] = 200; 6423 a[29] = 300; 6424 a[30] = 400; 6425 a[31] = 500; 6426 6427 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6428 b[9] = b[10] = 1; 6429 b[11] = b[12] = 2; 6430 b[13] = b[14] = b[15] = b[16] = 3; 6431 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6432 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6433 b[28] = b[29] = 6; 6434 b[30] = b[31] = 7; 6435 } 6436 6437 /* The minimum additive increment value for the congestion control table */ 6438 #define CC_MIN_INCR 2U 6439 6440 /** 6441 * t4_load_mtus - write the MTU and congestion control HW tables 6442 * @adap: the adapter 6443 * @mtus: the values for the MTU table 6444 * @alpha: the values for the congestion control alpha parameter 6445 * @beta: the values for the congestion control beta parameter 6446 * 6447 * Write the HW MTU table with the supplied MTUs and the high-speed 6448 * congestion control table with the supplied alpha, beta, and MTUs. 6449 * We write the two tables together because the additive increments 6450 * depend on the MTUs. 6451 */ 6452 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6453 const unsigned short *alpha, const unsigned short *beta) 6454 { 6455 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6456 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6457 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6458 28672, 40960, 57344, 81920, 114688, 163840, 229376 6459 }; 6460 6461 unsigned int i, w; 6462 6463 for (i = 0; i < NMTUS; ++i) { 6464 unsigned int mtu = mtus[i]; 6465 unsigned int log2 = fls(mtu); 6466 6467 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6468 log2--; 6469 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6470 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6471 6472 for (w = 0; w < NCCTRL_WIN; ++w) { 6473 unsigned int inc; 6474 6475 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6476 CC_MIN_INCR); 6477 6478 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6479 (w << 16) | (beta[w] << 13) | inc); 6480 } 6481 } 6482 } 6483 6484 /** 6485 * t4_set_pace_tbl - set the pace table 6486 * @adap: the adapter 6487 * @pace_vals: the pace values in microseconds 6488 * @start: index of the first entry in the HW pace table to set 6489 * @n: how many entries to set 6490 * 6491 * Sets (a subset of the) HW pace table. 6492 */ 6493 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6494 unsigned int start, unsigned int n) 6495 { 6496 unsigned int vals[NTX_SCHED], i; 6497 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6498 6499 if (n > NTX_SCHED) 6500 return -ERANGE; 6501 6502 /* convert values from us to dack ticks, rounding to closest value */ 6503 for (i = 0; i < n; i++, pace_vals++) { 6504 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6505 if (vals[i] > 0x7ff) 6506 return -ERANGE; 6507 if (*pace_vals && vals[i] == 0) 6508 return -ERANGE; 6509 } 6510 for (i = 0; i < n; i++, start++) 6511 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6512 return 0; 6513 } 6514 6515 /** 6516 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6517 * @adap: the adapter 6518 * @kbps: target rate in Kbps 6519 * @sched: the scheduler index 6520 * 6521 * Configure a Tx HW scheduler for the target rate. 6522 */ 6523 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6524 { 6525 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6526 unsigned int clk = adap->params.vpd.cclk * 1000; 6527 unsigned int selected_cpt = 0, selected_bpt = 0; 6528 6529 if (kbps > 0) { 6530 kbps *= 125; /* -> bytes */ 6531 for (cpt = 1; cpt <= 255; cpt++) { 6532 tps = clk / cpt; 6533 bpt = (kbps + tps / 2) / tps; 6534 if (bpt > 0 && bpt <= 255) { 6535 v = bpt * tps; 6536 delta = v >= kbps ? v - kbps : kbps - v; 6537 if (delta < mindelta) { 6538 mindelta = delta; 6539 selected_cpt = cpt; 6540 selected_bpt = bpt; 6541 } 6542 } else if (selected_cpt) 6543 break; 6544 } 6545 if (!selected_cpt) 6546 return -EINVAL; 6547 } 6548 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6549 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6550 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6551 if (sched & 1) 6552 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6553 else 6554 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6555 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6556 return 0; 6557 } 6558 6559 /** 6560 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6561 * @adap: the adapter 6562 * @sched: the scheduler index 6563 * @ipg: the interpacket delay in tenths of nanoseconds 6564 * 6565 * Set the interpacket delay for a HW packet rate scheduler. 6566 */ 6567 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6568 { 6569 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6570 6571 /* convert ipg to nearest number of core clocks */ 6572 ipg *= core_ticks_per_usec(adap); 6573 ipg = (ipg + 5000) / 10000; 6574 if (ipg > M_TXTIMERSEPQ0) 6575 return -EINVAL; 6576 6577 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6578 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6579 if (sched & 1) 6580 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6581 else 6582 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6583 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6584 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6585 return 0; 6586 } 6587 6588 /* 6589 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6590 * clocks. The formula is 6591 * 6592 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6593 * 6594 * which is equivalent to 6595 * 6596 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6597 */ 6598 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6599 { 6600 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6601 6602 return v * 62 + v / 2; 6603 } 6604 6605 /** 6606 * t4_get_chan_txrate - get the current per channel Tx rates 6607 * @adap: the adapter 6608 * @nic_rate: rates for NIC traffic 6609 * @ofld_rate: rates for offloaded traffic 6610 * 6611 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6612 * for each channel. 6613 */ 6614 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6615 { 6616 u32 v; 6617 6618 v = t4_read_reg(adap, A_TP_TX_TRATE); 6619 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6620 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6621 if (adap->chip_params->nchan > 2) { 6622 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6623 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6624 } 6625 6626 v = t4_read_reg(adap, A_TP_TX_ORATE); 6627 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6628 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6629 if (adap->chip_params->nchan > 2) { 6630 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6631 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6632 } 6633 } 6634 6635 /** 6636 * t4_set_trace_filter - configure one of the tracing filters 6637 * @adap: the adapter 6638 * @tp: the desired trace filter parameters 6639 * @idx: which filter to configure 6640 * @enable: whether to enable or disable the filter 6641 * 6642 * Configures one of the tracing filters available in HW. If @tp is %NULL 6643 * it indicates that the filter is already written in the register and it 6644 * just needs to be enabled or disabled. 6645 */ 6646 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6647 int idx, int enable) 6648 { 6649 int i, ofst = idx * 4; 6650 u32 data_reg, mask_reg, cfg; 6651 u32 multitrc = F_TRCMULTIFILTER; 6652 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6653 6654 if (idx < 0 || idx >= NTRACE) 6655 return -EINVAL; 6656 6657 if (tp == NULL || !enable) { 6658 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6659 enable ? en : 0); 6660 return 0; 6661 } 6662 6663 /* 6664 * TODO - After T4 data book is updated, specify the exact 6665 * section below. 6666 * 6667 * See T4 data book - MPS section for a complete description 6668 * of the below if..else handling of A_MPS_TRC_CFG register 6669 * value. 6670 */ 6671 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6672 if (cfg & F_TRCMULTIFILTER) { 6673 /* 6674 * If multiple tracers are enabled, then maximum 6675 * capture size is 2.5KB (FIFO size of a single channel) 6676 * minus 2 flits for CPL_TRACE_PKT header. 6677 */ 6678 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6679 return -EINVAL; 6680 } else { 6681 /* 6682 * If multiple tracers are disabled, to avoid deadlocks 6683 * maximum packet capture size of 9600 bytes is recommended. 6684 * Also in this mode, only trace0 can be enabled and running. 6685 */ 6686 multitrc = 0; 6687 if (tp->snap_len > 9600 || idx) 6688 return -EINVAL; 6689 } 6690 6691 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6692 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6693 tp->min_len > M_TFMINPKTSIZE) 6694 return -EINVAL; 6695 6696 /* stop the tracer we'll be changing */ 6697 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6698 6699 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6700 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6701 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6702 6703 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6704 t4_write_reg(adap, data_reg, tp->data[i]); 6705 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6706 } 6707 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6708 V_TFCAPTUREMAX(tp->snap_len) | 6709 V_TFMINPKTSIZE(tp->min_len)); 6710 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6711 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6712 (is_t4(adap) ? 6713 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6714 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6715 6716 return 0; 6717 } 6718 6719 /** 6720 * t4_get_trace_filter - query one of the tracing filters 6721 * @adap: the adapter 6722 * @tp: the current trace filter parameters 6723 * @idx: which trace filter to query 6724 * @enabled: non-zero if the filter is enabled 6725 * 6726 * Returns the current settings of one of the HW tracing filters. 6727 */ 6728 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6729 int *enabled) 6730 { 6731 u32 ctla, ctlb; 6732 int i, ofst = idx * 4; 6733 u32 data_reg, mask_reg; 6734 6735 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6736 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6737 6738 if (is_t4(adap)) { 6739 *enabled = !!(ctla & F_TFEN); 6740 tp->port = G_TFPORT(ctla); 6741 tp->invert = !!(ctla & F_TFINVERTMATCH); 6742 } else { 6743 *enabled = !!(ctla & F_T5_TFEN); 6744 tp->port = G_T5_TFPORT(ctla); 6745 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6746 } 6747 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6748 tp->min_len = G_TFMINPKTSIZE(ctlb); 6749 tp->skip_ofst = G_TFOFFSET(ctla); 6750 tp->skip_len = G_TFLENGTH(ctla); 6751 6752 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6753 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6754 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6755 6756 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6757 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6758 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6759 } 6760 } 6761 6762 /** 6763 * t4_pmtx_get_stats - returns the HW stats from PMTX 6764 * @adap: the adapter 6765 * @cnt: where to store the count statistics 6766 * @cycles: where to store the cycle statistics 6767 * 6768 * Returns performance statistics from PMTX. 6769 */ 6770 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6771 { 6772 int i; 6773 u32 data[2]; 6774 6775 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6776 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6777 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6778 if (is_t4(adap)) 6779 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6780 else { 6781 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6782 A_PM_TX_DBG_DATA, data, 2, 6783 A_PM_TX_DBG_STAT_MSB); 6784 cycles[i] = (((u64)data[0] << 32) | data[1]); 6785 } 6786 } 6787 } 6788 6789 /** 6790 * t4_pmrx_get_stats - returns the HW stats from PMRX 6791 * @adap: the adapter 6792 * @cnt: where to store the count statistics 6793 * @cycles: where to store the cycle statistics 6794 * 6795 * Returns performance statistics from PMRX. 6796 */ 6797 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6798 { 6799 int i; 6800 u32 data[2]; 6801 6802 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6803 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6804 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6805 if (is_t4(adap)) { 6806 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6807 } else { 6808 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6809 A_PM_RX_DBG_DATA, data, 2, 6810 A_PM_RX_DBG_STAT_MSB); 6811 cycles[i] = (((u64)data[0] << 32) | data[1]); 6812 } 6813 } 6814 } 6815 6816 /** 6817 * t4_get_mps_bg_map - return the buffer groups associated with a port 6818 * @adap: the adapter 6819 * @idx: the port index 6820 * 6821 * Returns a bitmap indicating which MPS buffer groups are associated 6822 * with the given port. Bit i is set if buffer group i is used by the 6823 * port. 6824 */ 6825 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6826 { 6827 u32 n; 6828 6829 if (adap->params.mps_bg_map) 6830 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6831 6832 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6833 if (n == 0) 6834 return idx == 0 ? 0xf : 0; 6835 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6836 return idx < 2 ? (3 << (2 * idx)) : 0; 6837 return 1 << idx; 6838 } 6839 6840 /* 6841 * TP RX e-channels associated with the port. 6842 */ 6843 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6844 { 6845 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6846 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; 6847 6848 if (n == 0) 6849 return idx == 0 ? all_chan : 0; 6850 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6851 return idx < 2 ? (3 << (2 * idx)) : 0; 6852 return 1 << idx; 6853 } 6854 6855 /* 6856 * TP RX c-channel associated with the port. 6857 */ 6858 static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx) 6859 { 6860 u32 param, val; 6861 int ret; 6862 6863 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6864 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPCHMAP)); 6865 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 6866 if (!ret) 6867 return (val >> (8 * idx)) & 0xff; 6868 6869 return 0; 6870 } 6871 6872 /** 6873 * t4_get_port_type_description - return Port Type string description 6874 * @port_type: firmware Port Type enumeration 6875 */ 6876 const char *t4_get_port_type_description(enum fw_port_type port_type) 6877 { 6878 static const char *const port_type_description[] = { 6879 "Fiber_XFI", 6880 "Fiber_XAUI", 6881 "BT_SGMII", 6882 "BT_XFI", 6883 "BT_XAUI", 6884 "KX4", 6885 "CX4", 6886 "KX", 6887 "KR", 6888 "SFP", 6889 "BP_AP", 6890 "BP4_AP", 6891 "QSFP_10G", 6892 "QSA", 6893 "QSFP", 6894 "BP40_BA", 6895 "KR4_100G", 6896 "CR4_QSFP", 6897 "CR_QSFP", 6898 "CR2_QSFP", 6899 "SFP28", 6900 "KR_SFP28", 6901 }; 6902 6903 if (port_type < ARRAY_SIZE(port_type_description)) 6904 return port_type_description[port_type]; 6905 return "UNKNOWN"; 6906 } 6907 6908 /** 6909 * t4_get_port_stats_offset - collect port stats relative to a previous 6910 * snapshot 6911 * @adap: The adapter 6912 * @idx: The port 6913 * @stats: Current stats to fill 6914 * @offset: Previous stats snapshot 6915 */ 6916 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6917 struct port_stats *stats, 6918 struct port_stats *offset) 6919 { 6920 u64 *s, *o; 6921 int i; 6922 6923 t4_get_port_stats(adap, idx, stats); 6924 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6925 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6926 i++, s++, o++) 6927 *s -= *o; 6928 } 6929 6930 /** 6931 * t4_get_port_stats - collect port statistics 6932 * @adap: the adapter 6933 * @idx: the port index 6934 * @p: the stats structure to fill 6935 * 6936 * Collect statistics related to the given port from HW. 6937 */ 6938 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6939 { 6940 struct port_info *pi = adap->port[idx]; 6941 u32 bgmap = pi->mps_bg_map; 6942 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6943 6944 #define GET_STAT(name) \ 6945 t4_read_reg64(adap, \ 6946 (is_t4(adap) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L) : \ 6947 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L))) 6948 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6949 6950 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6951 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6952 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6953 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6954 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6955 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6956 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6957 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6958 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6959 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6960 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6961 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6962 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6963 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6964 p->tx_drop = GET_STAT(TX_PORT_DROP); 6965 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6966 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6967 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6968 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6969 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6970 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6971 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6972 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6973 6974 if (chip_id(adap) >= CHELSIO_T5) { 6975 if (stat_ctl & F_COUNTPAUSESTATTX) { 6976 p->tx_frames -= p->tx_pause; 6977 p->tx_octets -= p->tx_pause * 64; 6978 } 6979 if (stat_ctl & F_COUNTPAUSEMCTX) 6980 p->tx_mcast_frames -= p->tx_pause; 6981 } 6982 6983 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6984 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6985 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6986 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6987 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6988 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6989 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6990 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6991 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6992 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6993 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6994 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6995 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6996 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6997 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6998 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6999 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 7000 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 7001 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 7002 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 7003 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 7004 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 7005 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 7006 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 7007 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 7008 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 7009 7010 if (pi->fcs_reg != -1) 7011 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base; 7012 7013 if (chip_id(adap) >= CHELSIO_T5) { 7014 if (stat_ctl & F_COUNTPAUSESTATRX) { 7015 p->rx_frames -= p->rx_pause; 7016 p->rx_octets -= p->rx_pause * 64; 7017 } 7018 if (stat_ctl & F_COUNTPAUSEMCRX) 7019 p->rx_mcast_frames -= p->rx_pause; 7020 } 7021 7022 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 7023 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 7024 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 7025 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 7026 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 7027 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 7028 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 7029 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 7030 7031 #undef GET_STAT 7032 #undef GET_STAT_COM 7033 } 7034 7035 /** 7036 * t4_get_lb_stats - collect loopback port statistics 7037 * @adap: the adapter 7038 * @idx: the loopback port index 7039 * @p: the stats structure to fill 7040 * 7041 * Return HW statistics for the given loopback port. 7042 */ 7043 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 7044 { 7045 7046 #define GET_STAT(name) \ 7047 t4_read_reg64(adap, \ 7048 (is_t4(adap) ? \ 7049 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 7050 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 7051 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 7052 7053 p->octets = GET_STAT(BYTES); 7054 p->frames = GET_STAT(FRAMES); 7055 p->bcast_frames = GET_STAT(BCAST); 7056 p->mcast_frames = GET_STAT(MCAST); 7057 p->ucast_frames = GET_STAT(UCAST); 7058 p->error_frames = GET_STAT(ERROR); 7059 7060 p->frames_64 = GET_STAT(64B); 7061 p->frames_65_127 = GET_STAT(65B_127B); 7062 p->frames_128_255 = GET_STAT(128B_255B); 7063 p->frames_256_511 = GET_STAT(256B_511B); 7064 p->frames_512_1023 = GET_STAT(512B_1023B); 7065 p->frames_1024_1518 = GET_STAT(1024B_1518B); 7066 p->frames_1519_max = GET_STAT(1519B_MAX); 7067 p->drop = GET_STAT(DROP_FRAMES); 7068 7069 if (idx < adap->params.nports) { 7070 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; 7071 7072 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 7073 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 7074 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 7075 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 7076 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 7077 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 7078 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 7079 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 7080 } 7081 7082 #undef GET_STAT 7083 #undef GET_STAT_COM 7084 } 7085 7086 /** 7087 * t4_wol_magic_enable - enable/disable magic packet WoL 7088 * @adap: the adapter 7089 * @port: the physical port index 7090 * @addr: MAC address expected in magic packets, %NULL to disable 7091 * 7092 * Enables/disables magic packet wake-on-LAN for the selected port. 7093 */ 7094 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 7095 const u8 *addr) 7096 { 7097 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 7098 7099 if (is_t4(adap)) { 7100 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 7101 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 7102 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7103 } else { 7104 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 7105 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 7106 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7107 } 7108 7109 if (addr) { 7110 t4_write_reg(adap, mag_id_reg_l, 7111 (addr[2] << 24) | (addr[3] << 16) | 7112 (addr[4] << 8) | addr[5]); 7113 t4_write_reg(adap, mag_id_reg_h, 7114 (addr[0] << 8) | addr[1]); 7115 } 7116 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 7117 V_MAGICEN(addr != NULL)); 7118 } 7119 7120 /** 7121 * t4_wol_pat_enable - enable/disable pattern-based WoL 7122 * @adap: the adapter 7123 * @port: the physical port index 7124 * @map: bitmap of which HW pattern filters to set 7125 * @mask0: byte mask for bytes 0-63 of a packet 7126 * @mask1: byte mask for bytes 64-127 of a packet 7127 * @crc: Ethernet CRC for selected bytes 7128 * @enable: enable/disable switch 7129 * 7130 * Sets the pattern filters indicated in @map to mask out the bytes 7131 * specified in @mask0/@mask1 in received packets and compare the CRC of 7132 * the resulting packet against @crc. If @enable is %true pattern-based 7133 * WoL is enabled, otherwise disabled. 7134 */ 7135 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 7136 u64 mask0, u64 mask1, unsigned int crc, bool enable) 7137 { 7138 int i; 7139 u32 port_cfg_reg; 7140 7141 if (is_t4(adap)) 7142 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7143 else 7144 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7145 7146 if (!enable) { 7147 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 7148 return 0; 7149 } 7150 if (map > 0xff) 7151 return -EINVAL; 7152 7153 #define EPIO_REG(name) \ 7154 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 7155 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 7156 7157 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 7158 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 7159 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 7160 7161 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 7162 if (!(map & 1)) 7163 continue; 7164 7165 /* write byte masks */ 7166 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 7167 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 7168 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7169 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7170 return -ETIMEDOUT; 7171 7172 /* write CRC */ 7173 t4_write_reg(adap, EPIO_REG(DATA0), crc); 7174 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 7175 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7176 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7177 return -ETIMEDOUT; 7178 } 7179 #undef EPIO_REG 7180 7181 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 7182 return 0; 7183 } 7184 7185 /* t4_mk_filtdelwr - create a delete filter WR 7186 * @ftid: the filter ID 7187 * @wr: the filter work request to populate 7188 * @qid: ingress queue to receive the delete notification 7189 * 7190 * Creates a filter work request to delete the supplied filter. If @qid is 7191 * negative the delete notification is suppressed. 7192 */ 7193 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7194 { 7195 memset(wr, 0, sizeof(*wr)); 7196 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7197 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7198 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7199 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7200 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7201 if (qid >= 0) 7202 wr->rx_chan_rx_rpl_iq = 7203 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7204 } 7205 7206 #define INIT_CMD(var, cmd, rd_wr) do { \ 7207 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7208 F_FW_CMD_REQUEST | \ 7209 F_FW_CMD_##rd_wr); \ 7210 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7211 } while (0) 7212 7213 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7214 u32 addr, u32 val) 7215 { 7216 u32 ldst_addrspace; 7217 struct fw_ldst_cmd c; 7218 7219 memset(&c, 0, sizeof(c)); 7220 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7221 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7222 F_FW_CMD_REQUEST | 7223 F_FW_CMD_WRITE | 7224 ldst_addrspace); 7225 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7226 c.u.addrval.addr = cpu_to_be32(addr); 7227 c.u.addrval.val = cpu_to_be32(val); 7228 7229 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7230 } 7231 7232 /** 7233 * t4_mdio_rd - read a PHY register through MDIO 7234 * @adap: the adapter 7235 * @mbox: mailbox to use for the FW command 7236 * @phy_addr: the PHY address 7237 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7238 * @reg: the register to read 7239 * @valp: where to store the value 7240 * 7241 * Issues a FW command through the given mailbox to read a PHY register. 7242 */ 7243 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7244 unsigned int mmd, unsigned int reg, unsigned int *valp) 7245 { 7246 int ret; 7247 u32 ldst_addrspace; 7248 struct fw_ldst_cmd c; 7249 7250 memset(&c, 0, sizeof(c)); 7251 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7252 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7253 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7254 ldst_addrspace); 7255 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7256 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7257 V_FW_LDST_CMD_MMD(mmd)); 7258 c.u.mdio.raddr = cpu_to_be16(reg); 7259 7260 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7261 if (ret == 0) 7262 *valp = be16_to_cpu(c.u.mdio.rval); 7263 return ret; 7264 } 7265 7266 /** 7267 * t4_mdio_wr - write a PHY register through MDIO 7268 * @adap: the adapter 7269 * @mbox: mailbox to use for the FW command 7270 * @phy_addr: the PHY address 7271 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7272 * @reg: the register to write 7273 * @valp: value to write 7274 * 7275 * Issues a FW command through the given mailbox to write a PHY register. 7276 */ 7277 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7278 unsigned int mmd, unsigned int reg, unsigned int val) 7279 { 7280 u32 ldst_addrspace; 7281 struct fw_ldst_cmd c; 7282 7283 memset(&c, 0, sizeof(c)); 7284 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7285 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7286 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7287 ldst_addrspace); 7288 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7289 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7290 V_FW_LDST_CMD_MMD(mmd)); 7291 c.u.mdio.raddr = cpu_to_be16(reg); 7292 c.u.mdio.rval = cpu_to_be16(val); 7293 7294 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7295 } 7296 7297 /** 7298 * 7299 * t4_sge_decode_idma_state - decode the idma state 7300 * @adap: the adapter 7301 * @state: the state idma is stuck in 7302 */ 7303 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7304 { 7305 static const char * const t4_decode[] = { 7306 "IDMA_IDLE", 7307 "IDMA_PUSH_MORE_CPL_FIFO", 7308 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7309 "Not used", 7310 "IDMA_PHYSADDR_SEND_PCIEHDR", 7311 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7312 "IDMA_PHYSADDR_SEND_PAYLOAD", 7313 "IDMA_SEND_FIFO_TO_IMSG", 7314 "IDMA_FL_REQ_DATA_FL_PREP", 7315 "IDMA_FL_REQ_DATA_FL", 7316 "IDMA_FL_DROP", 7317 "IDMA_FL_H_REQ_HEADER_FL", 7318 "IDMA_FL_H_SEND_PCIEHDR", 7319 "IDMA_FL_H_PUSH_CPL_FIFO", 7320 "IDMA_FL_H_SEND_CPL", 7321 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7322 "IDMA_FL_H_SEND_IP_HDR", 7323 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7324 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7325 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7326 "IDMA_FL_D_SEND_PCIEHDR", 7327 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7328 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7329 "IDMA_FL_SEND_PCIEHDR", 7330 "IDMA_FL_PUSH_CPL_FIFO", 7331 "IDMA_FL_SEND_CPL", 7332 "IDMA_FL_SEND_PAYLOAD_FIRST", 7333 "IDMA_FL_SEND_PAYLOAD", 7334 "IDMA_FL_REQ_NEXT_DATA_FL", 7335 "IDMA_FL_SEND_NEXT_PCIEHDR", 7336 "IDMA_FL_SEND_PADDING", 7337 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7338 "IDMA_FL_SEND_FIFO_TO_IMSG", 7339 "IDMA_FL_REQ_DATAFL_DONE", 7340 "IDMA_FL_REQ_HEADERFL_DONE", 7341 }; 7342 static const char * const t5_decode[] = { 7343 "IDMA_IDLE", 7344 "IDMA_ALMOST_IDLE", 7345 "IDMA_PUSH_MORE_CPL_FIFO", 7346 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7347 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7348 "IDMA_PHYSADDR_SEND_PCIEHDR", 7349 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7350 "IDMA_PHYSADDR_SEND_PAYLOAD", 7351 "IDMA_SEND_FIFO_TO_IMSG", 7352 "IDMA_FL_REQ_DATA_FL", 7353 "IDMA_FL_DROP", 7354 "IDMA_FL_DROP_SEND_INC", 7355 "IDMA_FL_H_REQ_HEADER_FL", 7356 "IDMA_FL_H_SEND_PCIEHDR", 7357 "IDMA_FL_H_PUSH_CPL_FIFO", 7358 "IDMA_FL_H_SEND_CPL", 7359 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7360 "IDMA_FL_H_SEND_IP_HDR", 7361 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7362 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7363 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7364 "IDMA_FL_D_SEND_PCIEHDR", 7365 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7366 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7367 "IDMA_FL_SEND_PCIEHDR", 7368 "IDMA_FL_PUSH_CPL_FIFO", 7369 "IDMA_FL_SEND_CPL", 7370 "IDMA_FL_SEND_PAYLOAD_FIRST", 7371 "IDMA_FL_SEND_PAYLOAD", 7372 "IDMA_FL_REQ_NEXT_DATA_FL", 7373 "IDMA_FL_SEND_NEXT_PCIEHDR", 7374 "IDMA_FL_SEND_PADDING", 7375 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7376 }; 7377 static const char * const t6_decode[] = { 7378 "IDMA_IDLE", 7379 "IDMA_PUSH_MORE_CPL_FIFO", 7380 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7381 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7382 "IDMA_PHYSADDR_SEND_PCIEHDR", 7383 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7384 "IDMA_PHYSADDR_SEND_PAYLOAD", 7385 "IDMA_FL_REQ_DATA_FL", 7386 "IDMA_FL_DROP", 7387 "IDMA_FL_DROP_SEND_INC", 7388 "IDMA_FL_H_REQ_HEADER_FL", 7389 "IDMA_FL_H_SEND_PCIEHDR", 7390 "IDMA_FL_H_PUSH_CPL_FIFO", 7391 "IDMA_FL_H_SEND_CPL", 7392 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7393 "IDMA_FL_H_SEND_IP_HDR", 7394 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7395 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7396 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7397 "IDMA_FL_D_SEND_PCIEHDR", 7398 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7399 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7400 "IDMA_FL_SEND_PCIEHDR", 7401 "IDMA_FL_PUSH_CPL_FIFO", 7402 "IDMA_FL_SEND_CPL", 7403 "IDMA_FL_SEND_PAYLOAD_FIRST", 7404 "IDMA_FL_SEND_PAYLOAD", 7405 "IDMA_FL_REQ_NEXT_DATA_FL", 7406 "IDMA_FL_SEND_NEXT_PCIEHDR", 7407 "IDMA_FL_SEND_PADDING", 7408 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7409 }; 7410 static const u32 sge_regs[] = { 7411 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7412 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7413 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7414 }; 7415 const char * const *sge_idma_decode; 7416 int sge_idma_decode_nstates; 7417 int i; 7418 unsigned int chip_version = chip_id(adapter); 7419 7420 /* Select the right set of decode strings to dump depending on the 7421 * adapter chip type. 7422 */ 7423 switch (chip_version) { 7424 case CHELSIO_T4: 7425 sge_idma_decode = (const char * const *)t4_decode; 7426 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7427 break; 7428 7429 case CHELSIO_T5: 7430 sge_idma_decode = (const char * const *)t5_decode; 7431 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7432 break; 7433 7434 case CHELSIO_T6: 7435 sge_idma_decode = (const char * const *)t6_decode; 7436 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7437 break; 7438 7439 default: 7440 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7441 return; 7442 } 7443 7444 if (state < sge_idma_decode_nstates) 7445 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7446 else 7447 CH_WARN(adapter, "idma state %d unknown\n", state); 7448 7449 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7450 CH_WARN(adapter, "SGE register %#x value %#x\n", 7451 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7452 } 7453 7454 /** 7455 * t4_sge_ctxt_flush - flush the SGE context cache 7456 * @adap: the adapter 7457 * @mbox: mailbox to use for the FW command 7458 * 7459 * Issues a FW command through the given mailbox to flush the 7460 * SGE context cache. 7461 */ 7462 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type) 7463 { 7464 int ret; 7465 u32 ldst_addrspace; 7466 struct fw_ldst_cmd c; 7467 7468 memset(&c, 0, sizeof(c)); 7469 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ? 7470 FW_LDST_ADDRSPC_SGE_EGRC : 7471 FW_LDST_ADDRSPC_SGE_INGC); 7472 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7473 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7474 ldst_addrspace); 7475 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7476 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7477 7478 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7479 return ret; 7480 } 7481 7482 /** 7483 * t4_fw_hello - establish communication with FW 7484 * @adap: the adapter 7485 * @mbox: mailbox to use for the FW command 7486 * @evt_mbox: mailbox to receive async FW events 7487 * @master: specifies the caller's willingness to be the device master 7488 * @state: returns the current device state (if non-NULL) 7489 * 7490 * Issues a command to establish communication with FW. Returns either 7491 * an error (negative integer) or the mailbox of the Master PF. 7492 */ 7493 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7494 enum dev_master master, enum dev_state *state) 7495 { 7496 int ret; 7497 struct fw_hello_cmd c; 7498 u32 v; 7499 unsigned int master_mbox; 7500 int retries = FW_CMD_HELLO_RETRIES; 7501 7502 retry: 7503 memset(&c, 0, sizeof(c)); 7504 INIT_CMD(c, HELLO, WRITE); 7505 c.err_to_clearinit = cpu_to_be32( 7506 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7507 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7508 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7509 mbox : M_FW_HELLO_CMD_MBMASTER) | 7510 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7511 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7512 F_FW_HELLO_CMD_CLEARINIT); 7513 7514 /* 7515 * Issue the HELLO command to the firmware. If it's not successful 7516 * but indicates that we got a "busy" or "timeout" condition, retry 7517 * the HELLO until we exhaust our retry limit. If we do exceed our 7518 * retry limit, check to see if the firmware left us any error 7519 * information and report that if so ... 7520 */ 7521 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7522 if (ret != FW_SUCCESS) { 7523 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7524 goto retry; 7525 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 7526 t4_report_fw_error(adap); 7527 return ret; 7528 } 7529 7530 v = be32_to_cpu(c.err_to_clearinit); 7531 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7532 if (state) { 7533 if (v & F_FW_HELLO_CMD_ERR) 7534 *state = DEV_STATE_ERR; 7535 else if (v & F_FW_HELLO_CMD_INIT) 7536 *state = DEV_STATE_INIT; 7537 else 7538 *state = DEV_STATE_UNINIT; 7539 } 7540 7541 /* 7542 * If we're not the Master PF then we need to wait around for the 7543 * Master PF Driver to finish setting up the adapter. 7544 * 7545 * Note that we also do this wait if we're a non-Master-capable PF and 7546 * there is no current Master PF; a Master PF may show up momentarily 7547 * and we wouldn't want to fail pointlessly. (This can happen when an 7548 * OS loads lots of different drivers rapidly at the same time). In 7549 * this case, the Master PF returned by the firmware will be 7550 * M_PCIE_FW_MASTER so the test below will work ... 7551 */ 7552 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7553 master_mbox != mbox) { 7554 int waiting = FW_CMD_HELLO_TIMEOUT; 7555 7556 /* 7557 * Wait for the firmware to either indicate an error or 7558 * initialized state. If we see either of these we bail out 7559 * and report the issue to the caller. If we exhaust the 7560 * "hello timeout" and we haven't exhausted our retries, try 7561 * again. Otherwise bail with a timeout error. 7562 */ 7563 for (;;) { 7564 u32 pcie_fw; 7565 7566 msleep(50); 7567 waiting -= 50; 7568 7569 /* 7570 * If neither Error nor Initialialized are indicated 7571 * by the firmware keep waiting till we exhaust our 7572 * timeout ... and then retry if we haven't exhausted 7573 * our retries ... 7574 */ 7575 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7576 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7577 if (waiting <= 0) { 7578 if (retries-- > 0) 7579 goto retry; 7580 7581 return -ETIMEDOUT; 7582 } 7583 continue; 7584 } 7585 7586 /* 7587 * We either have an Error or Initialized condition 7588 * report errors preferentially. 7589 */ 7590 if (state) { 7591 if (pcie_fw & F_PCIE_FW_ERR) 7592 *state = DEV_STATE_ERR; 7593 else if (pcie_fw & F_PCIE_FW_INIT) 7594 *state = DEV_STATE_INIT; 7595 } 7596 7597 /* 7598 * If we arrived before a Master PF was selected and 7599 * there's not a valid Master PF, grab its identity 7600 * for our caller. 7601 */ 7602 if (master_mbox == M_PCIE_FW_MASTER && 7603 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7604 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7605 break; 7606 } 7607 } 7608 7609 return master_mbox; 7610 } 7611 7612 /** 7613 * t4_fw_bye - end communication with FW 7614 * @adap: the adapter 7615 * @mbox: mailbox to use for the FW command 7616 * 7617 * Issues a command to terminate communication with FW. 7618 */ 7619 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7620 { 7621 struct fw_bye_cmd c; 7622 7623 memset(&c, 0, sizeof(c)); 7624 INIT_CMD(c, BYE, WRITE); 7625 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7626 } 7627 7628 /** 7629 * t4_fw_reset - issue a reset to FW 7630 * @adap: the adapter 7631 * @mbox: mailbox to use for the FW command 7632 * @reset: specifies the type of reset to perform 7633 * 7634 * Issues a reset command of the specified type to FW. 7635 */ 7636 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7637 { 7638 struct fw_reset_cmd c; 7639 7640 memset(&c, 0, sizeof(c)); 7641 INIT_CMD(c, RESET, WRITE); 7642 c.val = cpu_to_be32(reset); 7643 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7644 } 7645 7646 /** 7647 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7648 * @adap: the adapter 7649 * @mbox: mailbox to use for the FW RESET command (if desired) 7650 * @force: force uP into RESET even if FW RESET command fails 7651 * 7652 * Issues a RESET command to firmware (if desired) with a HALT indication 7653 * and then puts the microprocessor into RESET state. The RESET command 7654 * will only be issued if a legitimate mailbox is provided (mbox <= 7655 * M_PCIE_FW_MASTER). 7656 * 7657 * This is generally used in order for the host to safely manipulate the 7658 * adapter without fear of conflicting with whatever the firmware might 7659 * be doing. The only way out of this state is to RESTART the firmware 7660 * ... 7661 */ 7662 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7663 { 7664 int ret = 0; 7665 7666 /* 7667 * If a legitimate mailbox is provided, issue a RESET command 7668 * with a HALT indication. 7669 */ 7670 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7671 struct fw_reset_cmd c; 7672 7673 memset(&c, 0, sizeof(c)); 7674 INIT_CMD(c, RESET, WRITE); 7675 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7676 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7677 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7678 } 7679 7680 /* 7681 * Normally we won't complete the operation if the firmware RESET 7682 * command fails but if our caller insists we'll go ahead and put the 7683 * uP into RESET. This can be useful if the firmware is hung or even 7684 * missing ... We'll have to take the risk of putting the uP into 7685 * RESET without the cooperation of firmware in that case. 7686 * 7687 * We also force the firmware's HALT flag to be on in case we bypassed 7688 * the firmware RESET command above or we're dealing with old firmware 7689 * which doesn't have the HALT capability. This will serve as a flag 7690 * for the incoming firmware to know that it's coming out of a HALT 7691 * rather than a RESET ... if it's new enough to understand that ... 7692 */ 7693 if (ret == 0 || force) { 7694 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7695 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7696 F_PCIE_FW_HALT); 7697 } 7698 7699 /* 7700 * And we always return the result of the firmware RESET command 7701 * even when we force the uP into RESET ... 7702 */ 7703 return ret; 7704 } 7705 7706 /** 7707 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7708 * @adap: the adapter 7709 * 7710 * Restart firmware previously halted by t4_fw_halt(). On successful 7711 * return the previous PF Master remains as the new PF Master and there 7712 * is no need to issue a new HELLO command, etc. 7713 */ 7714 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7715 { 7716 int ms; 7717 7718 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7719 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7720 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7721 return FW_SUCCESS; 7722 msleep(100); 7723 ms += 100; 7724 } 7725 7726 return -ETIMEDOUT; 7727 } 7728 7729 /** 7730 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7731 * @adap: the adapter 7732 * @mbox: mailbox to use for the FW RESET command (if desired) 7733 * @fw_data: the firmware image to write 7734 * @size: image size 7735 * @force: force upgrade even if firmware doesn't cooperate 7736 * 7737 * Perform all of the steps necessary for upgrading an adapter's 7738 * firmware image. Normally this requires the cooperation of the 7739 * existing firmware in order to halt all existing activities 7740 * but if an invalid mailbox token is passed in we skip that step 7741 * (though we'll still put the adapter microprocessor into RESET in 7742 * that case). 7743 * 7744 * On successful return the new firmware will have been loaded and 7745 * the adapter will have been fully RESET losing all previous setup 7746 * state. On unsuccessful return the adapter may be completely hosed ... 7747 * positive errno indicates that the adapter is ~probably~ intact, a 7748 * negative errno indicates that things are looking bad ... 7749 */ 7750 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7751 const u8 *fw_data, unsigned int size, int force) 7752 { 7753 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7754 unsigned int bootstrap = 7755 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7756 int ret; 7757 7758 if (!t4_fw_matches_chip(adap, fw_hdr)) 7759 return -EINVAL; 7760 7761 if (!bootstrap) { 7762 ret = t4_fw_halt(adap, mbox, force); 7763 if (ret < 0 && !force) 7764 return ret; 7765 } 7766 7767 ret = t4_load_fw(adap, fw_data, size); 7768 if (ret < 0 || bootstrap) 7769 return ret; 7770 7771 return t4_fw_restart(adap, mbox); 7772 } 7773 7774 /** 7775 * t4_fw_initialize - ask FW to initialize the device 7776 * @adap: the adapter 7777 * @mbox: mailbox to use for the FW command 7778 * 7779 * Issues a command to FW to partially initialize the device. This 7780 * performs initialization that generally doesn't depend on user input. 7781 */ 7782 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7783 { 7784 struct fw_initialize_cmd c; 7785 7786 memset(&c, 0, sizeof(c)); 7787 INIT_CMD(c, INITIALIZE, WRITE); 7788 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7789 } 7790 7791 /** 7792 * t4_query_params_rw - query FW or device parameters 7793 * @adap: the adapter 7794 * @mbox: mailbox to use for the FW command 7795 * @pf: the PF 7796 * @vf: the VF 7797 * @nparams: the number of parameters 7798 * @params: the parameter names 7799 * @val: the parameter values 7800 * @rw: Write and read flag 7801 * 7802 * Reads the value of FW or device parameters. Up to 7 parameters can be 7803 * queried at once. 7804 */ 7805 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7806 unsigned int vf, unsigned int nparams, const u32 *params, 7807 u32 *val, int rw) 7808 { 7809 int i, ret; 7810 struct fw_params_cmd c; 7811 __be32 *p = &c.param[0].mnem; 7812 7813 if (nparams > 7) 7814 return -EINVAL; 7815 7816 memset(&c, 0, sizeof(c)); 7817 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7818 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7819 V_FW_PARAMS_CMD_PFN(pf) | 7820 V_FW_PARAMS_CMD_VFN(vf)); 7821 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7822 7823 for (i = 0; i < nparams; i++) { 7824 *p++ = cpu_to_be32(*params++); 7825 if (rw) 7826 *p = cpu_to_be32(*(val + i)); 7827 p++; 7828 } 7829 7830 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7831 if (ret == 0) 7832 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7833 *val++ = be32_to_cpu(*p); 7834 return ret; 7835 } 7836 7837 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7838 unsigned int vf, unsigned int nparams, const u32 *params, 7839 u32 *val) 7840 { 7841 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7842 } 7843 7844 /** 7845 * t4_set_params_timeout - sets FW or device parameters 7846 * @adap: the adapter 7847 * @mbox: mailbox to use for the FW command 7848 * @pf: the PF 7849 * @vf: the VF 7850 * @nparams: the number of parameters 7851 * @params: the parameter names 7852 * @val: the parameter values 7853 * @timeout: the timeout time 7854 * 7855 * Sets the value of FW or device parameters. Up to 7 parameters can be 7856 * specified at once. 7857 */ 7858 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7859 unsigned int pf, unsigned int vf, 7860 unsigned int nparams, const u32 *params, 7861 const u32 *val, int timeout) 7862 { 7863 struct fw_params_cmd c; 7864 __be32 *p = &c.param[0].mnem; 7865 7866 if (nparams > 7) 7867 return -EINVAL; 7868 7869 memset(&c, 0, sizeof(c)); 7870 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7871 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7872 V_FW_PARAMS_CMD_PFN(pf) | 7873 V_FW_PARAMS_CMD_VFN(vf)); 7874 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7875 7876 while (nparams--) { 7877 *p++ = cpu_to_be32(*params++); 7878 *p++ = cpu_to_be32(*val++); 7879 } 7880 7881 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7882 } 7883 7884 /** 7885 * t4_set_params - sets FW or device parameters 7886 * @adap: the adapter 7887 * @mbox: mailbox to use for the FW command 7888 * @pf: the PF 7889 * @vf: the VF 7890 * @nparams: the number of parameters 7891 * @params: the parameter names 7892 * @val: the parameter values 7893 * 7894 * Sets the value of FW or device parameters. Up to 7 parameters can be 7895 * specified at once. 7896 */ 7897 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7898 unsigned int vf, unsigned int nparams, const u32 *params, 7899 const u32 *val) 7900 { 7901 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7902 FW_CMD_MAX_TIMEOUT); 7903 } 7904 7905 /** 7906 * t4_cfg_pfvf - configure PF/VF resource limits 7907 * @adap: the adapter 7908 * @mbox: mailbox to use for the FW command 7909 * @pf: the PF being configured 7910 * @vf: the VF being configured 7911 * @txq: the max number of egress queues 7912 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7913 * @rxqi: the max number of interrupt-capable ingress queues 7914 * @rxq: the max number of interruptless ingress queues 7915 * @tc: the PCI traffic class 7916 * @vi: the max number of virtual interfaces 7917 * @cmask: the channel access rights mask for the PF/VF 7918 * @pmask: the port access rights mask for the PF/VF 7919 * @nexact: the maximum number of exact MPS filters 7920 * @rcaps: read capabilities 7921 * @wxcaps: write/execute capabilities 7922 * 7923 * Configures resource limits and capabilities for a physical or virtual 7924 * function. 7925 */ 7926 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7927 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7928 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7929 unsigned int vi, unsigned int cmask, unsigned int pmask, 7930 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7931 { 7932 struct fw_pfvf_cmd c; 7933 7934 memset(&c, 0, sizeof(c)); 7935 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7936 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7937 V_FW_PFVF_CMD_VFN(vf)); 7938 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7939 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7940 V_FW_PFVF_CMD_NIQ(rxq)); 7941 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7942 V_FW_PFVF_CMD_PMASK(pmask) | 7943 V_FW_PFVF_CMD_NEQ(txq)); 7944 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7945 V_FW_PFVF_CMD_NVI(vi) | 7946 V_FW_PFVF_CMD_NEXACTF(nexact)); 7947 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7948 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7949 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7950 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7951 } 7952 7953 /** 7954 * t4_alloc_vi_func - allocate a virtual interface 7955 * @adap: the adapter 7956 * @mbox: mailbox to use for the FW command 7957 * @port: physical port associated with the VI 7958 * @pf: the PF owning the VI 7959 * @vf: the VF owning the VI 7960 * @nmac: number of MAC addresses needed (1 to 5) 7961 * @mac: the MAC addresses of the VI 7962 * @rss_size: size of RSS table slice associated with this VI 7963 * @portfunc: which Port Application Function MAC Address is desired 7964 * @idstype: Intrusion Detection Type 7965 * 7966 * Allocates a virtual interface for the given physical port. If @mac is 7967 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7968 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7969 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7970 * stored consecutively so the space needed is @nmac * 6 bytes. 7971 * Returns a negative error number or the non-negative VI id. 7972 */ 7973 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7974 unsigned int port, unsigned int pf, unsigned int vf, 7975 unsigned int nmac, u8 *mac, u16 *rss_size, 7976 uint8_t *vfvld, uint16_t *vin, 7977 unsigned int portfunc, unsigned int idstype) 7978 { 7979 int ret; 7980 struct fw_vi_cmd c; 7981 7982 memset(&c, 0, sizeof(c)); 7983 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7984 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7985 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7986 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7987 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7988 V_FW_VI_CMD_FUNC(portfunc)); 7989 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7990 c.nmac = nmac - 1; 7991 if(!rss_size) 7992 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7993 7994 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7995 if (ret) 7996 return ret; 7997 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7998 7999 if (mac) { 8000 memcpy(mac, c.mac, sizeof(c.mac)); 8001 switch (nmac) { 8002 case 5: 8003 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 8004 case 4: 8005 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 8006 case 3: 8007 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 8008 case 2: 8009 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 8010 } 8011 } 8012 if (rss_size) 8013 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 8014 if (vfvld) { 8015 *vfvld = adap->params.viid_smt_extn_support ? 8016 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) : 8017 G_FW_VIID_VIVLD(ret); 8018 } 8019 if (vin) { 8020 *vin = adap->params.viid_smt_extn_support ? 8021 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) : 8022 G_FW_VIID_VIN(ret); 8023 } 8024 8025 return ret; 8026 } 8027 8028 /** 8029 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 8030 * @adap: the adapter 8031 * @mbox: mailbox to use for the FW command 8032 * @port: physical port associated with the VI 8033 * @pf: the PF owning the VI 8034 * @vf: the VF owning the VI 8035 * @nmac: number of MAC addresses needed (1 to 5) 8036 * @mac: the MAC addresses of the VI 8037 * @rss_size: size of RSS table slice associated with this VI 8038 * 8039 * backwards compatible and convieniance routine to allocate a Virtual 8040 * Interface with a Ethernet Port Application Function and Intrustion 8041 * Detection System disabled. 8042 */ 8043 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 8044 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 8045 u16 *rss_size, uint8_t *vfvld, uint16_t *vin) 8046 { 8047 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 8048 vfvld, vin, FW_VI_FUNC_ETH, 0); 8049 } 8050 8051 /** 8052 * t4_free_vi - free a virtual interface 8053 * @adap: the adapter 8054 * @mbox: mailbox to use for the FW command 8055 * @pf: the PF owning the VI 8056 * @vf: the VF owning the VI 8057 * @viid: virtual interface identifiler 8058 * 8059 * Free a previously allocated virtual interface. 8060 */ 8061 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 8062 unsigned int vf, unsigned int viid) 8063 { 8064 struct fw_vi_cmd c; 8065 8066 memset(&c, 0, sizeof(c)); 8067 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 8068 F_FW_CMD_REQUEST | 8069 F_FW_CMD_EXEC | 8070 V_FW_VI_CMD_PFN(pf) | 8071 V_FW_VI_CMD_VFN(vf)); 8072 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 8073 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 8074 8075 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8076 } 8077 8078 /** 8079 * t4_set_rxmode - set Rx properties of a virtual interface 8080 * @adap: the adapter 8081 * @mbox: mailbox to use for the FW command 8082 * @viid: the VI id 8083 * @mtu: the new MTU or -1 8084 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 8085 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 8086 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 8087 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 8088 * @sleep_ok: if true we may sleep while awaiting command completion 8089 * 8090 * Sets Rx properties of a virtual interface. 8091 */ 8092 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 8093 int mtu, int promisc, int all_multi, int bcast, int vlanex, 8094 bool sleep_ok) 8095 { 8096 struct fw_vi_rxmode_cmd c; 8097 8098 /* convert to FW values */ 8099 if (mtu < 0) 8100 mtu = M_FW_VI_RXMODE_CMD_MTU; 8101 if (promisc < 0) 8102 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 8103 if (all_multi < 0) 8104 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 8105 if (bcast < 0) 8106 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 8107 if (vlanex < 0) 8108 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 8109 8110 memset(&c, 0, sizeof(c)); 8111 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 8112 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8113 V_FW_VI_RXMODE_CMD_VIID(viid)); 8114 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 8115 c.mtu_to_vlanexen = 8116 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 8117 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 8118 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 8119 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 8120 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 8121 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8122 } 8123 8124 /** 8125 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support 8126 * @adap: the adapter 8127 * @viid: the VI id 8128 * @mac: the MAC address 8129 * @mask: the mask 8130 * @vni: the VNI id for the tunnel protocol 8131 * @vni_mask: mask for the VNI id 8132 * @dip_hit: to enable DIP match for the MPS entry 8133 * @lookup_type: MAC address for inner (1) or outer (0) header 8134 * @sleep_ok: call is allowed to sleep 8135 * 8136 * Allocates an MPS entry with specified MAC address and VNI value. 8137 * 8138 * Returns a negative error number or the allocated index for this mac. 8139 */ 8140 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 8141 const u8 *addr, const u8 *mask, unsigned int vni, 8142 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 8143 bool sleep_ok) 8144 { 8145 struct fw_vi_mac_cmd c; 8146 struct fw_vi_mac_vni *p = c.u.exact_vni; 8147 int ret = 0; 8148 u32 val; 8149 8150 memset(&c, 0, sizeof(c)); 8151 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8152 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8153 V_FW_VI_MAC_CMD_VIID(viid)); 8154 val = V_FW_CMD_LEN16(1) | 8155 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI); 8156 c.freemacs_to_len16 = cpu_to_be32(val); 8157 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8158 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8159 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8160 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); 8161 8162 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | 8163 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) | 8164 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type)); 8165 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); 8166 8167 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8168 if (ret == 0) 8169 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8170 return ret; 8171 } 8172 8173 /** 8174 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam 8175 * @adap: the adapter 8176 * @viid: the VI id 8177 * @mac: the MAC address 8178 * @mask: the mask 8179 * @idx: index at which to add this entry 8180 * @port_id: the port index 8181 * @lookup_type: MAC address for inner (1) or outer (0) header 8182 * @sleep_ok: call is allowed to sleep 8183 * 8184 * Adds the mac entry at the specified index using raw mac interface. 8185 * 8186 * Returns a negative error number or the allocated index for this mac. 8187 */ 8188 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 8189 const u8 *addr, const u8 *mask, unsigned int idx, 8190 u8 lookup_type, u8 port_id, bool sleep_ok) 8191 { 8192 int ret = 0; 8193 struct fw_vi_mac_cmd c; 8194 struct fw_vi_mac_raw *p = &c.u.raw; 8195 u32 val; 8196 8197 memset(&c, 0, sizeof(c)); 8198 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8199 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8200 V_FW_VI_MAC_CMD_VIID(viid)); 8201 val = V_FW_CMD_LEN16(1) | 8202 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8203 c.freemacs_to_len16 = cpu_to_be32(val); 8204 8205 /* Specify that this is an inner mac address */ 8206 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); 8207 8208 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8209 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8210 V_DATAPORTNUM(port_id)); 8211 /* Lookup mask and port mask */ 8212 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8213 V_DATAPORTNUM(M_DATAPORTNUM)); 8214 8215 /* Copy the address and the mask */ 8216 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8217 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8218 8219 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8220 if (ret == 0) { 8221 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); 8222 if (ret != idx) 8223 ret = -ENOMEM; 8224 } 8225 8226 return ret; 8227 } 8228 8229 /** 8230 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 8231 * @adap: the adapter 8232 * @mbox: mailbox to use for the FW command 8233 * @viid: the VI id 8234 * @free: if true any existing filters for this VI id are first removed 8235 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8236 * @addr: the MAC address(es) 8237 * @idx: where to store the index of each allocated filter 8238 * @hash: pointer to hash address filter bitmap 8239 * @sleep_ok: call is allowed to sleep 8240 * 8241 * Allocates an exact-match filter for each of the supplied addresses and 8242 * sets it to the corresponding address. If @idx is not %NULL it should 8243 * have at least @naddr entries, each of which will be set to the index of 8244 * the filter allocated for the corresponding MAC address. If a filter 8245 * could not be allocated for an address its index is set to 0xffff. 8246 * If @hash is not %NULL addresses that fail to allocate an exact filter 8247 * are hashed and update the hash filter bitmap pointed at by @hash. 8248 * 8249 * Returns a negative error number or the number of filters allocated. 8250 */ 8251 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 8252 unsigned int viid, bool free, unsigned int naddr, 8253 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 8254 { 8255 int offset, ret = 0; 8256 struct fw_vi_mac_cmd c; 8257 unsigned int nfilters = 0; 8258 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8259 unsigned int rem = naddr; 8260 8261 if (naddr > max_naddr) 8262 return -EINVAL; 8263 8264 for (offset = 0; offset < naddr ; /**/) { 8265 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8266 ? rem 8267 : ARRAY_SIZE(c.u.exact)); 8268 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8269 u.exact[fw_naddr]), 16); 8270 struct fw_vi_mac_exact *p; 8271 int i; 8272 8273 memset(&c, 0, sizeof(c)); 8274 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8275 F_FW_CMD_REQUEST | 8276 F_FW_CMD_WRITE | 8277 V_FW_CMD_EXEC(free) | 8278 V_FW_VI_MAC_CMD_VIID(viid)); 8279 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 8280 V_FW_CMD_LEN16(len16)); 8281 8282 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8283 p->valid_to_idx = 8284 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8285 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8286 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8287 } 8288 8289 /* 8290 * It's okay if we run out of space in our MAC address arena. 8291 * Some of the addresses we submit may get stored so we need 8292 * to run through the reply to see what the results were ... 8293 */ 8294 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8295 if (ret && ret != -FW_ENOMEM) 8296 break; 8297 8298 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8299 u16 index = G_FW_VI_MAC_CMD_IDX( 8300 be16_to_cpu(p->valid_to_idx)); 8301 8302 if (idx) 8303 idx[offset+i] = (index >= max_naddr 8304 ? 0xffff 8305 : index); 8306 if (index < max_naddr) 8307 nfilters++; 8308 else if (hash) 8309 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8310 } 8311 8312 free = false; 8313 offset += fw_naddr; 8314 rem -= fw_naddr; 8315 } 8316 8317 if (ret == 0 || ret == -FW_ENOMEM) 8318 ret = nfilters; 8319 return ret; 8320 } 8321 8322 /** 8323 * t4_free_encap_mac_filt - frees MPS entry at given index 8324 * @adap: the adapter 8325 * @viid: the VI id 8326 * @idx: index of MPS entry to be freed 8327 * @sleep_ok: call is allowed to sleep 8328 * 8329 * Frees the MPS entry at supplied index 8330 * 8331 * Returns a negative error number or zero on success 8332 */ 8333 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 8334 int idx, bool sleep_ok) 8335 { 8336 struct fw_vi_mac_exact *p; 8337 struct fw_vi_mac_cmd c; 8338 u8 addr[] = {0,0,0,0,0,0}; 8339 int ret = 0; 8340 u32 exact; 8341 8342 memset(&c, 0, sizeof(c)); 8343 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8344 F_FW_CMD_REQUEST | 8345 F_FW_CMD_WRITE | 8346 V_FW_CMD_EXEC(0) | 8347 V_FW_VI_MAC_CMD_VIID(viid)); 8348 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC); 8349 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8350 exact | 8351 V_FW_CMD_LEN16(1)); 8352 p = c.u.exact; 8353 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8354 V_FW_VI_MAC_CMD_IDX(idx)); 8355 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8356 8357 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8358 return ret; 8359 } 8360 8361 /** 8362 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam 8363 * @adap: the adapter 8364 * @viid: the VI id 8365 * @addr: the MAC address 8366 * @mask: the mask 8367 * @idx: index of the entry in mps tcam 8368 * @lookup_type: MAC address for inner (1) or outer (0) header 8369 * @port_id: the port index 8370 * @sleep_ok: call is allowed to sleep 8371 * 8372 * Removes the mac entry at the specified index using raw mac interface. 8373 * 8374 * Returns a negative error number on failure. 8375 */ 8376 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 8377 const u8 *addr, const u8 *mask, unsigned int idx, 8378 u8 lookup_type, u8 port_id, bool sleep_ok) 8379 { 8380 struct fw_vi_mac_cmd c; 8381 struct fw_vi_mac_raw *p = &c.u.raw; 8382 u32 raw; 8383 8384 memset(&c, 0, sizeof(c)); 8385 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8386 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8387 V_FW_CMD_EXEC(0) | 8388 V_FW_VI_MAC_CMD_VIID(viid)); 8389 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8390 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8391 raw | 8392 V_FW_CMD_LEN16(1)); 8393 8394 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | 8395 FW_VI_MAC_ID_BASED_FREE); 8396 8397 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8398 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8399 V_DATAPORTNUM(port_id)); 8400 /* Lookup mask and port mask */ 8401 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8402 V_DATAPORTNUM(M_DATAPORTNUM)); 8403 8404 /* Copy the address and the mask */ 8405 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8406 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8407 8408 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8409 } 8410 8411 /** 8412 * t4_free_mac_filt - frees exact-match filters of given MAC addresses 8413 * @adap: the adapter 8414 * @mbox: mailbox to use for the FW command 8415 * @viid: the VI id 8416 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8417 * @addr: the MAC address(es) 8418 * @sleep_ok: call is allowed to sleep 8419 * 8420 * Frees the exact-match filter for each of the supplied addresses 8421 * 8422 * Returns a negative error number or the number of filters freed. 8423 */ 8424 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 8425 unsigned int viid, unsigned int naddr, 8426 const u8 **addr, bool sleep_ok) 8427 { 8428 int offset, ret = 0; 8429 struct fw_vi_mac_cmd c; 8430 unsigned int nfilters = 0; 8431 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8432 unsigned int rem = naddr; 8433 8434 if (naddr > max_naddr) 8435 return -EINVAL; 8436 8437 for (offset = 0; offset < (int)naddr ; /**/) { 8438 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8439 ? rem 8440 : ARRAY_SIZE(c.u.exact)); 8441 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8442 u.exact[fw_naddr]), 16); 8443 struct fw_vi_mac_exact *p; 8444 int i; 8445 8446 memset(&c, 0, sizeof(c)); 8447 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8448 F_FW_CMD_REQUEST | 8449 F_FW_CMD_WRITE | 8450 V_FW_CMD_EXEC(0) | 8451 V_FW_VI_MAC_CMD_VIID(viid)); 8452 c.freemacs_to_len16 = 8453 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8454 V_FW_CMD_LEN16(len16)); 8455 8456 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) { 8457 p->valid_to_idx = cpu_to_be16( 8458 F_FW_VI_MAC_CMD_VALID | 8459 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 8460 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8461 } 8462 8463 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8464 if (ret) 8465 break; 8466 8467 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8468 u16 index = G_FW_VI_MAC_CMD_IDX( 8469 be16_to_cpu(p->valid_to_idx)); 8470 8471 if (index < max_naddr) 8472 nfilters++; 8473 } 8474 8475 offset += fw_naddr; 8476 rem -= fw_naddr; 8477 } 8478 8479 if (ret == 0) 8480 ret = nfilters; 8481 return ret; 8482 } 8483 8484 /** 8485 * t4_change_mac - modifies the exact-match filter for a MAC address 8486 * @adap: the adapter 8487 * @mbox: mailbox to use for the FW command 8488 * @viid: the VI id 8489 * @idx: index of existing filter for old value of MAC address, or -1 8490 * @addr: the new MAC address value 8491 * @persist: whether a new MAC allocation should be persistent 8492 * @smt_idx: add MAC to SMT and return its index, or NULL 8493 * 8494 * Modifies an exact-match filter and sets it to the new MAC address if 8495 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8496 * latter case the address is added persistently if @persist is %true. 8497 * 8498 * Note that in general it is not possible to modify the value of a given 8499 * filter so the generic way to modify an address filter is to free the one 8500 * being used by the old address value and allocate a new filter for the 8501 * new address value. 8502 * 8503 * Returns a negative error number or the index of the filter with the new 8504 * MAC value. Note that this index may differ from @idx. 8505 */ 8506 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8507 int idx, const u8 *addr, bool persist, uint16_t *smt_idx) 8508 { 8509 int ret, mode; 8510 struct fw_vi_mac_cmd c; 8511 struct fw_vi_mac_exact *p = c.u.exact; 8512 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8513 8514 if (idx < 0) /* new allocation */ 8515 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8516 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8517 8518 memset(&c, 0, sizeof(c)); 8519 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8520 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8521 V_FW_VI_MAC_CMD_VIID(viid)); 8522 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8523 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8524 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8525 V_FW_VI_MAC_CMD_IDX(idx)); 8526 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8527 8528 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8529 if (ret == 0) { 8530 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8531 if (ret >= max_mac_addr) 8532 ret = -ENOMEM; 8533 if (smt_idx) { 8534 if (adap->params.viid_smt_extn_support) 8535 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 8536 else { 8537 if (chip_id(adap) <= CHELSIO_T5) 8538 *smt_idx = (viid & M_FW_VIID_VIN) << 1; 8539 else 8540 *smt_idx = viid & M_FW_VIID_VIN; 8541 } 8542 } 8543 } 8544 return ret; 8545 } 8546 8547 /** 8548 * t4_set_addr_hash - program the MAC inexact-match hash filter 8549 * @adap: the adapter 8550 * @mbox: mailbox to use for the FW command 8551 * @viid: the VI id 8552 * @ucast: whether the hash filter should also match unicast addresses 8553 * @vec: the value to be written to the hash filter 8554 * @sleep_ok: call is allowed to sleep 8555 * 8556 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8557 */ 8558 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8559 bool ucast, u64 vec, bool sleep_ok) 8560 { 8561 struct fw_vi_mac_cmd c; 8562 u32 val; 8563 8564 memset(&c, 0, sizeof(c)); 8565 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8566 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8567 V_FW_VI_ENABLE_CMD_VIID(viid)); 8568 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8569 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8570 c.freemacs_to_len16 = cpu_to_be32(val); 8571 c.u.hash.hashvec = cpu_to_be64(vec); 8572 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8573 } 8574 8575 /** 8576 * t4_enable_vi_params - enable/disable a virtual interface 8577 * @adap: the adapter 8578 * @mbox: mailbox to use for the FW command 8579 * @viid: the VI id 8580 * @rx_en: 1=enable Rx, 0=disable Rx 8581 * @tx_en: 1=enable Tx, 0=disable Tx 8582 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8583 * 8584 * Enables/disables a virtual interface. Note that setting DCB Enable 8585 * only makes sense when enabling a Virtual Interface ... 8586 */ 8587 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8588 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8589 { 8590 struct fw_vi_enable_cmd c; 8591 8592 memset(&c, 0, sizeof(c)); 8593 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8594 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8595 V_FW_VI_ENABLE_CMD_VIID(viid)); 8596 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8597 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8598 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8599 FW_LEN16(c)); 8600 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8601 } 8602 8603 /** 8604 * t4_enable_vi - enable/disable a virtual interface 8605 * @adap: the adapter 8606 * @mbox: mailbox to use for the FW command 8607 * @viid: the VI id 8608 * @rx_en: 1=enable Rx, 0=disable Rx 8609 * @tx_en: 1=enable Tx, 0=disable Tx 8610 * 8611 * Enables/disables a virtual interface. Note that setting DCB Enable 8612 * only makes sense when enabling a Virtual Interface ... 8613 */ 8614 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8615 bool rx_en, bool tx_en) 8616 { 8617 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8618 } 8619 8620 /** 8621 * t4_identify_port - identify a VI's port by blinking its LED 8622 * @adap: the adapter 8623 * @mbox: mailbox to use for the FW command 8624 * @viid: the VI id 8625 * @nblinks: how many times to blink LED at 2.5 Hz 8626 * 8627 * Identifies a VI's port by blinking its LED. 8628 */ 8629 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8630 unsigned int nblinks) 8631 { 8632 struct fw_vi_enable_cmd c; 8633 8634 memset(&c, 0, sizeof(c)); 8635 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8636 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8637 V_FW_VI_ENABLE_CMD_VIID(viid)); 8638 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8639 c.blinkdur = cpu_to_be16(nblinks); 8640 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8641 } 8642 8643 /** 8644 * t4_iq_stop - stop an ingress queue and its FLs 8645 * @adap: the adapter 8646 * @mbox: mailbox to use for the FW command 8647 * @pf: the PF owning the queues 8648 * @vf: the VF owning the queues 8649 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8650 * @iqid: ingress queue id 8651 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8652 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8653 * 8654 * Stops an ingress queue and its associated FLs, if any. This causes 8655 * any current or future data/messages destined for these queues to be 8656 * tossed. 8657 */ 8658 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8659 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8660 unsigned int fl0id, unsigned int fl1id) 8661 { 8662 struct fw_iq_cmd c; 8663 8664 memset(&c, 0, sizeof(c)); 8665 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8666 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8667 V_FW_IQ_CMD_VFN(vf)); 8668 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8669 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8670 c.iqid = cpu_to_be16(iqid); 8671 c.fl0id = cpu_to_be16(fl0id); 8672 c.fl1id = cpu_to_be16(fl1id); 8673 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8674 } 8675 8676 /** 8677 * t4_iq_free - free an ingress queue and its FLs 8678 * @adap: the adapter 8679 * @mbox: mailbox to use for the FW command 8680 * @pf: the PF owning the queues 8681 * @vf: the VF owning the queues 8682 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8683 * @iqid: ingress queue id 8684 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8685 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8686 * 8687 * Frees an ingress queue and its associated FLs, if any. 8688 */ 8689 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8690 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8691 unsigned int fl0id, unsigned int fl1id) 8692 { 8693 struct fw_iq_cmd c; 8694 8695 memset(&c, 0, sizeof(c)); 8696 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8697 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8698 V_FW_IQ_CMD_VFN(vf)); 8699 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8700 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8701 c.iqid = cpu_to_be16(iqid); 8702 c.fl0id = cpu_to_be16(fl0id); 8703 c.fl1id = cpu_to_be16(fl1id); 8704 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8705 } 8706 8707 /** 8708 * t4_eth_eq_stop - stop an Ethernet egress queue 8709 * @adap: the adapter 8710 * @mbox: mailbox to use for the FW command 8711 * @pf: the PF owning the queues 8712 * @vf: the VF owning the queues 8713 * @eqid: egress queue id 8714 * 8715 * Stops an Ethernet egress queue. The queue can be reinitialized or 8716 * freed but is not otherwise functional after this call. 8717 */ 8718 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8719 unsigned int vf, unsigned int eqid) 8720 { 8721 struct fw_eq_eth_cmd c; 8722 8723 memset(&c, 0, sizeof(c)); 8724 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8725 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8726 V_FW_EQ_ETH_CMD_PFN(pf) | 8727 V_FW_EQ_ETH_CMD_VFN(vf)); 8728 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c)); 8729 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8730 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8731 } 8732 8733 /** 8734 * t4_eth_eq_free - free an Ethernet egress queue 8735 * @adap: the adapter 8736 * @mbox: mailbox to use for the FW command 8737 * @pf: the PF owning the queue 8738 * @vf: the VF owning the queue 8739 * @eqid: egress queue id 8740 * 8741 * Frees an Ethernet egress queue. 8742 */ 8743 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8744 unsigned int vf, unsigned int eqid) 8745 { 8746 struct fw_eq_eth_cmd c; 8747 8748 memset(&c, 0, sizeof(c)); 8749 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8750 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8751 V_FW_EQ_ETH_CMD_PFN(pf) | 8752 V_FW_EQ_ETH_CMD_VFN(vf)); 8753 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8754 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8755 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8756 } 8757 8758 /** 8759 * t4_ctrl_eq_free - free a control egress queue 8760 * @adap: the adapter 8761 * @mbox: mailbox to use for the FW command 8762 * @pf: the PF owning the queue 8763 * @vf: the VF owning the queue 8764 * @eqid: egress queue id 8765 * 8766 * Frees a control egress queue. 8767 */ 8768 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8769 unsigned int vf, unsigned int eqid) 8770 { 8771 struct fw_eq_ctrl_cmd c; 8772 8773 memset(&c, 0, sizeof(c)); 8774 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8775 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8776 V_FW_EQ_CTRL_CMD_PFN(pf) | 8777 V_FW_EQ_CTRL_CMD_VFN(vf)); 8778 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8779 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8780 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8781 } 8782 8783 /** 8784 * t4_ofld_eq_free - free an offload egress queue 8785 * @adap: the adapter 8786 * @mbox: mailbox to use for the FW command 8787 * @pf: the PF owning the queue 8788 * @vf: the VF owning the queue 8789 * @eqid: egress queue id 8790 * 8791 * Frees a control egress queue. 8792 */ 8793 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8794 unsigned int vf, unsigned int eqid) 8795 { 8796 struct fw_eq_ofld_cmd c; 8797 8798 memset(&c, 0, sizeof(c)); 8799 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8800 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8801 V_FW_EQ_OFLD_CMD_PFN(pf) | 8802 V_FW_EQ_OFLD_CMD_VFN(vf)); 8803 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8804 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8805 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8806 } 8807 8808 /** 8809 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8810 * @link_down_rc: Link Down Reason Code 8811 * 8812 * Returns a string representation of the Link Down Reason Code. 8813 */ 8814 const char *t4_link_down_rc_str(unsigned char link_down_rc) 8815 { 8816 static const char *reason[] = { 8817 "Link Down", 8818 "Remote Fault", 8819 "Auto-negotiation Failure", 8820 "Reserved3", 8821 "Insufficient Airflow", 8822 "Unable To Determine Reason", 8823 "No RX Signal Detected", 8824 "Reserved7", 8825 }; 8826 8827 if (link_down_rc >= ARRAY_SIZE(reason)) 8828 return "Bad Reason Code"; 8829 8830 return reason[link_down_rc]; 8831 } 8832 8833 /* 8834 * Return the highest speed set in the port capabilities, in Mb/s. 8835 */ 8836 unsigned int fwcap_to_speed(uint32_t caps) 8837 { 8838 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8839 do { \ 8840 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8841 return __speed; \ 8842 } while (0) 8843 8844 TEST_SPEED_RETURN(400G, 400000); 8845 TEST_SPEED_RETURN(200G, 200000); 8846 TEST_SPEED_RETURN(100G, 100000); 8847 TEST_SPEED_RETURN(50G, 50000); 8848 TEST_SPEED_RETURN(40G, 40000); 8849 TEST_SPEED_RETURN(25G, 25000); 8850 TEST_SPEED_RETURN(10G, 10000); 8851 TEST_SPEED_RETURN(1G, 1000); 8852 TEST_SPEED_RETURN(100M, 100); 8853 8854 #undef TEST_SPEED_RETURN 8855 8856 return 0; 8857 } 8858 8859 /* 8860 * Return the port capabilities bit for the given speed, which is in Mb/s. 8861 */ 8862 uint32_t speed_to_fwcap(unsigned int speed) 8863 { 8864 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8865 do { \ 8866 if (speed == __speed) \ 8867 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8868 } while (0) 8869 8870 TEST_SPEED_RETURN(400G, 400000); 8871 TEST_SPEED_RETURN(200G, 200000); 8872 TEST_SPEED_RETURN(100G, 100000); 8873 TEST_SPEED_RETURN(50G, 50000); 8874 TEST_SPEED_RETURN(40G, 40000); 8875 TEST_SPEED_RETURN(25G, 25000); 8876 TEST_SPEED_RETURN(10G, 10000); 8877 TEST_SPEED_RETURN(1G, 1000); 8878 TEST_SPEED_RETURN(100M, 100); 8879 8880 #undef TEST_SPEED_RETURN 8881 8882 return 0; 8883 } 8884 8885 /* 8886 * Return the port capabilities bit for the highest speed in the capabilities. 8887 */ 8888 uint32_t fwcap_top_speed(uint32_t caps) 8889 { 8890 #define TEST_SPEED_RETURN(__caps_speed) \ 8891 do { \ 8892 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8893 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8894 } while (0) 8895 8896 TEST_SPEED_RETURN(400G); 8897 TEST_SPEED_RETURN(200G); 8898 TEST_SPEED_RETURN(100G); 8899 TEST_SPEED_RETURN(50G); 8900 TEST_SPEED_RETURN(40G); 8901 TEST_SPEED_RETURN(25G); 8902 TEST_SPEED_RETURN(10G); 8903 TEST_SPEED_RETURN(1G); 8904 TEST_SPEED_RETURN(100M); 8905 8906 #undef TEST_SPEED_RETURN 8907 8908 return 0; 8909 } 8910 8911 /** 8912 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8913 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8914 * 8915 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8916 * 32-bit Port Capabilities value. 8917 */ 8918 static uint32_t lstatus_to_fwcap(u32 lstatus) 8919 { 8920 uint32_t linkattr = 0; 8921 8922 /* 8923 * Unfortunately the format of the Link Status in the old 8924 * 16-bit Port Information message isn't the same as the 8925 * 16-bit Port Capabilities bitfield used everywhere else ... 8926 */ 8927 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8928 linkattr |= FW_PORT_CAP32_FC_RX; 8929 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8930 linkattr |= FW_PORT_CAP32_FC_TX; 8931 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8932 linkattr |= FW_PORT_CAP32_SPEED_100M; 8933 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8934 linkattr |= FW_PORT_CAP32_SPEED_1G; 8935 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8936 linkattr |= FW_PORT_CAP32_SPEED_10G; 8937 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8938 linkattr |= FW_PORT_CAP32_SPEED_25G; 8939 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8940 linkattr |= FW_PORT_CAP32_SPEED_40G; 8941 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8942 linkattr |= FW_PORT_CAP32_SPEED_100G; 8943 8944 return linkattr; 8945 } 8946 8947 /* 8948 * Updates all fields owned by the common code in port_info and link_config 8949 * based on information provided by the firmware. Does not touch any 8950 * requested_* field. 8951 */ 8952 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8953 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8954 { 8955 struct link_config old_lc, *lc = &pi->link_cfg; 8956 unsigned char fc; 8957 u32 stat, linkattr; 8958 int old_ptype, old_mtype; 8959 8960 old_ptype = pi->port_type; 8961 old_mtype = pi->mod_type; 8962 old_lc = *lc; 8963 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8964 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8965 8966 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8967 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8968 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8969 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8970 8971 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8972 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8973 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8974 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8975 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8976 8977 linkattr = lstatus_to_fwcap(stat); 8978 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8979 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8980 8981 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8982 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8983 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8984 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8985 8986 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); 8987 lc->acaps = be32_to_cpu(p->u.info32.acaps32); 8988 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); 8989 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8990 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8991 8992 linkattr = be32_to_cpu(p->u.info32.linkattr32); 8993 } else { 8994 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 8995 return; 8996 } 8997 8998 lc->speed = fwcap_to_speed(linkattr); 8999 lc->fec = fwcap_to_fec(linkattr, true); 9000 9001 fc = 0; 9002 if (linkattr & FW_PORT_CAP32_FC_RX) 9003 fc |= PAUSE_RX; 9004 if (linkattr & FW_PORT_CAP32_FC_TX) 9005 fc |= PAUSE_TX; 9006 lc->fc = fc; 9007 9008 if (mod_changed != NULL) 9009 *mod_changed = false; 9010 if (link_changed != NULL) 9011 *link_changed = false; 9012 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 9013 old_lc.pcaps != lc->pcaps) { 9014 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) 9015 lc->fec_hint = fwcap_to_fec(lc->acaps, true); 9016 if (mod_changed != NULL) 9017 *mod_changed = true; 9018 } 9019 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 9020 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 9021 if (link_changed != NULL) 9022 *link_changed = true; 9023 } 9024 } 9025 9026 /** 9027 * t4_update_port_info - retrieve and update port information if changed 9028 * @pi: the port_info 9029 * 9030 * We issue a Get Port Information Command to the Firmware and, if 9031 * successful, we check to see if anything is different from what we 9032 * last recorded and update things accordingly. 9033 */ 9034 int t4_update_port_info(struct port_info *pi) 9035 { 9036 struct adapter *sc = pi->adapter; 9037 struct fw_port_cmd cmd; 9038 enum fw_port_action action; 9039 int ret; 9040 9041 memset(&cmd, 0, sizeof(cmd)); 9042 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 9043 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9044 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 9045 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 9046 FW_PORT_ACTION_GET_PORT_INFO; 9047 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 9048 FW_LEN16(cmd)); 9049 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 9050 if (ret) 9051 return ret; 9052 9053 handle_port_info(pi, &cmd, action, NULL, NULL); 9054 return 0; 9055 } 9056 9057 /** 9058 * t4_handle_fw_rpl - process a FW reply message 9059 * @adap: the adapter 9060 * @rpl: start of the FW message 9061 * 9062 * Processes a FW message, such as link state change messages. 9063 */ 9064 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 9065 { 9066 u8 opcode = *(const u8 *)rpl; 9067 const struct fw_port_cmd *p = (const void *)rpl; 9068 enum fw_port_action action = 9069 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 9070 bool mod_changed, link_changed; 9071 9072 if (opcode == FW_PORT_CMD && 9073 (action == FW_PORT_ACTION_GET_PORT_INFO || 9074 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 9075 /* link/module state change message */ 9076 int i; 9077 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 9078 struct port_info *pi = NULL; 9079 struct link_config *lc; 9080 9081 for_each_port(adap, i) { 9082 pi = adap2pinfo(adap, i); 9083 if (pi->tx_chan == chan) 9084 break; 9085 } 9086 9087 lc = &pi->link_cfg; 9088 PORT_LOCK(pi); 9089 handle_port_info(pi, p, action, &mod_changed, &link_changed); 9090 PORT_UNLOCK(pi); 9091 if (mod_changed) 9092 t4_os_portmod_changed(pi); 9093 if (link_changed) { 9094 PORT_LOCK(pi); 9095 t4_os_link_changed(pi); 9096 PORT_UNLOCK(pi); 9097 } 9098 } else { 9099 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 9100 return -EINVAL; 9101 } 9102 return 0; 9103 } 9104 9105 /** 9106 * get_pci_mode - determine a card's PCI mode 9107 * @adapter: the adapter 9108 * @p: where to store the PCI settings 9109 * 9110 * Determines a card's PCI mode and associated parameters, such as speed 9111 * and width. 9112 */ 9113 static void get_pci_mode(struct adapter *adapter, 9114 struct pci_params *p) 9115 { 9116 u16 val; 9117 u32 pcie_cap; 9118 9119 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9120 if (pcie_cap) { 9121 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 9122 p->speed = val & PCI_EXP_LNKSTA_CLS; 9123 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 9124 } 9125 } 9126 9127 struct flash_desc { 9128 u32 vendor_and_model_id; 9129 u32 size_mb; 9130 }; 9131 9132 int t4_get_flash_params(struct adapter *adapter) 9133 { 9134 /* 9135 * Table for non-standard supported Flash parts. Note, all Flash 9136 * parts must have 64KB sectors. 9137 */ 9138 static struct flash_desc supported_flash[] = { 9139 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 9140 }; 9141 9142 int ret; 9143 u32 flashid = 0; 9144 unsigned int part, manufacturer; 9145 unsigned int density, size = 0; 9146 9147 9148 /* 9149 * Issue a Read ID Command to the Flash part. We decode supported 9150 * Flash parts and their sizes from this. There's a newer Query 9151 * Command which can retrieve detailed geometry information but many 9152 * Flash parts don't support it. 9153 */ 9154 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 9155 if (!ret) 9156 ret = sf1_read(adapter, 3, 0, 1, &flashid); 9157 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 9158 if (ret < 0) 9159 return ret; 9160 9161 /* 9162 * Check to see if it's one of our non-standard supported Flash parts. 9163 */ 9164 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 9165 if (supported_flash[part].vendor_and_model_id == flashid) { 9166 adapter->params.sf_size = 9167 supported_flash[part].size_mb; 9168 adapter->params.sf_nsec = 9169 adapter->params.sf_size / SF_SEC_SIZE; 9170 goto found; 9171 } 9172 9173 /* 9174 * Decode Flash part size. The code below looks repetative with 9175 * common encodings, but that's not guaranteed in the JEDEC 9176 * specification for the Read JADEC ID command. The only thing that 9177 * we're guaranteed by the JADEC specification is where the 9178 * Manufacturer ID is in the returned result. After that each 9179 * Manufacturer ~could~ encode things completely differently. 9180 * Note, all Flash parts must have 64KB sectors. 9181 */ 9182 manufacturer = flashid & 0xff; 9183 switch (manufacturer) { 9184 case 0x20: /* Micron/Numonix */ 9185 /* 9186 * This Density -> Size decoding table is taken from Micron 9187 * Data Sheets. 9188 */ 9189 density = (flashid >> 16) & 0xff; 9190 switch (density) { 9191 case 0x14: size = 1 << 20; break; /* 1MB */ 9192 case 0x15: size = 1 << 21; break; /* 2MB */ 9193 case 0x16: size = 1 << 22; break; /* 4MB */ 9194 case 0x17: size = 1 << 23; break; /* 8MB */ 9195 case 0x18: size = 1 << 24; break; /* 16MB */ 9196 case 0x19: size = 1 << 25; break; /* 32MB */ 9197 case 0x20: size = 1 << 26; break; /* 64MB */ 9198 case 0x21: size = 1 << 27; break; /* 128MB */ 9199 case 0x22: size = 1 << 28; break; /* 256MB */ 9200 } 9201 break; 9202 9203 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 9204 /* 9205 * This Density -> Size decoding table is taken from ISSI 9206 * Data Sheets. 9207 */ 9208 density = (flashid >> 16) & 0xff; 9209 switch (density) { 9210 case 0x16: size = 1 << 25; break; /* 32MB */ 9211 case 0x17: size = 1 << 26; break; /* 64MB */ 9212 } 9213 break; 9214 9215 case 0xc2: /* Macronix */ 9216 /* 9217 * This Density -> Size decoding table is taken from Macronix 9218 * Data Sheets. 9219 */ 9220 density = (flashid >> 16) & 0xff; 9221 switch (density) { 9222 case 0x17: size = 1 << 23; break; /* 8MB */ 9223 case 0x18: size = 1 << 24; break; /* 16MB */ 9224 } 9225 break; 9226 9227 case 0xef: /* Winbond */ 9228 /* 9229 * This Density -> Size decoding table is taken from Winbond 9230 * Data Sheets. 9231 */ 9232 density = (flashid >> 16) & 0xff; 9233 switch (density) { 9234 case 0x17: size = 1 << 23; break; /* 8MB */ 9235 case 0x18: size = 1 << 24; break; /* 16MB */ 9236 } 9237 break; 9238 } 9239 9240 /* If we didn't recognize the FLASH part, that's no real issue: the 9241 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 9242 * use a FLASH part which is at least 4MB in size and has 64KB 9243 * sectors. The unrecognized FLASH part is likely to be much larger 9244 * than 4MB, but that's all we really need. 9245 */ 9246 if (size == 0) { 9247 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 9248 size = 1 << 22; 9249 } 9250 9251 /* 9252 * Store decoded Flash size and fall through into vetting code. 9253 */ 9254 adapter->params.sf_size = size; 9255 adapter->params.sf_nsec = size / SF_SEC_SIZE; 9256 9257 found: 9258 /* 9259 * We should ~probably~ reject adapters with FLASHes which are too 9260 * small but we have some legacy FPGAs with small FLASHes that we'd 9261 * still like to use. So instead we emit a scary message ... 9262 */ 9263 if (adapter->params.sf_size < FLASH_MIN_SIZE) 9264 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 9265 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 9266 9267 return 0; 9268 } 9269 9270 static void set_pcie_completion_timeout(struct adapter *adapter, 9271 u8 range) 9272 { 9273 u16 val; 9274 u32 pcie_cap; 9275 9276 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9277 if (pcie_cap) { 9278 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 9279 val &= 0xfff0; 9280 val |= range ; 9281 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 9282 } 9283 } 9284 9285 const struct chip_params *t4_get_chip_params(int chipid) 9286 { 9287 static const struct chip_params chip_params[] = { 9288 { 9289 /* T4 */ 9290 .nchan = NCHAN, 9291 .pm_stats_cnt = PM_NSTATS, 9292 .cng_ch_bits_log = 2, 9293 .nsched_cls = 15, 9294 .cim_num_obq = CIM_NUM_OBQ, 9295 .filter_opt_len = FILTER_OPT_LEN, 9296 .mps_rplc_size = 128, 9297 .vfcount = 128, 9298 .sge_fl_db = F_DBPRIO, 9299 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 9300 .rss_nentries = RSS_NENTRIES, 9301 }, 9302 { 9303 /* T5 */ 9304 .nchan = NCHAN, 9305 .pm_stats_cnt = PM_NSTATS, 9306 .cng_ch_bits_log = 2, 9307 .nsched_cls = 16, 9308 .cim_num_obq = CIM_NUM_OBQ_T5, 9309 .filter_opt_len = T5_FILTER_OPT_LEN, 9310 .mps_rplc_size = 128, 9311 .vfcount = 128, 9312 .sge_fl_db = F_DBPRIO | F_DBTYPE, 9313 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9314 .rss_nentries = RSS_NENTRIES, 9315 }, 9316 { 9317 /* T6 */ 9318 .nchan = T6_NCHAN, 9319 .pm_stats_cnt = T6_PM_NSTATS, 9320 .cng_ch_bits_log = 3, 9321 .nsched_cls = 16, 9322 .cim_num_obq = CIM_NUM_OBQ_T5, 9323 .filter_opt_len = T5_FILTER_OPT_LEN, 9324 .mps_rplc_size = 256, 9325 .vfcount = 256, 9326 .sge_fl_db = 0, 9327 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9328 .rss_nentries = T6_RSS_NENTRIES, 9329 }, 9330 }; 9331 9332 chipid -= CHELSIO_T4; 9333 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 9334 return NULL; 9335 9336 return &chip_params[chipid]; 9337 } 9338 9339 /** 9340 * t4_prep_adapter - prepare SW and HW for operation 9341 * @adapter: the adapter 9342 * @buf: temporary space of at least VPD_LEN size provided by the caller. 9343 * 9344 * Initialize adapter SW state for the various HW modules, set initial 9345 * values for some adapter tunables, take PHYs out of reset, and 9346 * initialize the MDIO interface. 9347 */ 9348 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 9349 { 9350 int ret; 9351 uint16_t device_id; 9352 uint32_t pl_rev; 9353 9354 get_pci_mode(adapter, &adapter->params.pci); 9355 9356 pl_rev = t4_read_reg(adapter, A_PL_REV); 9357 adapter->params.chipid = G_CHIPID(pl_rev); 9358 adapter->params.rev = G_REV(pl_rev); 9359 if (adapter->params.chipid == 0) { 9360 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 9361 adapter->params.chipid = CHELSIO_T4; 9362 9363 /* T4A1 chip is not supported */ 9364 if (adapter->params.rev == 1) { 9365 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 9366 return -EINVAL; 9367 } 9368 } 9369 9370 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 9371 if (adapter->chip_params == NULL) 9372 return -EINVAL; 9373 9374 adapter->params.pci.vpd_cap_addr = 9375 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 9376 9377 ret = t4_get_flash_params(adapter); 9378 if (ret < 0) 9379 return ret; 9380 9381 /* Cards with real ASICs have the chipid in the PCIe device id */ 9382 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 9383 if (device_id >> 12 == chip_id(adapter)) 9384 adapter->params.cim_la_size = CIMLA_SIZE; 9385 else { 9386 /* FPGA */ 9387 adapter->params.fpga = 1; 9388 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 9389 } 9390 9391 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 9392 if (ret < 0) 9393 return ret; 9394 9395 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 9396 9397 /* 9398 * Default port and clock for debugging in case we can't reach FW. 9399 */ 9400 adapter->params.nports = 1; 9401 adapter->params.portvec = 1; 9402 adapter->params.vpd.cclk = 50000; 9403 9404 /* Set pci completion timeout value to 4 seconds. */ 9405 set_pcie_completion_timeout(adapter, 0xd); 9406 return 0; 9407 } 9408 9409 /** 9410 * t4_shutdown_adapter - shut down adapter, host & wire 9411 * @adapter: the adapter 9412 * 9413 * Perform an emergency shutdown of the adapter and stop it from 9414 * continuing any further communication on the ports or DMA to the 9415 * host. This is typically used when the adapter and/or firmware 9416 * have crashed and we want to prevent any further accidental 9417 * communication with the rest of the world. This will also force 9418 * the port Link Status to go down -- if register writes work -- 9419 * which should help our peers figure out that we're down. 9420 */ 9421 int t4_shutdown_adapter(struct adapter *adapter) 9422 { 9423 int port; 9424 const bool bt = adapter->bt_map != 0; 9425 9426 t4_intr_disable(adapter); 9427 if (bt) 9428 t4_write_reg(adapter, A_DBG_GPIO_EN, 0xffff0000); 9429 for_each_port(adapter, port) { 9430 u32 a_port_cfg = is_t4(adapter) ? 9431 PORT_REG(port, A_XGMAC_PORT_CFG) : 9432 T5_PORT_REG(port, A_MAC_PORT_CFG); 9433 9434 t4_write_reg(adapter, a_port_cfg, 9435 t4_read_reg(adapter, a_port_cfg) 9436 & ~V_SIGNAL_DET(1)); 9437 if (!bt) { 9438 u32 hss_cfg0 = is_t4(adapter) ? 9439 PORT_REG(port, A_XGMAC_PORT_HSS_CFG0) : 9440 T5_PORT_REG(port, A_MAC_PORT_HSS_CFG0); 9441 t4_set_reg_field(adapter, hss_cfg0, F_HSSPDWNPLLB | 9442 F_HSSPDWNPLLA | F_HSSPLLBYPB | F_HSSPLLBYPA, 9443 F_HSSPDWNPLLB | F_HSSPDWNPLLA | F_HSSPLLBYPB | 9444 F_HSSPLLBYPA); 9445 } 9446 } 9447 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 9448 9449 return 0; 9450 } 9451 9452 /** 9453 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 9454 * @adapter: the adapter 9455 * @qid: the Queue ID 9456 * @qtype: the Ingress or Egress type for @qid 9457 * @user: true if this request is for a user mode queue 9458 * @pbar2_qoffset: BAR2 Queue Offset 9459 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 9460 * 9461 * Returns the BAR2 SGE Queue Registers information associated with the 9462 * indicated Absolute Queue ID. These are passed back in return value 9463 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 9464 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 9465 * 9466 * This may return an error which indicates that BAR2 SGE Queue 9467 * registers aren't available. If an error is not returned, then the 9468 * following values are returned: 9469 * 9470 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 9471 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 9472 * 9473 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 9474 * require the "Inferred Queue ID" ability may be used. E.g. the 9475 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 9476 * then these "Inferred Queue ID" register may not be used. 9477 */ 9478 int t4_bar2_sge_qregs(struct adapter *adapter, 9479 unsigned int qid, 9480 enum t4_bar2_qtype qtype, 9481 int user, 9482 u64 *pbar2_qoffset, 9483 unsigned int *pbar2_qid) 9484 { 9485 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 9486 u64 bar2_page_offset, bar2_qoffset; 9487 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 9488 9489 /* T4 doesn't support BAR2 SGE Queue registers for kernel 9490 * mode queues. 9491 */ 9492 if (!user && is_t4(adapter)) 9493 return -EINVAL; 9494 9495 /* Get our SGE Page Size parameters. 9496 */ 9497 page_shift = adapter->params.sge.page_shift; 9498 page_size = 1 << page_shift; 9499 9500 /* Get the right Queues per Page parameters for our Queue. 9501 */ 9502 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 9503 ? adapter->params.sge.eq_s_qpp 9504 : adapter->params.sge.iq_s_qpp); 9505 qpp_mask = (1 << qpp_shift) - 1; 9506 9507 /* Calculate the basics of the BAR2 SGE Queue register area: 9508 * o The BAR2 page the Queue registers will be in. 9509 * o The BAR2 Queue ID. 9510 * o The BAR2 Queue ID Offset into the BAR2 page. 9511 */ 9512 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 9513 bar2_qid = qid & qpp_mask; 9514 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 9515 9516 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9517 * hardware will infer the Absolute Queue ID simply from the writes to 9518 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9519 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9520 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9521 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9522 * from the BAR2 Page and BAR2 Queue ID. 9523 * 9524 * One important censequence of this is that some BAR2 SGE registers 9525 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9526 * there. But other registers synthesize the SGE Queue ID purely 9527 * from the writes to the registers -- the Write Combined Doorbell 9528 * Buffer is a good example. These BAR2 SGE Registers are only 9529 * available for those BAR2 SGE Register areas where the SGE Absolute 9530 * Queue ID can be inferred from simple writes. 9531 */ 9532 bar2_qoffset = bar2_page_offset; 9533 bar2_qinferred = (bar2_qid_offset < page_size); 9534 if (bar2_qinferred) { 9535 bar2_qoffset += bar2_qid_offset; 9536 bar2_qid = 0; 9537 } 9538 9539 *pbar2_qoffset = bar2_qoffset; 9540 *pbar2_qid = bar2_qid; 9541 return 0; 9542 } 9543 9544 /** 9545 * t4_init_devlog_params - initialize adapter->params.devlog 9546 * @adap: the adapter 9547 * @fw_attach: whether we can talk to the firmware 9548 * 9549 * Initialize various fields of the adapter's Firmware Device Log 9550 * Parameters structure. 9551 */ 9552 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9553 { 9554 struct devlog_params *dparams = &adap->params.devlog; 9555 u32 pf_dparams; 9556 unsigned int devlog_meminfo; 9557 struct fw_devlog_cmd devlog_cmd; 9558 int ret; 9559 9560 /* If we're dealing with newer firmware, the Device Log Paramerters 9561 * are stored in a designated register which allows us to access the 9562 * Device Log even if we can't talk to the firmware. 9563 */ 9564 pf_dparams = 9565 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9566 if (pf_dparams) { 9567 unsigned int nentries, nentries128; 9568 9569 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9570 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9571 9572 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9573 nentries = (nentries128 + 1) * 128; 9574 dparams->size = nentries * sizeof(struct fw_devlog_e); 9575 9576 return 0; 9577 } 9578 9579 /* 9580 * For any failing returns ... 9581 */ 9582 memset(dparams, 0, sizeof *dparams); 9583 9584 /* 9585 * If we can't talk to the firmware, there's really nothing we can do 9586 * at this point. 9587 */ 9588 if (!fw_attach) 9589 return -ENXIO; 9590 9591 /* Otherwise, ask the firmware for it's Device Log Parameters. 9592 */ 9593 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9594 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9595 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9596 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9597 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9598 &devlog_cmd); 9599 if (ret) 9600 return ret; 9601 9602 devlog_meminfo = 9603 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9604 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9605 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9606 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9607 9608 return 0; 9609 } 9610 9611 /** 9612 * t4_init_sge_params - initialize adap->params.sge 9613 * @adapter: the adapter 9614 * 9615 * Initialize various fields of the adapter's SGE Parameters structure. 9616 */ 9617 int t4_init_sge_params(struct adapter *adapter) 9618 { 9619 u32 r; 9620 struct sge_params *sp = &adapter->params.sge; 9621 unsigned i, tscale = 1; 9622 9623 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9624 sp->counter_val[0] = G_THRESHOLD_0(r); 9625 sp->counter_val[1] = G_THRESHOLD_1(r); 9626 sp->counter_val[2] = G_THRESHOLD_2(r); 9627 sp->counter_val[3] = G_THRESHOLD_3(r); 9628 9629 if (chip_id(adapter) >= CHELSIO_T6) { 9630 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9631 tscale = G_TSCALE(r); 9632 if (tscale == 0) 9633 tscale = 1; 9634 else 9635 tscale += 2; 9636 } 9637 9638 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9639 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9640 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9641 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9642 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9643 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9644 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9645 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9646 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9647 9648 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9649 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9650 if (is_t4(adapter)) 9651 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9652 else if (is_t5(adapter)) 9653 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9654 else 9655 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9656 9657 /* egress queues: log2 of # of doorbells per BAR2 page */ 9658 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9659 r >>= S_QUEUESPERPAGEPF0 + 9660 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9661 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9662 9663 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9664 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9665 r >>= S_QUEUESPERPAGEPF0 + 9666 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9667 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9668 9669 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9670 r >>= S_HOSTPAGESIZEPF0 + 9671 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9672 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9673 9674 r = t4_read_reg(adapter, A_SGE_CONTROL); 9675 sp->sge_control = r; 9676 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9677 sp->fl_pktshift = G_PKTSHIFT(r); 9678 if (chip_id(adapter) <= CHELSIO_T5) { 9679 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9680 X_INGPADBOUNDARY_SHIFT); 9681 } else { 9682 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9683 X_T6_INGPADBOUNDARY_SHIFT); 9684 } 9685 if (is_t4(adapter)) 9686 sp->pack_boundary = sp->pad_boundary; 9687 else { 9688 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9689 if (G_INGPACKBOUNDARY(r) == 0) 9690 sp->pack_boundary = 16; 9691 else 9692 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9693 } 9694 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9695 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9696 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9697 9698 return 0; 9699 } 9700 9701 /* Convert the LE's hardware hash mask to a shorter filter mask. */ 9702 static inline uint16_t 9703 hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode) 9704 { 9705 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 9706 int i; 9707 uint16_t filter_mask; 9708 uint64_t mask; /* field mask */ 9709 9710 filter_mask = 0; 9711 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 9712 if ((filter_mode & (1 << i)) == 0) 9713 continue; 9714 mask = (1 << width[i]) - 1; 9715 if ((hashmask & mask) == mask) 9716 filter_mask |= 1 << i; 9717 hashmask >>= width[i]; 9718 } 9719 9720 return (filter_mask); 9721 } 9722 9723 /* 9724 * Read and cache the adapter's compressed filter mode and ingress config. 9725 */ 9726 static void 9727 read_filter_mode_and_ingress_config(struct adapter *adap) 9728 { 9729 int rc; 9730 uint32_t v, param[2], val[2]; 9731 struct tp_params *tpp = &adap->params.tp; 9732 uint64_t hash_mask; 9733 9734 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9735 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9736 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 9737 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9738 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9739 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 9740 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); 9741 if (rc == 0) { 9742 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); 9743 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); 9744 tpp->vnic_mode = val[1]; 9745 } else { 9746 /* 9747 * Old firmware. Read filter mode/mask and ingress config 9748 * straight from the hardware. 9749 */ 9750 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true); 9751 tpp->filter_mode = v & 0xffff; 9752 9753 hash_mask = 0; 9754 if (chip_id(adap) > CHELSIO_T4) { 9755 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9756 hash_mask = v; 9757 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9758 hash_mask |= (u64)v << 32; 9759 } 9760 tpp->filter_mask = hashmask_to_filtermask(hash_mask, 9761 tpp->filter_mode); 9762 9763 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true); 9764 if (v & F_VNIC) 9765 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; 9766 else 9767 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; 9768 } 9769 9770 /* 9771 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9772 * shift positions of several elements of the Compressed Filter Tuple 9773 * for this adapter which we need frequently ... 9774 */ 9775 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9776 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9777 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9778 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9779 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9780 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9781 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9782 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9783 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9784 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9785 } 9786 9787 /** 9788 * t4_init_tp_params - initialize adap->params.tp 9789 * @adap: the adapter 9790 * 9791 * Initialize various fields of the adapter's TP Parameters structure. 9792 */ 9793 int t4_init_tp_params(struct adapter *adap) 9794 { 9795 int chan; 9796 u32 tx_len, rx_len, r, v; 9797 struct tp_params *tpp = &adap->params.tp; 9798 9799 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9800 tpp->tre = G_TIMERRESOLUTION(v); 9801 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9802 9803 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9804 for (chan = 0; chan < MAX_NCHAN; chan++) 9805 tpp->tx_modq[chan] = chan; 9806 9807 read_filter_mode_and_ingress_config(adap); 9808 9809 if (chip_id(adap) > CHELSIO_T5) { 9810 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9811 tpp->rx_pkt_encap = v & F_CRXPKTENC; 9812 } else 9813 tpp->rx_pkt_encap = false; 9814 9815 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE); 9816 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE); 9817 9818 r = t4_read_reg(adap, A_TP_PARA_REG2); 9819 rx_len = min(rx_len, G_MAXRXDATA(r)); 9820 tx_len = min(tx_len, G_MAXRXDATA(r)); 9821 9822 r = t4_read_reg(adap, A_TP_PARA_REG7); 9823 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r)); 9824 rx_len = min(rx_len, v); 9825 tx_len = min(tx_len, v); 9826 9827 tpp->max_tx_pdu = tx_len; 9828 tpp->max_rx_pdu = rx_len; 9829 9830 return 0; 9831 } 9832 9833 /** 9834 * t4_filter_field_shift - calculate filter field shift 9835 * @adap: the adapter 9836 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9837 * 9838 * Return the shift position of a filter field within the Compressed 9839 * Filter Tuple. The filter field is specified via its selection bit 9840 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9841 */ 9842 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9843 { 9844 const unsigned int filter_mode = adap->params.tp.filter_mode; 9845 unsigned int sel; 9846 int field_shift; 9847 9848 if ((filter_mode & filter_sel) == 0) 9849 return -1; 9850 9851 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9852 switch (filter_mode & sel) { 9853 case F_FCOE: 9854 field_shift += W_FT_FCOE; 9855 break; 9856 case F_PORT: 9857 field_shift += W_FT_PORT; 9858 break; 9859 case F_VNIC_ID: 9860 field_shift += W_FT_VNIC_ID; 9861 break; 9862 case F_VLAN: 9863 field_shift += W_FT_VLAN; 9864 break; 9865 case F_TOS: 9866 field_shift += W_FT_TOS; 9867 break; 9868 case F_PROTOCOL: 9869 field_shift += W_FT_PROTOCOL; 9870 break; 9871 case F_ETHERTYPE: 9872 field_shift += W_FT_ETHERTYPE; 9873 break; 9874 case F_MACMATCH: 9875 field_shift += W_FT_MACMATCH; 9876 break; 9877 case F_MPSHITTYPE: 9878 field_shift += W_FT_MPSHITTYPE; 9879 break; 9880 case F_FRAGMENTATION: 9881 field_shift += W_FT_FRAGMENTATION; 9882 break; 9883 } 9884 } 9885 return field_shift; 9886 } 9887 9888 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9889 { 9890 u8 addr[6]; 9891 int ret, i, j; 9892 struct port_info *p = adap2pinfo(adap, port_id); 9893 u32 param, val; 9894 struct vi_info *vi = &p->vi[0]; 9895 9896 for (i = 0, j = -1; i <= p->port_id; i++) { 9897 do { 9898 j++; 9899 } while ((adap->params.portvec & (1 << j)) == 0); 9900 } 9901 9902 p->tx_chan = j; 9903 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9904 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9905 p->rx_c_chan = t4_get_rx_c_chan(adap, j); 9906 p->lport = j; 9907 9908 if (!(adap->flags & IS_VF) || 9909 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9910 t4_update_port_info(p); 9911 } 9912 9913 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, 9914 &vi->vfvld, &vi->vin); 9915 if (ret < 0) 9916 return ret; 9917 9918 vi->viid = ret; 9919 t4_os_set_hw_addr(p, addr); 9920 9921 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9922 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9923 V_FW_PARAMS_PARAM_YZ(vi->viid); 9924 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9925 if (ret) 9926 vi->rss_base = 0xffff; 9927 else { 9928 /* MPASS((val >> 16) == rss_size); */ 9929 vi->rss_base = val & 0xffff; 9930 } 9931 9932 return 0; 9933 } 9934 9935 /** 9936 * t4_read_cimq_cfg - read CIM queue configuration 9937 * @adap: the adapter 9938 * @base: holds the queue base addresses in bytes 9939 * @size: holds the queue sizes in bytes 9940 * @thres: holds the queue full thresholds in bytes 9941 * 9942 * Returns the current configuration of the CIM queues, starting with 9943 * the IBQs, then the OBQs. 9944 */ 9945 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9946 { 9947 unsigned int i, v; 9948 int cim_num_obq = adap->chip_params->cim_num_obq; 9949 9950 for (i = 0; i < CIM_NUM_IBQ; i++) { 9951 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9952 V_QUENUMSELECT(i)); 9953 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9954 /* value is in 256-byte units */ 9955 *base++ = G_CIMQBASE(v) * 256; 9956 *size++ = G_CIMQSIZE(v) * 256; 9957 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9958 } 9959 for (i = 0; i < cim_num_obq; i++) { 9960 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9961 V_QUENUMSELECT(i)); 9962 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9963 /* value is in 256-byte units */ 9964 *base++ = G_CIMQBASE(v) * 256; 9965 *size++ = G_CIMQSIZE(v) * 256; 9966 } 9967 } 9968 9969 /** 9970 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9971 * @adap: the adapter 9972 * @qid: the queue index 9973 * @data: where to store the queue contents 9974 * @n: capacity of @data in 32-bit words 9975 * 9976 * Reads the contents of the selected CIM queue starting at address 0 up 9977 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9978 * error and the number of 32-bit words actually read on success. 9979 */ 9980 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9981 { 9982 int i, err, attempts; 9983 unsigned int addr; 9984 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9985 9986 if (qid > 5 || (n & 3)) 9987 return -EINVAL; 9988 9989 addr = qid * nwords; 9990 if (n > nwords) 9991 n = nwords; 9992 9993 /* It might take 3-10ms before the IBQ debug read access is allowed. 9994 * Wait for 1 Sec with a delay of 1 usec. 9995 */ 9996 attempts = 1000000; 9997 9998 for (i = 0; i < n; i++, addr++) { 9999 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 10000 F_IBQDBGEN); 10001 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 10002 attempts, 1); 10003 if (err) 10004 return err; 10005 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 10006 } 10007 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 10008 return i; 10009 } 10010 10011 /** 10012 * t4_read_cim_obq - read the contents of a CIM outbound queue 10013 * @adap: the adapter 10014 * @qid: the queue index 10015 * @data: where to store the queue contents 10016 * @n: capacity of @data in 32-bit words 10017 * 10018 * Reads the contents of the selected CIM queue starting at address 0 up 10019 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 10020 * error and the number of 32-bit words actually read on success. 10021 */ 10022 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 10023 { 10024 int i, err; 10025 unsigned int addr, v, nwords; 10026 int cim_num_obq = adap->chip_params->cim_num_obq; 10027 10028 if ((qid > (cim_num_obq - 1)) || (n & 3)) 10029 return -EINVAL; 10030 10031 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 10032 V_QUENUMSELECT(qid)); 10033 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 10034 10035 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 10036 nwords = G_CIMQSIZE(v) * 64; /* same */ 10037 if (n > nwords) 10038 n = nwords; 10039 10040 for (i = 0; i < n; i++, addr++) { 10041 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 10042 F_OBQDBGEN); 10043 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 10044 2, 1); 10045 if (err) 10046 return err; 10047 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 10048 } 10049 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 10050 return i; 10051 } 10052 10053 enum { 10054 CIM_QCTL_BASE = 0, 10055 CIM_CTL_BASE = 0x2000, 10056 CIM_PBT_ADDR_BASE = 0x2800, 10057 CIM_PBT_LRF_BASE = 0x3000, 10058 CIM_PBT_DATA_BASE = 0x3800 10059 }; 10060 10061 /** 10062 * t4_cim_read - read a block from CIM internal address space 10063 * @adap: the adapter 10064 * @addr: the start address within the CIM address space 10065 * @n: number of words to read 10066 * @valp: where to store the result 10067 * 10068 * Reads a block of 4-byte words from the CIM intenal address space. 10069 */ 10070 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 10071 unsigned int *valp) 10072 { 10073 int ret = 0; 10074 10075 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10076 return -EBUSY; 10077 10078 for ( ; !ret && n--; addr += 4) { 10079 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 10080 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10081 0, 5, 2); 10082 if (!ret) 10083 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 10084 } 10085 return ret; 10086 } 10087 10088 /** 10089 * t4_cim_write - write a block into CIM internal address space 10090 * @adap: the adapter 10091 * @addr: the start address within the CIM address space 10092 * @n: number of words to write 10093 * @valp: set of values to write 10094 * 10095 * Writes a block of 4-byte words into the CIM intenal address space. 10096 */ 10097 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 10098 const unsigned int *valp) 10099 { 10100 int ret = 0; 10101 10102 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10103 return -EBUSY; 10104 10105 for ( ; !ret && n--; addr += 4) { 10106 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 10107 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 10108 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10109 0, 5, 2); 10110 } 10111 return ret; 10112 } 10113 10114 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 10115 unsigned int val) 10116 { 10117 return t4_cim_write(adap, addr, 1, &val); 10118 } 10119 10120 /** 10121 * t4_cim_ctl_read - read a block from CIM control region 10122 * @adap: the adapter 10123 * @addr: the start address within the CIM control region 10124 * @n: number of words to read 10125 * @valp: where to store the result 10126 * 10127 * Reads a block of 4-byte words from the CIM control region. 10128 */ 10129 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 10130 unsigned int *valp) 10131 { 10132 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 10133 } 10134 10135 /** 10136 * t4_cim_read_la - read CIM LA capture buffer 10137 * @adap: the adapter 10138 * @la_buf: where to store the LA data 10139 * @wrptr: the HW write pointer within the capture buffer 10140 * 10141 * Reads the contents of the CIM LA buffer with the most recent entry at 10142 * the end of the returned data and with the entry at @wrptr first. 10143 * We try to leave the LA in the running state we find it in. 10144 */ 10145 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 10146 { 10147 int i, ret; 10148 unsigned int cfg, val, idx; 10149 10150 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 10151 if (ret) 10152 return ret; 10153 10154 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 10155 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 10156 if (ret) 10157 return ret; 10158 } 10159 10160 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10161 if (ret) 10162 goto restart; 10163 10164 idx = G_UPDBGLAWRPTR(val); 10165 if (wrptr) 10166 *wrptr = idx; 10167 10168 for (i = 0; i < adap->params.cim_la_size; i++) { 10169 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10170 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 10171 if (ret) 10172 break; 10173 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10174 if (ret) 10175 break; 10176 if (val & F_UPDBGLARDEN) { 10177 ret = -ETIMEDOUT; 10178 break; 10179 } 10180 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 10181 if (ret) 10182 break; 10183 10184 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 10185 * identify the 32-bit portion of the full 312-bit data 10186 */ 10187 if (is_t6(adap) && (idx & 0xf) >= 9) 10188 idx = (idx & 0xff0) + 0x10; 10189 else 10190 idx++; 10191 /* address can't exceed 0xfff */ 10192 idx &= M_UPDBGLARDPTR; 10193 } 10194 restart: 10195 if (cfg & F_UPDBGLAEN) { 10196 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10197 cfg & ~F_UPDBGLARDEN); 10198 if (!ret) 10199 ret = r; 10200 } 10201 return ret; 10202 } 10203 10204 /** 10205 * t4_tp_read_la - read TP LA capture buffer 10206 * @adap: the adapter 10207 * @la_buf: where to store the LA data 10208 * @wrptr: the HW write pointer within the capture buffer 10209 * 10210 * Reads the contents of the TP LA buffer with the most recent entry at 10211 * the end of the returned data and with the entry at @wrptr first. 10212 * We leave the LA in the running state we find it in. 10213 */ 10214 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 10215 { 10216 bool last_incomplete; 10217 unsigned int i, cfg, val, idx; 10218 10219 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 10220 if (cfg & F_DBGLAENABLE) /* freeze LA */ 10221 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10222 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 10223 10224 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 10225 idx = G_DBGLAWPTR(val); 10226 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 10227 if (last_incomplete) 10228 idx = (idx + 1) & M_DBGLARPTR; 10229 if (wrptr) 10230 *wrptr = idx; 10231 10232 val &= 0xffff; 10233 val &= ~V_DBGLARPTR(M_DBGLARPTR); 10234 val |= adap->params.tp.la_mask; 10235 10236 for (i = 0; i < TPLA_SIZE; i++) { 10237 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 10238 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 10239 idx = (idx + 1) & M_DBGLARPTR; 10240 } 10241 10242 /* Wipe out last entry if it isn't valid */ 10243 if (last_incomplete) 10244 la_buf[TPLA_SIZE - 1] = ~0ULL; 10245 10246 if (cfg & F_DBGLAENABLE) /* restore running state */ 10247 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10248 cfg | adap->params.tp.la_mask); 10249 } 10250 10251 /* 10252 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 10253 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 10254 * state for more than the Warning Threshold then we'll issue a warning about 10255 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 10256 * appears to be hung every Warning Repeat second till the situation clears. 10257 * If the situation clears, we'll note that as well. 10258 */ 10259 #define SGE_IDMA_WARN_THRESH 1 10260 #define SGE_IDMA_WARN_REPEAT 300 10261 10262 /** 10263 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 10264 * @adapter: the adapter 10265 * @idma: the adapter IDMA Monitor state 10266 * 10267 * Initialize the state of an SGE Ingress DMA Monitor. 10268 */ 10269 void t4_idma_monitor_init(struct adapter *adapter, 10270 struct sge_idma_monitor_state *idma) 10271 { 10272 /* Initialize the state variables for detecting an SGE Ingress DMA 10273 * hang. The SGE has internal counters which count up on each clock 10274 * tick whenever the SGE finds its Ingress DMA State Engines in the 10275 * same state they were on the previous clock tick. The clock used is 10276 * the Core Clock so we have a limit on the maximum "time" they can 10277 * record; typically a very small number of seconds. For instance, 10278 * with a 600MHz Core Clock, we can only count up to a bit more than 10279 * 7s. So we'll synthesize a larger counter in order to not run the 10280 * risk of having the "timers" overflow and give us the flexibility to 10281 * maintain a Hung SGE State Machine of our own which operates across 10282 * a longer time frame. 10283 */ 10284 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 10285 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 10286 } 10287 10288 /** 10289 * t4_idma_monitor - monitor SGE Ingress DMA state 10290 * @adapter: the adapter 10291 * @idma: the adapter IDMA Monitor state 10292 * @hz: number of ticks/second 10293 * @ticks: number of ticks since the last IDMA Monitor call 10294 */ 10295 void t4_idma_monitor(struct adapter *adapter, 10296 struct sge_idma_monitor_state *idma, 10297 int hz, int ticks) 10298 { 10299 int i, idma_same_state_cnt[2]; 10300 10301 /* Read the SGE Debug Ingress DMA Same State Count registers. These 10302 * are counters inside the SGE which count up on each clock when the 10303 * SGE finds its Ingress DMA State Engines in the same states they 10304 * were in the previous clock. The counters will peg out at 10305 * 0xffffffff without wrapping around so once they pass the 1s 10306 * threshold they'll stay above that till the IDMA state changes. 10307 */ 10308 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 10309 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 10310 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10311 10312 for (i = 0; i < 2; i++) { 10313 u32 debug0, debug11; 10314 10315 /* If the Ingress DMA Same State Counter ("timer") is less 10316 * than 1s, then we can reset our synthesized Stall Timer and 10317 * continue. If we have previously emitted warnings about a 10318 * potential stalled Ingress Queue, issue a note indicating 10319 * that the Ingress Queue has resumed forward progress. 10320 */ 10321 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 10322 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 10323 CH_WARN(adapter, "SGE idma%d, queue %u, " 10324 "resumed after %d seconds\n", 10325 i, idma->idma_qid[i], 10326 idma->idma_stalled[i]/hz); 10327 idma->idma_stalled[i] = 0; 10328 continue; 10329 } 10330 10331 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 10332 * domain. The first time we get here it'll be because we 10333 * passed the 1s Threshold; each additional time it'll be 10334 * because the RX Timer Callback is being fired on its regular 10335 * schedule. 10336 * 10337 * If the stall is below our Potential Hung Ingress Queue 10338 * Warning Threshold, continue. 10339 */ 10340 if (idma->idma_stalled[i] == 0) { 10341 idma->idma_stalled[i] = hz; 10342 idma->idma_warn[i] = 0; 10343 } else { 10344 idma->idma_stalled[i] += ticks; 10345 idma->idma_warn[i] -= ticks; 10346 } 10347 10348 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 10349 continue; 10350 10351 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 10352 */ 10353 if (idma->idma_warn[i] > 0) 10354 continue; 10355 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 10356 10357 /* Read and save the SGE IDMA State and Queue ID information. 10358 * We do this every time in case it changes across time ... 10359 * can't be too careful ... 10360 */ 10361 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 10362 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10363 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 10364 10365 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 10366 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10367 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 10368 10369 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 10370 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 10371 i, idma->idma_qid[i], idma->idma_state[i], 10372 idma->idma_stalled[i]/hz, 10373 debug0, debug11); 10374 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 10375 } 10376 } 10377 10378 /** 10379 * t4_set_vf_mac - Set MAC address for the specified VF 10380 * @adapter: The adapter 10381 * @pf: the PF used to instantiate the VFs 10382 * @vf: one of the VFs instantiated by the specified PF 10383 * @naddr: the number of MAC addresses 10384 * @addr: the MAC address(es) to be set to the specified VF 10385 */ 10386 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf, 10387 unsigned int naddr, u8 *addr) 10388 { 10389 struct fw_acl_mac_cmd cmd; 10390 10391 memset(&cmd, 0, sizeof(cmd)); 10392 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) | 10393 F_FW_CMD_REQUEST | 10394 F_FW_CMD_WRITE | 10395 V_FW_ACL_MAC_CMD_PFN(pf) | 10396 V_FW_ACL_MAC_CMD_VFN(vf)); 10397 10398 /* Note: Do not enable the ACL */ 10399 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd)); 10400 cmd.nmac = naddr; 10401 10402 switch (pf) { 10403 case 3: 10404 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3)); 10405 break; 10406 case 2: 10407 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2)); 10408 break; 10409 case 1: 10410 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1)); 10411 break; 10412 case 0: 10413 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0)); 10414 break; 10415 } 10416 10417 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); 10418 } 10419 10420 /** 10421 * t4_read_pace_tbl - read the pace table 10422 * @adap: the adapter 10423 * @pace_vals: holds the returned values 10424 * 10425 * Returns the values of TP's pace table in microseconds. 10426 */ 10427 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 10428 { 10429 unsigned int i, v; 10430 10431 for (i = 0; i < NTX_SCHED; i++) { 10432 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 10433 v = t4_read_reg(adap, A_TP_PACE_TABLE); 10434 pace_vals[i] = dack_ticks_to_usec(adap, v); 10435 } 10436 } 10437 10438 /** 10439 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 10440 * @adap: the adapter 10441 * @sched: the scheduler index 10442 * @kbps: the byte rate in Kbps 10443 * @ipg: the interpacket delay in tenths of nanoseconds 10444 * 10445 * Return the current configuration of a HW Tx scheduler. 10446 */ 10447 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 10448 unsigned int *ipg, bool sleep_ok) 10449 { 10450 unsigned int v, addr, bpt, cpt; 10451 10452 if (kbps) { 10453 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 10454 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10455 if (sched & 1) 10456 v >>= 16; 10457 bpt = (v >> 8) & 0xff; 10458 cpt = v & 0xff; 10459 if (!cpt) 10460 *kbps = 0; /* scheduler disabled */ 10461 else { 10462 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 10463 *kbps = (v * bpt) / 125; 10464 } 10465 } 10466 if (ipg) { 10467 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 10468 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10469 if (sched & 1) 10470 v >>= 16; 10471 v &= 0xffff; 10472 *ipg = (10000 * v) / core_ticks_per_usec(adap); 10473 } 10474 } 10475 10476 /** 10477 * t4_load_cfg - download config file 10478 * @adap: the adapter 10479 * @cfg_data: the cfg text file to write 10480 * @size: text file size 10481 * 10482 * Write the supplied config text file to the card's serial flash. 10483 */ 10484 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 10485 { 10486 int ret, i, n, cfg_addr; 10487 unsigned int addr; 10488 unsigned int flash_cfg_start_sec; 10489 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10490 10491 cfg_addr = t4_flash_cfg_addr(adap); 10492 if (cfg_addr < 0) 10493 return cfg_addr; 10494 10495 addr = cfg_addr; 10496 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10497 10498 if (size > FLASH_CFG_MAX_SIZE) { 10499 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 10500 FLASH_CFG_MAX_SIZE); 10501 return -EFBIG; 10502 } 10503 10504 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 10505 sf_sec_size); 10506 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10507 flash_cfg_start_sec + i - 1); 10508 /* 10509 * If size == 0 then we're simply erasing the FLASH sectors associated 10510 * with the on-adapter Firmware Configuration File. 10511 */ 10512 if (ret || size == 0) 10513 goto out; 10514 10515 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10516 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10517 if ( (size - i) < SF_PAGE_SIZE) 10518 n = size - i; 10519 else 10520 n = SF_PAGE_SIZE; 10521 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 10522 if (ret) 10523 goto out; 10524 10525 addr += SF_PAGE_SIZE; 10526 cfg_data += SF_PAGE_SIZE; 10527 } 10528 10529 out: 10530 if (ret) 10531 CH_ERR(adap, "config file %s failed %d\n", 10532 (size == 0 ? "clear" : "download"), ret); 10533 return ret; 10534 } 10535 10536 /** 10537 * t5_fw_init_extern_mem - initialize the external memory 10538 * @adap: the adapter 10539 * 10540 * Initializes the external memory on T5. 10541 */ 10542 int t5_fw_init_extern_mem(struct adapter *adap) 10543 { 10544 u32 params[1], val[1]; 10545 int ret; 10546 10547 if (!is_t5(adap)) 10548 return 0; 10549 10550 val[0] = 0xff; /* Initialize all MCs */ 10551 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10552 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 10553 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 10554 FW_CMD_MAX_TIMEOUT); 10555 10556 return ret; 10557 } 10558 10559 /* BIOS boot headers */ 10560 typedef struct pci_expansion_rom_header { 10561 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10562 u8 reserved[22]; /* Reserved per processor Architecture data */ 10563 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10564 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 10565 10566 /* Legacy PCI Expansion ROM Header */ 10567 typedef struct legacy_pci_expansion_rom_header { 10568 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10569 u8 size512; /* Current Image Size in units of 512 bytes */ 10570 u8 initentry_point[4]; 10571 u8 cksum; /* Checksum computed on the entire Image */ 10572 u8 reserved[16]; /* Reserved */ 10573 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 10574 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 10575 10576 /* EFI PCI Expansion ROM Header */ 10577 typedef struct efi_pci_expansion_rom_header { 10578 u8 signature[2]; // ROM signature. The value 0xaa55 10579 u8 initialization_size[2]; /* Units 512. Includes this header */ 10580 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 10581 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 10582 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 10583 u8 compression_type[2]; /* Compression type. */ 10584 /* 10585 * Compression type definition 10586 * 0x0: uncompressed 10587 * 0x1: Compressed 10588 * 0x2-0xFFFF: Reserved 10589 */ 10590 u8 reserved[8]; /* Reserved */ 10591 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 10592 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10593 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 10594 10595 /* PCI Data Structure Format */ 10596 typedef struct pcir_data_structure { /* PCI Data Structure */ 10597 u8 signature[4]; /* Signature. The string "PCIR" */ 10598 u8 vendor_id[2]; /* Vendor Identification */ 10599 u8 device_id[2]; /* Device Identification */ 10600 u8 vital_product[2]; /* Pointer to Vital Product Data */ 10601 u8 length[2]; /* PCIR Data Structure Length */ 10602 u8 revision; /* PCIR Data Structure Revision */ 10603 u8 class_code[3]; /* Class Code */ 10604 u8 image_length[2]; /* Image Length. Multiple of 512B */ 10605 u8 code_revision[2]; /* Revision Level of Code/Data */ 10606 u8 code_type; /* Code Type. */ 10607 /* 10608 * PCI Expansion ROM Code Types 10609 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10610 * 0x01: Open Firmware standard for PCI. FCODE 10611 * 0x02: Hewlett-Packard PA RISC. HP reserved 10612 * 0x03: EFI Image. EFI 10613 * 0x04-0xFF: Reserved. 10614 */ 10615 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10616 u8 reserved[2]; /* Reserved */ 10617 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 10618 10619 /* BOOT constants */ 10620 enum { 10621 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10622 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10623 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10624 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10625 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10626 VENDOR_ID = 0x1425, /* Vendor ID */ 10627 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10628 }; 10629 10630 /* 10631 * modify_device_id - Modifies the device ID of the Boot BIOS image 10632 * @adatper: the device ID to write. 10633 * @boot_data: the boot image to modify. 10634 * 10635 * Write the supplied device ID to the boot BIOS image. 10636 */ 10637 static void modify_device_id(int device_id, u8 *boot_data) 10638 { 10639 legacy_pci_exp_rom_header_t *header; 10640 pcir_data_t *pcir_header; 10641 u32 cur_header = 0; 10642 10643 /* 10644 * Loop through all chained images and change the device ID's 10645 */ 10646 while (1) { 10647 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10648 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10649 le16_to_cpu(*(u16*)header->pcir_offset)]; 10650 10651 /* 10652 * Only modify the Device ID if code type is Legacy or HP. 10653 * 0x00: Okay to modify 10654 * 0x01: FCODE. Do not be modify 10655 * 0x03: Okay to modify 10656 * 0x04-0xFF: Do not modify 10657 */ 10658 if (pcir_header->code_type == 0x00) { 10659 u8 csum = 0; 10660 int i; 10661 10662 /* 10663 * Modify Device ID to match current adatper 10664 */ 10665 *(u16*) pcir_header->device_id = device_id; 10666 10667 /* 10668 * Set checksum temporarily to 0. 10669 * We will recalculate it later. 10670 */ 10671 header->cksum = 0x0; 10672 10673 /* 10674 * Calculate and update checksum 10675 */ 10676 for (i = 0; i < (header->size512 * 512); i++) 10677 csum += (u8)boot_data[cur_header + i]; 10678 10679 /* 10680 * Invert summed value to create the checksum 10681 * Writing new checksum value directly to the boot data 10682 */ 10683 boot_data[cur_header + 7] = -csum; 10684 10685 } else if (pcir_header->code_type == 0x03) { 10686 10687 /* 10688 * Modify Device ID to match current adatper 10689 */ 10690 *(u16*) pcir_header->device_id = device_id; 10691 10692 } 10693 10694 10695 /* 10696 * Check indicator element to identify if this is the last 10697 * image in the ROM. 10698 */ 10699 if (pcir_header->indicator & 0x80) 10700 break; 10701 10702 /* 10703 * Move header pointer up to the next image in the ROM. 10704 */ 10705 cur_header += header->size512 * 512; 10706 } 10707 } 10708 10709 /* 10710 * t4_load_boot - download boot flash 10711 * @adapter: the adapter 10712 * @boot_data: the boot image to write 10713 * @boot_addr: offset in flash to write boot_data 10714 * @size: image size 10715 * 10716 * Write the supplied boot image to the card's serial flash. 10717 * The boot image has the following sections: a 28-byte header and the 10718 * boot image. 10719 */ 10720 int t4_load_boot(struct adapter *adap, u8 *boot_data, 10721 unsigned int boot_addr, unsigned int size) 10722 { 10723 pci_exp_rom_header_t *header; 10724 int pcir_offset ; 10725 pcir_data_t *pcir_header; 10726 int ret, addr; 10727 uint16_t device_id; 10728 unsigned int i; 10729 unsigned int boot_sector = (boot_addr * 1024 ); 10730 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10731 10732 /* 10733 * Make sure the boot image does not encroach on the firmware region 10734 */ 10735 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10736 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10737 return -EFBIG; 10738 } 10739 10740 /* 10741 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10742 * and Boot configuration data sections. These 3 boot sections span 10743 * sectors 0 to 7 in flash and live right before the FW image location. 10744 */ 10745 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10746 sf_sec_size); 10747 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10748 (boot_sector >> 16) + i - 1); 10749 10750 /* 10751 * If size == 0 then we're simply erasing the FLASH sectors associated 10752 * with the on-adapter option ROM file 10753 */ 10754 if (ret || (size == 0)) 10755 goto out; 10756 10757 /* Get boot header */ 10758 header = (pci_exp_rom_header_t *)boot_data; 10759 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10760 /* PCIR Data Structure */ 10761 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10762 10763 /* 10764 * Perform some primitive sanity testing to avoid accidentally 10765 * writing garbage over the boot sectors. We ought to check for 10766 * more but it's not worth it for now ... 10767 */ 10768 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10769 CH_ERR(adap, "boot image too small/large\n"); 10770 return -EFBIG; 10771 } 10772 10773 #ifndef CHELSIO_T4_DIAGS 10774 /* 10775 * Check BOOT ROM header signature 10776 */ 10777 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10778 CH_ERR(adap, "Boot image missing signature\n"); 10779 return -EINVAL; 10780 } 10781 10782 /* 10783 * Check PCI header signature 10784 */ 10785 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10786 CH_ERR(adap, "PCI header missing signature\n"); 10787 return -EINVAL; 10788 } 10789 10790 /* 10791 * Check Vendor ID matches Chelsio ID 10792 */ 10793 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10794 CH_ERR(adap, "Vendor ID missing signature\n"); 10795 return -EINVAL; 10796 } 10797 #endif 10798 10799 /* 10800 * Retrieve adapter's device ID 10801 */ 10802 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10803 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10804 device_id = device_id & 0xf0ff; 10805 10806 /* 10807 * Check PCIE Device ID 10808 */ 10809 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10810 /* 10811 * Change the device ID in the Boot BIOS image to match 10812 * the Device ID of the current adapter. 10813 */ 10814 modify_device_id(device_id, boot_data); 10815 } 10816 10817 /* 10818 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10819 * we finish copying the rest of the boot image. This will ensure 10820 * that the BIOS boot header will only be written if the boot image 10821 * was written in full. 10822 */ 10823 addr = boot_sector; 10824 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10825 addr += SF_PAGE_SIZE; 10826 boot_data += SF_PAGE_SIZE; 10827 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10828 if (ret) 10829 goto out; 10830 } 10831 10832 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10833 (const u8 *)header, 0); 10834 10835 out: 10836 if (ret) 10837 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10838 return ret; 10839 } 10840 10841 /* 10842 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10843 * @adapter: the adapter 10844 * 10845 * Return the address within the flash where the OptionROM Configuration 10846 * is stored, or an error if the device FLASH is too small to contain 10847 * a OptionROM Configuration. 10848 */ 10849 static int t4_flash_bootcfg_addr(struct adapter *adapter) 10850 { 10851 /* 10852 * If the device FLASH isn't large enough to hold a Firmware 10853 * Configuration File, return an error. 10854 */ 10855 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10856 return -ENOSPC; 10857 10858 return FLASH_BOOTCFG_START; 10859 } 10860 10861 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10862 { 10863 int ret, i, n, cfg_addr; 10864 unsigned int addr; 10865 unsigned int flash_cfg_start_sec; 10866 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10867 10868 cfg_addr = t4_flash_bootcfg_addr(adap); 10869 if (cfg_addr < 0) 10870 return cfg_addr; 10871 10872 addr = cfg_addr; 10873 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10874 10875 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10876 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10877 FLASH_BOOTCFG_MAX_SIZE); 10878 return -EFBIG; 10879 } 10880 10881 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10882 sf_sec_size); 10883 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10884 flash_cfg_start_sec + i - 1); 10885 10886 /* 10887 * If size == 0 then we're simply erasing the FLASH sectors associated 10888 * with the on-adapter OptionROM Configuration File. 10889 */ 10890 if (ret || size == 0) 10891 goto out; 10892 10893 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10894 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10895 if ( (size - i) < SF_PAGE_SIZE) 10896 n = size - i; 10897 else 10898 n = SF_PAGE_SIZE; 10899 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10900 if (ret) 10901 goto out; 10902 10903 addr += SF_PAGE_SIZE; 10904 cfg_data += SF_PAGE_SIZE; 10905 } 10906 10907 out: 10908 if (ret) 10909 CH_ERR(adap, "boot config data %s failed %d\n", 10910 (size == 0 ? "clear" : "download"), ret); 10911 return ret; 10912 } 10913 10914 /** 10915 * t4_set_filter_cfg - set up filter mode/mask and ingress config. 10916 * @adap: the adapter 10917 * @mode: a bitmap selecting which optional filter components to enable 10918 * @mask: a bitmap selecting which components to enable in filter mask 10919 * @vnic_mode: the ingress config/vnic mode setting 10920 * 10921 * Sets the filter mode and mask by selecting the optional components to 10922 * enable in filter tuples. Returns 0 on success and a negative error if 10923 * the requested mode needs more bits than are available for optional 10924 * components. The filter mask must be a subset of the filter mode. 10925 */ 10926 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode) 10927 { 10928 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 10929 int i, nbits, rc; 10930 uint32_t param, val; 10931 uint16_t fmode, fmask; 10932 const int maxbits = adap->chip_params->filter_opt_len; 10933 10934 if (mode != -1 || mask != -1) { 10935 if (mode != -1) { 10936 fmode = mode; 10937 nbits = 0; 10938 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10939 if (fmode & (1 << i)) 10940 nbits += width[i]; 10941 } 10942 if (nbits > maxbits) { 10943 CH_ERR(adap, "optional fields in the filter " 10944 "mode (0x%x) add up to %d bits " 10945 "(must be <= %db). Remove some fields and " 10946 "try again.\n", fmode, nbits, maxbits); 10947 return -E2BIG; 10948 } 10949 10950 /* 10951 * Hardware wants the bits to be maxed out. Keep 10952 * setting them until there's no room for more. 10953 */ 10954 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10955 if (fmode & (1 << i)) 10956 continue; 10957 if (nbits + width[i] <= maxbits) { 10958 fmode |= 1 << i; 10959 nbits += width[i]; 10960 if (nbits == maxbits) 10961 break; 10962 } 10963 } 10964 10965 fmask = fmode & adap->params.tp.filter_mask; 10966 if (fmask != adap->params.tp.filter_mask) { 10967 CH_WARN(adap, 10968 "filter mask will be changed from 0x%x to " 10969 "0x%x to comply with the filter mode (0x%x).\n", 10970 adap->params.tp.filter_mask, fmask, fmode); 10971 } 10972 } else { 10973 fmode = adap->params.tp.filter_mode; 10974 fmask = mask; 10975 if ((fmode | fmask) != fmode) { 10976 CH_ERR(adap, 10977 "filter mask (0x%x) must be a subset of " 10978 "the filter mode (0x%x).\n", fmask, fmode); 10979 return -EINVAL; 10980 } 10981 } 10982 10983 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10984 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10985 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 10986 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) | 10987 V_FW_PARAMS_PARAM_FILTER_MASK(fmask); 10988 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10989 &val); 10990 if (rc < 0) 10991 return rc; 10992 } 10993 10994 if (vnic_mode != -1) { 10995 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10996 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10997 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 10998 val = vnic_mode; 10999 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 11000 &val); 11001 if (rc < 0) 11002 return rc; 11003 } 11004 11005 /* Refresh. */ 11006 read_filter_mode_and_ingress_config(adap); 11007 11008 return 0; 11009 } 11010 11011 /** 11012 * t4_clr_port_stats - clear port statistics 11013 * @adap: the adapter 11014 * @idx: the port index 11015 * 11016 * Clear HW statistics for the given port. 11017 */ 11018 void t4_clr_port_stats(struct adapter *adap, int idx) 11019 { 11020 unsigned int i; 11021 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 11022 u32 port_base_addr; 11023 11024 if (is_t4(adap)) 11025 port_base_addr = PORT_BASE(idx); 11026 else 11027 port_base_addr = T5_PORT_BASE(idx); 11028 11029 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 11030 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 11031 t4_write_reg(adap, port_base_addr + i, 0); 11032 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 11033 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 11034 t4_write_reg(adap, port_base_addr + i, 0); 11035 for (i = 0; i < 4; i++) 11036 if (bgmap & (1 << i)) { 11037 t4_write_reg(adap, 11038 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 11039 t4_write_reg(adap, 11040 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 11041 } 11042 } 11043 11044 /** 11045 * t4_i2c_io - read/write I2C data from adapter 11046 * @adap: the adapter 11047 * @port: Port number if per-port device; <0 if not 11048 * @devid: per-port device ID or absolute device ID 11049 * @offset: byte offset into device I2C space 11050 * @len: byte length of I2C space data 11051 * @buf: buffer in which to return I2C data for read 11052 * buffer which holds the I2C data for write 11053 * @write: if true, do a write; else do a read 11054 * Reads/Writes the I2C data from/to the indicated device and location. 11055 */ 11056 int t4_i2c_io(struct adapter *adap, unsigned int mbox, 11057 int port, unsigned int devid, 11058 unsigned int offset, unsigned int len, 11059 u8 *buf, bool write) 11060 { 11061 struct fw_ldst_cmd ldst_cmd, ldst_rpl; 11062 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data); 11063 int ret = 0; 11064 11065 if (len > I2C_PAGE_SIZE) 11066 return -EINVAL; 11067 11068 /* Dont allow reads that spans multiple pages */ 11069 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) 11070 return -EINVAL; 11071 11072 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 11073 ldst_cmd.op_to_addrspace = 11074 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11075 F_FW_CMD_REQUEST | 11076 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) | 11077 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 11078 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 11079 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port); 11080 ldst_cmd.u.i2c.did = devid; 11081 11082 while (len > 0) { 11083 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max; 11084 11085 ldst_cmd.u.i2c.boffset = offset; 11086 ldst_cmd.u.i2c.blen = i2c_len; 11087 11088 if (write) 11089 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len); 11090 11091 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd), 11092 write ? NULL : &ldst_rpl); 11093 if (ret) 11094 break; 11095 11096 if (!write) 11097 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len); 11098 offset += i2c_len; 11099 buf += i2c_len; 11100 len -= i2c_len; 11101 } 11102 11103 return ret; 11104 } 11105 11106 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 11107 int port, unsigned int devid, 11108 unsigned int offset, unsigned int len, 11109 u8 *buf) 11110 { 11111 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false); 11112 } 11113 11114 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 11115 int port, unsigned int devid, 11116 unsigned int offset, unsigned int len, 11117 u8 *buf) 11118 { 11119 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true); 11120 } 11121 11122 /** 11123 * t4_sge_ctxt_rd - read an SGE context through FW 11124 * @adap: the adapter 11125 * @mbox: mailbox to use for the FW command 11126 * @cid: the context id 11127 * @ctype: the context type 11128 * @data: where to store the context data 11129 * 11130 * Issues a FW command through the given mailbox to read an SGE context. 11131 */ 11132 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 11133 enum ctxt_type ctype, u32 *data) 11134 { 11135 int ret; 11136 struct fw_ldst_cmd c; 11137 11138 if (ctype == CTXT_EGRESS) 11139 ret = FW_LDST_ADDRSPC_SGE_EGRC; 11140 else if (ctype == CTXT_INGRESS) 11141 ret = FW_LDST_ADDRSPC_SGE_INGC; 11142 else if (ctype == CTXT_FLM) 11143 ret = FW_LDST_ADDRSPC_SGE_FLMC; 11144 else 11145 ret = FW_LDST_ADDRSPC_SGE_CONMC; 11146 11147 memset(&c, 0, sizeof(c)); 11148 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11149 F_FW_CMD_REQUEST | F_FW_CMD_READ | 11150 V_FW_LDST_CMD_ADDRSPACE(ret)); 11151 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 11152 c.u.idctxt.physid = cpu_to_be32(cid); 11153 11154 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11155 if (ret == 0) { 11156 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 11157 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 11158 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 11159 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 11160 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 11161 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 11162 } 11163 return ret; 11164 } 11165 11166 /** 11167 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 11168 * @adap: the adapter 11169 * @cid: the context id 11170 * @ctype: the context type 11171 * @data: where to store the context data 11172 * 11173 * Reads an SGE context directly, bypassing FW. This is only for 11174 * debugging when FW is unavailable. 11175 */ 11176 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 11177 u32 *data) 11178 { 11179 int i, ret; 11180 11181 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 11182 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 11183 if (!ret) 11184 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 11185 *data++ = t4_read_reg(adap, i); 11186 return ret; 11187 } 11188 11189 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 11190 int sleep_ok) 11191 { 11192 struct fw_sched_cmd cmd; 11193 11194 memset(&cmd, 0, sizeof(cmd)); 11195 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11196 F_FW_CMD_REQUEST | 11197 F_FW_CMD_WRITE); 11198 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11199 11200 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 11201 cmd.u.config.type = type; 11202 cmd.u.config.minmaxen = minmaxen; 11203 11204 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11205 NULL, sleep_ok); 11206 } 11207 11208 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 11209 int rateunit, int ratemode, int channel, int cl, 11210 int minrate, int maxrate, int weight, int pktsize, 11211 int burstsize, int sleep_ok) 11212 { 11213 struct fw_sched_cmd cmd; 11214 11215 memset(&cmd, 0, sizeof(cmd)); 11216 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11217 F_FW_CMD_REQUEST | 11218 F_FW_CMD_WRITE); 11219 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11220 11221 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11222 cmd.u.params.type = type; 11223 cmd.u.params.level = level; 11224 cmd.u.params.mode = mode; 11225 cmd.u.params.ch = channel; 11226 cmd.u.params.cl = cl; 11227 cmd.u.params.unit = rateunit; 11228 cmd.u.params.rate = ratemode; 11229 cmd.u.params.min = cpu_to_be32(minrate); 11230 cmd.u.params.max = cpu_to_be32(maxrate); 11231 cmd.u.params.weight = cpu_to_be16(weight); 11232 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11233 cmd.u.params.burstsize = cpu_to_be16(burstsize); 11234 11235 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11236 NULL, sleep_ok); 11237 } 11238 11239 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 11240 unsigned int maxrate, int sleep_ok) 11241 { 11242 struct fw_sched_cmd cmd; 11243 11244 memset(&cmd, 0, sizeof(cmd)); 11245 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11246 F_FW_CMD_REQUEST | 11247 F_FW_CMD_WRITE); 11248 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11249 11250 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11251 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11252 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 11253 cmd.u.params.ch = channel; 11254 cmd.u.params.rate = ratemode; /* REL or ABS */ 11255 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 11256 11257 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11258 NULL, sleep_ok); 11259 } 11260 11261 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 11262 int weight, int sleep_ok) 11263 { 11264 struct fw_sched_cmd cmd; 11265 11266 if (weight < 0 || weight > 100) 11267 return -EINVAL; 11268 11269 memset(&cmd, 0, sizeof(cmd)); 11270 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11271 F_FW_CMD_REQUEST | 11272 F_FW_CMD_WRITE); 11273 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11274 11275 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11276 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11277 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 11278 cmd.u.params.ch = channel; 11279 cmd.u.params.cl = cl; 11280 cmd.u.params.weight = cpu_to_be16(weight); 11281 11282 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11283 NULL, sleep_ok); 11284 } 11285 11286 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 11287 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 11288 { 11289 struct fw_sched_cmd cmd; 11290 11291 memset(&cmd, 0, sizeof(cmd)); 11292 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11293 F_FW_CMD_REQUEST | 11294 F_FW_CMD_WRITE); 11295 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11296 11297 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11298 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11299 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 11300 cmd.u.params.mode = mode; 11301 cmd.u.params.ch = channel; 11302 cmd.u.params.cl = cl; 11303 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 11304 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 11305 cmd.u.params.max = cpu_to_be32(maxrate); 11306 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11307 11308 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11309 NULL, sleep_ok); 11310 } 11311 11312 /* 11313 * t4_config_watchdog - configure (enable/disable) a watchdog timer 11314 * @adapter: the adapter 11315 * @mbox: mailbox to use for the FW command 11316 * @pf: the PF owning the queue 11317 * @vf: the VF owning the queue 11318 * @timeout: watchdog timeout in ms 11319 * @action: watchdog timer / action 11320 * 11321 * There are separate watchdog timers for each possible watchdog 11322 * action. Configure one of the watchdog timers by setting a non-zero 11323 * timeout. Disable a watchdog timer by using a timeout of zero. 11324 */ 11325 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 11326 unsigned int pf, unsigned int vf, 11327 unsigned int timeout, unsigned int action) 11328 { 11329 struct fw_watchdog_cmd wdog; 11330 unsigned int ticks; 11331 11332 /* 11333 * The watchdog command expects a timeout in units of 10ms so we need 11334 * to convert it here (via rounding) and force a minimum of one 10ms 11335 * "tick" if the timeout is non-zero but the conversion results in 0 11336 * ticks. 11337 */ 11338 ticks = (timeout + 5)/10; 11339 if (timeout && !ticks) 11340 ticks = 1; 11341 11342 memset(&wdog, 0, sizeof wdog); 11343 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 11344 F_FW_CMD_REQUEST | 11345 F_FW_CMD_WRITE | 11346 V_FW_PARAMS_CMD_PFN(pf) | 11347 V_FW_PARAMS_CMD_VFN(vf)); 11348 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 11349 wdog.timeout = cpu_to_be32(ticks); 11350 wdog.action = cpu_to_be32(action); 11351 11352 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 11353 } 11354 11355 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 11356 { 11357 struct fw_devlog_cmd devlog_cmd; 11358 int ret; 11359 11360 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11361 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11362 F_FW_CMD_REQUEST | F_FW_CMD_READ); 11363 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11364 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11365 sizeof(devlog_cmd), &devlog_cmd); 11366 if (ret) 11367 return ret; 11368 11369 *level = devlog_cmd.level; 11370 return 0; 11371 } 11372 11373 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 11374 { 11375 struct fw_devlog_cmd devlog_cmd; 11376 11377 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11378 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11379 F_FW_CMD_REQUEST | 11380 F_FW_CMD_WRITE); 11381 devlog_cmd.level = level; 11382 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11383 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11384 sizeof(devlog_cmd), &devlog_cmd); 11385 } 11386 11387 int t4_configure_add_smac(struct adapter *adap) 11388 { 11389 unsigned int param, val; 11390 int ret = 0; 11391 11392 adap->params.smac_add_support = 0; 11393 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11394 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC)); 11395 /* Query FW to check if FW supports adding source mac address 11396 * to TCAM feature or not. 11397 * If FW returns 1, driver can use this feature and driver need to send 11398 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to 11399 * enable adding smac to TCAM. 11400 */ 11401 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11402 if (ret) 11403 return ret; 11404 11405 if (val == 1) { 11406 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 11407 ¶m, &val); 11408 if (!ret) 11409 /* Firmware allows adding explicit TCAM entries. 11410 * Save this internally. 11411 */ 11412 adap->params.smac_add_support = 1; 11413 } 11414 11415 return ret; 11416 } 11417 11418 int t4_configure_ringbb(struct adapter *adap) 11419 { 11420 unsigned int param, val; 11421 int ret = 0; 11422 11423 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11424 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE)); 11425 /* Query FW to check if FW supports ring switch feature or not. 11426 * If FW returns 1, driver can use this feature and driver need to send 11427 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to 11428 * enable the ring backbone configuration. 11429 */ 11430 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11431 if (ret < 0) { 11432 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n", 11433 ret); 11434 goto out; 11435 } 11436 11437 if (val != 1) { 11438 CH_ERR(adap, "FW doesnot support ringbackbone features\n"); 11439 goto out; 11440 } 11441 11442 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11443 if (ret < 0) { 11444 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n", 11445 ret); 11446 goto out; 11447 } 11448 11449 out: 11450 return ret; 11451 } 11452 11453 /* 11454 * t4_set_vlan_acl - Set a VLAN id for the specified VF 11455 * @adapter: the adapter 11456 * @mbox: mailbox to use for the FW command 11457 * @vf: one of the VFs instantiated by the specified PF 11458 * @vlan: The vlanid to be set 11459 * 11460 */ 11461 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 11462 u16 vlan) 11463 { 11464 struct fw_acl_vlan_cmd vlan_cmd; 11465 unsigned int enable; 11466 11467 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0); 11468 memset(&vlan_cmd, 0, sizeof(vlan_cmd)); 11469 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) | 11470 F_FW_CMD_REQUEST | 11471 F_FW_CMD_WRITE | 11472 F_FW_CMD_EXEC | 11473 V_FW_ACL_VLAN_CMD_PFN(adap->pf) | 11474 V_FW_ACL_VLAN_CMD_VFN(vf)); 11475 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd)); 11476 /* Drop all packets that donot match vlan id */ 11477 vlan_cmd.dropnovlan_fm = (enable 11478 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN | 11479 F_FW_ACL_VLAN_CMD_FM) 11480 : 0); 11481 if (enable != 0) { 11482 vlan_cmd.nvlan = 1; 11483 vlan_cmd.vlanid[0] = cpu_to_be16(vlan); 11484 } 11485 11486 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); 11487 } 11488 11489 /** 11490 * t4_del_mac - Removes the exact-match filter for a MAC address 11491 * @adap: the adapter 11492 * @mbox: mailbox to use for the FW command 11493 * @viid: the VI id 11494 * @addr: the MAC address value 11495 * @smac: if true, delete from only the smac region of MPS 11496 * 11497 * Modifies an exact-match filter and sets it to the new MAC address if 11498 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11499 * latter case the address is added persistently if @persist is %true. 11500 * 11501 * Returns a negative error number or the index of the filter with the new 11502 * MAC value. Note that this index may differ from @idx. 11503 */ 11504 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11505 const u8 *addr, bool smac) 11506 { 11507 int ret; 11508 struct fw_vi_mac_cmd c; 11509 struct fw_vi_mac_exact *p = c.u.exact; 11510 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11511 11512 memset(&c, 0, sizeof(c)); 11513 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11514 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11515 V_FW_VI_MAC_CMD_VIID(viid)); 11516 c.freemacs_to_len16 = cpu_to_be32( 11517 V_FW_CMD_LEN16(1) | 11518 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11519 11520 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11521 p->valid_to_idx = cpu_to_be16( 11522 F_FW_VI_MAC_CMD_VALID | 11523 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 11524 11525 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11526 if (ret == 0) { 11527 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11528 if (ret < max_mac_addr) 11529 return -ENOMEM; 11530 } 11531 11532 return ret; 11533 } 11534 11535 /** 11536 * t4_add_mac - Adds an exact-match filter for a MAC address 11537 * @adap: the adapter 11538 * @mbox: mailbox to use for the FW command 11539 * @viid: the VI id 11540 * @idx: index of existing filter for old value of MAC address, or -1 11541 * @addr: the new MAC address value 11542 * @persist: whether a new MAC allocation should be persistent 11543 * @add_smt: if true also add the address to the HW SMT 11544 * @smac: if true, update only the smac region of MPS 11545 * 11546 * Modifies an exact-match filter and sets it to the new MAC address if 11547 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11548 * latter case the address is added persistently if @persist is %true. 11549 * 11550 * Returns a negative error number or the index of the filter with the new 11551 * MAC value. Note that this index may differ from @idx. 11552 */ 11553 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11554 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac) 11555 { 11556 int ret, mode; 11557 struct fw_vi_mac_cmd c; 11558 struct fw_vi_mac_exact *p = c.u.exact; 11559 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11560 11561 if (idx < 0) /* new allocation */ 11562 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 11563 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 11564 11565 memset(&c, 0, sizeof(c)); 11566 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11567 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11568 V_FW_VI_MAC_CMD_VIID(viid)); 11569 c.freemacs_to_len16 = cpu_to_be32( 11570 V_FW_CMD_LEN16(1) | 11571 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11572 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 11573 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 11574 V_FW_VI_MAC_CMD_IDX(idx)); 11575 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11576 11577 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11578 if (ret == 0) { 11579 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11580 if (ret >= max_mac_addr) 11581 return -ENOMEM; 11582 if (smt_idx) { 11583 /* Does fw supports returning smt_idx? */ 11584 if (adap->params.viid_smt_extn_support) 11585 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 11586 else { 11587 /* In T4/T5, SMT contains 256 SMAC entries 11588 * organized in 128 rows of 2 entries each. 11589 * In T6, SMT contains 256 SMAC entries in 11590 * 256 rows. 11591 */ 11592 if (chip_id(adap) <= CHELSIO_T5) 11593 *smt_idx = ((viid & M_FW_VIID_VIN) << 1); 11594 else 11595 *smt_idx = (viid & M_FW_VIID_VIN); 11596 } 11597 } 11598 } 11599 11600 return ret; 11601 } 11602