1# Copyright 2010-2016 The OpenSSL Project Authors. All Rights Reserved. 2# 3# Licensed under the Apache License 2.0 (the "License"). You may not use 4# this file except in compliance with the License. You can obtain a copy 5# in the file LICENSE in the source distribution or at 6# https://www.openssl.org/source/license.html 7 8# 9# ==================================================================== 10# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL 11# project. The module is, however, dual licensed under OpenSSL and 12# CRYPTOGAMS licenses depending on where you obtain it. For further 13# details see http://www.openssl.org/~appro/cryptogams/. 14# ==================================================================== 15# 16# March, June 2010 17# 18# The module implements "4-bit" GCM GHASH function and underlying 19# single multiplication operation in GF(2^128). "4-bit" means that 20# it uses 256 bytes per-key table [+128 bytes shared table]. GHASH 21# function features so called "528B" variant utilizing additional 22# 256+16 bytes of per-key storage [+512 bytes shared table]. 23# Performance results are for this streamed GHASH subroutine and are 24# expressed in cycles per processed byte, less is better: 25# 26# gcc 3.4.x(*) assembler 27# 28# P4 28.6 14.0 +100% 29# Opteron 19.3 7.7 +150% 30# Core2 17.8 8.1(**) +120% 31# Atom 31.6 16.8 +88% 32# VIA Nano 21.8 10.1 +115% 33# 34# (*) comparison is not completely fair, because C results are 35# for vanilla "256B" implementation, while assembler results 36# are for "528B";-) 37# (**) it's mystery [to me] why Core2 result is not same as for 38# Opteron; 39 40# May 2010 41# 42# Add PCLMULQDQ version performing at 2.02 cycles per processed byte. 43# See ghash-x86.pl for background information and details about coding 44# techniques. 45# 46# Special thanks to David Woodhouse for providing access to a 47# Westmere-based system on behalf of Intel Open Source Technology Centre. 48 49# December 2012 50# 51# Overhaul: aggregate Karatsuba post-processing, improve ILP in 52# reduction_alg9, increase reduction aggregate factor to 4x. As for 53# the latter. ghash-x86.pl discusses that it makes lesser sense to 54# increase aggregate factor. Then why increase here? Critical path 55# consists of 3 independent pclmulqdq instructions, Karatsuba post- 56# processing and reduction. "On top" of this we lay down aggregated 57# multiplication operations, triplets of independent pclmulqdq's. As 58# issue rate for pclmulqdq is limited, it makes lesser sense to 59# aggregate more multiplications than it takes to perform remaining 60# non-multiplication operations. 2x is near-optimal coefficient for 61# contemporary Intel CPUs (therefore modest improvement coefficient), 62# but not for Bulldozer. Latter is because logical SIMD operations 63# are twice as slow in comparison to Intel, so that critical path is 64# longer. A CPU with higher pclmulqdq issue rate would also benefit 65# from higher aggregate factor... 66# 67# Westmere 1.78(+13%) 68# Sandy Bridge 1.80(+8%) 69# Ivy Bridge 1.80(+7%) 70# Haswell 0.55(+93%) (if system doesn't support AVX) 71# Broadwell 0.45(+110%)(if system doesn't support AVX) 72# Skylake 0.44(+110%)(if system doesn't support AVX) 73# Bulldozer 1.49(+27%) 74# Silvermont 2.88(+13%) 75# Knights L 2.12(-) (if system doesn't support AVX) 76# Goldmont 1.08(+24%) 77 78# March 2013 79# 80# ... 8x aggregate factor AVX code path is using reduction algorithm 81# suggested by Shay Gueron[1]. Even though contemporary AVX-capable 82# CPUs such as Sandy and Ivy Bridge can execute it, the code performs 83# sub-optimally in comparison to above mentioned version. But thanks 84# to Ilya Albrekht and Max Locktyukhin of Intel Corp. we knew that 85# it performs in 0.41 cycles per byte on Haswell processor, in 86# 0.29 on Broadwell, and in 0.36 on Skylake. 87# 88# Knights Landing achieves 1.09 cpb. 89# 90# [1] http://rt.openssl.org/Ticket/Display.html?id=2900&user=guest&pass=guest 91 92# Generated once from 93# https://github.com/openssl/openssl/blob/5ffc3324/crypto/modes/asm/ghash-x86_64.pl 94# and modified for ICP. Modification are kept at a bare minimum to ease later 95# upstream merges. 96 97#if defined(__x86_64__) && defined(HAVE_AVX) && \ 98 defined(HAVE_AES) && defined(HAVE_PCLMULQDQ) 99 100.text 101 102.globl gcm_gmult_clmul 103.type gcm_gmult_clmul,@function 104.align 16 105gcm_gmult_clmul: 106.cfi_startproc 107.L_gmult_clmul: 108 movdqu (%rdi),%xmm0 109 movdqa .Lbswap_mask(%rip),%xmm5 110 movdqu (%rsi),%xmm2 111 movdqu 32(%rsi),%xmm4 112.byte 102,15,56,0,197 113 movdqa %xmm0,%xmm1 114 pshufd $78,%xmm0,%xmm3 115 pxor %xmm0,%xmm3 116.byte 102,15,58,68,194,0 117.byte 102,15,58,68,202,17 118.byte 102,15,58,68,220,0 119 pxor %xmm0,%xmm3 120 pxor %xmm1,%xmm3 121 122 movdqa %xmm3,%xmm4 123 psrldq $8,%xmm3 124 pslldq $8,%xmm4 125 pxor %xmm3,%xmm1 126 pxor %xmm4,%xmm0 127 128 movdqa %xmm0,%xmm4 129 movdqa %xmm0,%xmm3 130 psllq $5,%xmm0 131 pxor %xmm0,%xmm3 132 psllq $1,%xmm0 133 pxor %xmm3,%xmm0 134 psllq $57,%xmm0 135 movdqa %xmm0,%xmm3 136 pslldq $8,%xmm0 137 psrldq $8,%xmm3 138 pxor %xmm4,%xmm0 139 pxor %xmm3,%xmm1 140 141 142 movdqa %xmm0,%xmm4 143 psrlq $1,%xmm0 144 pxor %xmm4,%xmm1 145 pxor %xmm0,%xmm4 146 psrlq $5,%xmm0 147 pxor %xmm4,%xmm0 148 psrlq $1,%xmm0 149 pxor %xmm1,%xmm0 150.byte 102,15,56,0,197 151 movdqu %xmm0,(%rdi) 152 .byte 0xf3,0xc3 153.cfi_endproc 154.size gcm_gmult_clmul,.-gcm_gmult_clmul 155 156.globl gcm_init_htab_avx 157.type gcm_init_htab_avx,@function 158.align 32 159gcm_init_htab_avx: 160.cfi_startproc 161 vzeroupper 162 163 vmovdqu (%rsi),%xmm2 164 // KCF/ICP stores H in network byte order with the hi qword first 165 // so we need to swap all bytes, not the 2 qwords. 166 vmovdqu .Lbswap_mask(%rip),%xmm4 167 vpshufb %xmm4,%xmm2,%xmm2 168 169 170 vpshufd $255,%xmm2,%xmm4 171 vpsrlq $63,%xmm2,%xmm3 172 vpsllq $1,%xmm2,%xmm2 173 vpxor %xmm5,%xmm5,%xmm5 174 vpcmpgtd %xmm4,%xmm5,%xmm5 175 vpslldq $8,%xmm3,%xmm3 176 vpor %xmm3,%xmm2,%xmm2 177 178 179 vpand .L0x1c2_polynomial(%rip),%xmm5,%xmm5 180 vpxor %xmm5,%xmm2,%xmm2 181 182 vpunpckhqdq %xmm2,%xmm2,%xmm6 183 vmovdqa %xmm2,%xmm0 184 vpxor %xmm2,%xmm6,%xmm6 185 movq $4,%r10 186 jmp .Linit_start_avx 187.align 32 188.Linit_loop_avx: 189 vpalignr $8,%xmm3,%xmm4,%xmm5 190 vmovdqu %xmm5,-16(%rdi) 191 vpunpckhqdq %xmm0,%xmm0,%xmm3 192 vpxor %xmm0,%xmm3,%xmm3 193 vpclmulqdq $0x11,%xmm2,%xmm0,%xmm1 194 vpclmulqdq $0x00,%xmm2,%xmm0,%xmm0 195 vpclmulqdq $0x00,%xmm6,%xmm3,%xmm3 196 vpxor %xmm0,%xmm1,%xmm4 197 vpxor %xmm4,%xmm3,%xmm3 198 199 vpslldq $8,%xmm3,%xmm4 200 vpsrldq $8,%xmm3,%xmm3 201 vpxor %xmm4,%xmm0,%xmm0 202 vpxor %xmm3,%xmm1,%xmm1 203 vpsllq $57,%xmm0,%xmm3 204 vpsllq $62,%xmm0,%xmm4 205 vpxor %xmm3,%xmm4,%xmm4 206 vpsllq $63,%xmm0,%xmm3 207 vpxor %xmm3,%xmm4,%xmm4 208 vpslldq $8,%xmm4,%xmm3 209 vpsrldq $8,%xmm4,%xmm4 210 vpxor %xmm3,%xmm0,%xmm0 211 vpxor %xmm4,%xmm1,%xmm1 212 213 vpsrlq $1,%xmm0,%xmm4 214 vpxor %xmm0,%xmm1,%xmm1 215 vpxor %xmm4,%xmm0,%xmm0 216 vpsrlq $5,%xmm4,%xmm4 217 vpxor %xmm4,%xmm0,%xmm0 218 vpsrlq $1,%xmm0,%xmm0 219 vpxor %xmm1,%xmm0,%xmm0 220.Linit_start_avx: 221 vmovdqa %xmm0,%xmm5 222 vpunpckhqdq %xmm0,%xmm0,%xmm3 223 vpxor %xmm0,%xmm3,%xmm3 224 vpclmulqdq $0x11,%xmm2,%xmm0,%xmm1 225 vpclmulqdq $0x00,%xmm2,%xmm0,%xmm0 226 vpclmulqdq $0x00,%xmm6,%xmm3,%xmm3 227 vpxor %xmm0,%xmm1,%xmm4 228 vpxor %xmm4,%xmm3,%xmm3 229 230 vpslldq $8,%xmm3,%xmm4 231 vpsrldq $8,%xmm3,%xmm3 232 vpxor %xmm4,%xmm0,%xmm0 233 vpxor %xmm3,%xmm1,%xmm1 234 vpsllq $57,%xmm0,%xmm3 235 vpsllq $62,%xmm0,%xmm4 236 vpxor %xmm3,%xmm4,%xmm4 237 vpsllq $63,%xmm0,%xmm3 238 vpxor %xmm3,%xmm4,%xmm4 239 vpslldq $8,%xmm4,%xmm3 240 vpsrldq $8,%xmm4,%xmm4 241 vpxor %xmm3,%xmm0,%xmm0 242 vpxor %xmm4,%xmm1,%xmm1 243 244 vpsrlq $1,%xmm0,%xmm4 245 vpxor %xmm0,%xmm1,%xmm1 246 vpxor %xmm4,%xmm0,%xmm0 247 vpsrlq $5,%xmm4,%xmm4 248 vpxor %xmm4,%xmm0,%xmm0 249 vpsrlq $1,%xmm0,%xmm0 250 vpxor %xmm1,%xmm0,%xmm0 251 vpshufd $78,%xmm5,%xmm3 252 vpshufd $78,%xmm0,%xmm4 253 vpxor %xmm5,%xmm3,%xmm3 254 vmovdqu %xmm5,0(%rdi) 255 vpxor %xmm0,%xmm4,%xmm4 256 vmovdqu %xmm0,16(%rdi) 257 leaq 48(%rdi),%rdi 258 subq $1,%r10 259 jnz .Linit_loop_avx 260 261 vpalignr $8,%xmm4,%xmm3,%xmm5 262 vmovdqu %xmm5,-16(%rdi) 263 264 vzeroupper 265 .byte 0xf3,0xc3 266.cfi_endproc 267.size gcm_init_htab_avx,.-gcm_init_htab_avx 268 269.globl gcm_gmult_avx 270.type gcm_gmult_avx,@function 271.align 32 272gcm_gmult_avx: 273.cfi_startproc 274 jmp .L_gmult_clmul 275.cfi_endproc 276.size gcm_gmult_avx,.-gcm_gmult_avx 277.globl gcm_ghash_avx 278.type gcm_ghash_avx,@function 279.align 32 280gcm_ghash_avx: 281.cfi_startproc 282 vzeroupper 283 284 vmovdqu (%rdi),%xmm10 285 leaq .L0x1c2_polynomial(%rip),%r10 286 leaq 64(%rsi),%rsi 287 vmovdqu .Lbswap_mask(%rip),%xmm13 288 vpshufb %xmm13,%xmm10,%xmm10 289 cmpq $0x80,%rcx 290 jb .Lshort_avx 291 subq $0x80,%rcx 292 293 vmovdqu 112(%rdx),%xmm14 294 vmovdqu 0-64(%rsi),%xmm6 295 vpshufb %xmm13,%xmm14,%xmm14 296 vmovdqu 32-64(%rsi),%xmm7 297 298 vpunpckhqdq %xmm14,%xmm14,%xmm9 299 vmovdqu 96(%rdx),%xmm15 300 vpclmulqdq $0x00,%xmm6,%xmm14,%xmm0 301 vpxor %xmm14,%xmm9,%xmm9 302 vpshufb %xmm13,%xmm15,%xmm15 303 vpclmulqdq $0x11,%xmm6,%xmm14,%xmm1 304 vmovdqu 16-64(%rsi),%xmm6 305 vpunpckhqdq %xmm15,%xmm15,%xmm8 306 vmovdqu 80(%rdx),%xmm14 307 vpclmulqdq $0x00,%xmm7,%xmm9,%xmm2 308 vpxor %xmm15,%xmm8,%xmm8 309 310 vpshufb %xmm13,%xmm14,%xmm14 311 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm3 312 vpunpckhqdq %xmm14,%xmm14,%xmm9 313 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm4 314 vmovdqu 48-64(%rsi),%xmm6 315 vpxor %xmm14,%xmm9,%xmm9 316 vmovdqu 64(%rdx),%xmm15 317 vpclmulqdq $0x10,%xmm7,%xmm8,%xmm5 318 vmovdqu 80-64(%rsi),%xmm7 319 320 vpshufb %xmm13,%xmm15,%xmm15 321 vpxor %xmm0,%xmm3,%xmm3 322 vpclmulqdq $0x00,%xmm6,%xmm14,%xmm0 323 vpxor %xmm1,%xmm4,%xmm4 324 vpunpckhqdq %xmm15,%xmm15,%xmm8 325 vpclmulqdq $0x11,%xmm6,%xmm14,%xmm1 326 vmovdqu 64-64(%rsi),%xmm6 327 vpxor %xmm2,%xmm5,%xmm5 328 vpclmulqdq $0x00,%xmm7,%xmm9,%xmm2 329 vpxor %xmm15,%xmm8,%xmm8 330 331 vmovdqu 48(%rdx),%xmm14 332 vpxor %xmm3,%xmm0,%xmm0 333 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm3 334 vpxor %xmm4,%xmm1,%xmm1 335 vpshufb %xmm13,%xmm14,%xmm14 336 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm4 337 vmovdqu 96-64(%rsi),%xmm6 338 vpxor %xmm5,%xmm2,%xmm2 339 vpunpckhqdq %xmm14,%xmm14,%xmm9 340 vpclmulqdq $0x10,%xmm7,%xmm8,%xmm5 341 vmovdqu 128-64(%rsi),%xmm7 342 vpxor %xmm14,%xmm9,%xmm9 343 344 vmovdqu 32(%rdx),%xmm15 345 vpxor %xmm0,%xmm3,%xmm3 346 vpclmulqdq $0x00,%xmm6,%xmm14,%xmm0 347 vpxor %xmm1,%xmm4,%xmm4 348 vpshufb %xmm13,%xmm15,%xmm15 349 vpclmulqdq $0x11,%xmm6,%xmm14,%xmm1 350 vmovdqu 112-64(%rsi),%xmm6 351 vpxor %xmm2,%xmm5,%xmm5 352 vpunpckhqdq %xmm15,%xmm15,%xmm8 353 vpclmulqdq $0x00,%xmm7,%xmm9,%xmm2 354 vpxor %xmm15,%xmm8,%xmm8 355 356 vmovdqu 16(%rdx),%xmm14 357 vpxor %xmm3,%xmm0,%xmm0 358 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm3 359 vpxor %xmm4,%xmm1,%xmm1 360 vpshufb %xmm13,%xmm14,%xmm14 361 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm4 362 vmovdqu 144-64(%rsi),%xmm6 363 vpxor %xmm5,%xmm2,%xmm2 364 vpunpckhqdq %xmm14,%xmm14,%xmm9 365 vpclmulqdq $0x10,%xmm7,%xmm8,%xmm5 366 vmovdqu 176-64(%rsi),%xmm7 367 vpxor %xmm14,%xmm9,%xmm9 368 369 vmovdqu (%rdx),%xmm15 370 vpxor %xmm0,%xmm3,%xmm3 371 vpclmulqdq $0x00,%xmm6,%xmm14,%xmm0 372 vpxor %xmm1,%xmm4,%xmm4 373 vpshufb %xmm13,%xmm15,%xmm15 374 vpclmulqdq $0x11,%xmm6,%xmm14,%xmm1 375 vmovdqu 160-64(%rsi),%xmm6 376 vpxor %xmm2,%xmm5,%xmm5 377 vpclmulqdq $0x10,%xmm7,%xmm9,%xmm2 378 379 leaq 128(%rdx),%rdx 380 cmpq $0x80,%rcx 381 jb .Ltail_avx 382 383 vpxor %xmm10,%xmm15,%xmm15 384 subq $0x80,%rcx 385 jmp .Loop8x_avx 386 387.align 32 388.Loop8x_avx: 389 vpunpckhqdq %xmm15,%xmm15,%xmm8 390 vmovdqu 112(%rdx),%xmm14 391 vpxor %xmm0,%xmm3,%xmm3 392 vpxor %xmm15,%xmm8,%xmm8 393 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm10 394 vpshufb %xmm13,%xmm14,%xmm14 395 vpxor %xmm1,%xmm4,%xmm4 396 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm11 397 vmovdqu 0-64(%rsi),%xmm6 398 vpunpckhqdq %xmm14,%xmm14,%xmm9 399 vpxor %xmm2,%xmm5,%xmm5 400 vpclmulqdq $0x00,%xmm7,%xmm8,%xmm12 401 vmovdqu 32-64(%rsi),%xmm7 402 vpxor %xmm14,%xmm9,%xmm9 403 404 vmovdqu 96(%rdx),%xmm15 405 vpclmulqdq $0x00,%xmm6,%xmm14,%xmm0 406 vpxor %xmm3,%xmm10,%xmm10 407 vpshufb %xmm13,%xmm15,%xmm15 408 vpclmulqdq $0x11,%xmm6,%xmm14,%xmm1 409 vxorps %xmm4,%xmm11,%xmm11 410 vmovdqu 16-64(%rsi),%xmm6 411 vpunpckhqdq %xmm15,%xmm15,%xmm8 412 vpclmulqdq $0x00,%xmm7,%xmm9,%xmm2 413 vpxor %xmm5,%xmm12,%xmm12 414 vxorps %xmm15,%xmm8,%xmm8 415 416 vmovdqu 80(%rdx),%xmm14 417 vpxor %xmm10,%xmm12,%xmm12 418 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm3 419 vpxor %xmm11,%xmm12,%xmm12 420 vpslldq $8,%xmm12,%xmm9 421 vpxor %xmm0,%xmm3,%xmm3 422 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm4 423 vpsrldq $8,%xmm12,%xmm12 424 vpxor %xmm9,%xmm10,%xmm10 425 vmovdqu 48-64(%rsi),%xmm6 426 vpshufb %xmm13,%xmm14,%xmm14 427 vxorps %xmm12,%xmm11,%xmm11 428 vpxor %xmm1,%xmm4,%xmm4 429 vpunpckhqdq %xmm14,%xmm14,%xmm9 430 vpclmulqdq $0x10,%xmm7,%xmm8,%xmm5 431 vmovdqu 80-64(%rsi),%xmm7 432 vpxor %xmm14,%xmm9,%xmm9 433 vpxor %xmm2,%xmm5,%xmm5 434 435 vmovdqu 64(%rdx),%xmm15 436 vpalignr $8,%xmm10,%xmm10,%xmm12 437 vpclmulqdq $0x00,%xmm6,%xmm14,%xmm0 438 vpshufb %xmm13,%xmm15,%xmm15 439 vpxor %xmm3,%xmm0,%xmm0 440 vpclmulqdq $0x11,%xmm6,%xmm14,%xmm1 441 vmovdqu 64-64(%rsi),%xmm6 442 vpunpckhqdq %xmm15,%xmm15,%xmm8 443 vpxor %xmm4,%xmm1,%xmm1 444 vpclmulqdq $0x00,%xmm7,%xmm9,%xmm2 445 vxorps %xmm15,%xmm8,%xmm8 446 vpxor %xmm5,%xmm2,%xmm2 447 448 vmovdqu 48(%rdx),%xmm14 449 vpclmulqdq $0x10,(%r10),%xmm10,%xmm10 450 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm3 451 vpshufb %xmm13,%xmm14,%xmm14 452 vpxor %xmm0,%xmm3,%xmm3 453 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm4 454 vmovdqu 96-64(%rsi),%xmm6 455 vpunpckhqdq %xmm14,%xmm14,%xmm9 456 vpxor %xmm1,%xmm4,%xmm4 457 vpclmulqdq $0x10,%xmm7,%xmm8,%xmm5 458 vmovdqu 128-64(%rsi),%xmm7 459 vpxor %xmm14,%xmm9,%xmm9 460 vpxor %xmm2,%xmm5,%xmm5 461 462 vmovdqu 32(%rdx),%xmm15 463 vpclmulqdq $0x00,%xmm6,%xmm14,%xmm0 464 vpshufb %xmm13,%xmm15,%xmm15 465 vpxor %xmm3,%xmm0,%xmm0 466 vpclmulqdq $0x11,%xmm6,%xmm14,%xmm1 467 vmovdqu 112-64(%rsi),%xmm6 468 vpunpckhqdq %xmm15,%xmm15,%xmm8 469 vpxor %xmm4,%xmm1,%xmm1 470 vpclmulqdq $0x00,%xmm7,%xmm9,%xmm2 471 vpxor %xmm15,%xmm8,%xmm8 472 vpxor %xmm5,%xmm2,%xmm2 473 vxorps %xmm12,%xmm10,%xmm10 474 475 vmovdqu 16(%rdx),%xmm14 476 vpalignr $8,%xmm10,%xmm10,%xmm12 477 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm3 478 vpshufb %xmm13,%xmm14,%xmm14 479 vpxor %xmm0,%xmm3,%xmm3 480 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm4 481 vmovdqu 144-64(%rsi),%xmm6 482 vpclmulqdq $0x10,(%r10),%xmm10,%xmm10 483 vxorps %xmm11,%xmm12,%xmm12 484 vpunpckhqdq %xmm14,%xmm14,%xmm9 485 vpxor %xmm1,%xmm4,%xmm4 486 vpclmulqdq $0x10,%xmm7,%xmm8,%xmm5 487 vmovdqu 176-64(%rsi),%xmm7 488 vpxor %xmm14,%xmm9,%xmm9 489 vpxor %xmm2,%xmm5,%xmm5 490 491 vmovdqu (%rdx),%xmm15 492 vpclmulqdq $0x00,%xmm6,%xmm14,%xmm0 493 vpshufb %xmm13,%xmm15,%xmm15 494 vpclmulqdq $0x11,%xmm6,%xmm14,%xmm1 495 vmovdqu 160-64(%rsi),%xmm6 496 vpxor %xmm12,%xmm15,%xmm15 497 vpclmulqdq $0x10,%xmm7,%xmm9,%xmm2 498 vpxor %xmm10,%xmm15,%xmm15 499 500 leaq 128(%rdx),%rdx 501 subq $0x80,%rcx 502 jnc .Loop8x_avx 503 504 addq $0x80,%rcx 505 jmp .Ltail_no_xor_avx 506 507.align 32 508.Lshort_avx: 509 vmovdqu -16(%rdx,%rcx,1),%xmm14 510 leaq (%rdx,%rcx,1),%rdx 511 vmovdqu 0-64(%rsi),%xmm6 512 vmovdqu 32-64(%rsi),%xmm7 513 vpshufb %xmm13,%xmm14,%xmm15 514 515 vmovdqa %xmm0,%xmm3 516 vmovdqa %xmm1,%xmm4 517 vmovdqa %xmm2,%xmm5 518 subq $0x10,%rcx 519 jz .Ltail_avx 520 521 vpunpckhqdq %xmm15,%xmm15,%xmm8 522 vpxor %xmm0,%xmm3,%xmm3 523 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm0 524 vpxor %xmm15,%xmm8,%xmm8 525 vmovdqu -32(%rdx),%xmm14 526 vpxor %xmm1,%xmm4,%xmm4 527 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm1 528 vmovdqu 16-64(%rsi),%xmm6 529 vpshufb %xmm13,%xmm14,%xmm15 530 vpxor %xmm2,%xmm5,%xmm5 531 vpclmulqdq $0x00,%xmm7,%xmm8,%xmm2 532 vpsrldq $8,%xmm7,%xmm7 533 subq $0x10,%rcx 534 jz .Ltail_avx 535 536 vpunpckhqdq %xmm15,%xmm15,%xmm8 537 vpxor %xmm0,%xmm3,%xmm3 538 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm0 539 vpxor %xmm15,%xmm8,%xmm8 540 vmovdqu -48(%rdx),%xmm14 541 vpxor %xmm1,%xmm4,%xmm4 542 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm1 543 vmovdqu 48-64(%rsi),%xmm6 544 vpshufb %xmm13,%xmm14,%xmm15 545 vpxor %xmm2,%xmm5,%xmm5 546 vpclmulqdq $0x00,%xmm7,%xmm8,%xmm2 547 vmovdqu 80-64(%rsi),%xmm7 548 subq $0x10,%rcx 549 jz .Ltail_avx 550 551 vpunpckhqdq %xmm15,%xmm15,%xmm8 552 vpxor %xmm0,%xmm3,%xmm3 553 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm0 554 vpxor %xmm15,%xmm8,%xmm8 555 vmovdqu -64(%rdx),%xmm14 556 vpxor %xmm1,%xmm4,%xmm4 557 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm1 558 vmovdqu 64-64(%rsi),%xmm6 559 vpshufb %xmm13,%xmm14,%xmm15 560 vpxor %xmm2,%xmm5,%xmm5 561 vpclmulqdq $0x00,%xmm7,%xmm8,%xmm2 562 vpsrldq $8,%xmm7,%xmm7 563 subq $0x10,%rcx 564 jz .Ltail_avx 565 566 vpunpckhqdq %xmm15,%xmm15,%xmm8 567 vpxor %xmm0,%xmm3,%xmm3 568 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm0 569 vpxor %xmm15,%xmm8,%xmm8 570 vmovdqu -80(%rdx),%xmm14 571 vpxor %xmm1,%xmm4,%xmm4 572 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm1 573 vmovdqu 96-64(%rsi),%xmm6 574 vpshufb %xmm13,%xmm14,%xmm15 575 vpxor %xmm2,%xmm5,%xmm5 576 vpclmulqdq $0x00,%xmm7,%xmm8,%xmm2 577 vmovdqu 128-64(%rsi),%xmm7 578 subq $0x10,%rcx 579 jz .Ltail_avx 580 581 vpunpckhqdq %xmm15,%xmm15,%xmm8 582 vpxor %xmm0,%xmm3,%xmm3 583 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm0 584 vpxor %xmm15,%xmm8,%xmm8 585 vmovdqu -96(%rdx),%xmm14 586 vpxor %xmm1,%xmm4,%xmm4 587 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm1 588 vmovdqu 112-64(%rsi),%xmm6 589 vpshufb %xmm13,%xmm14,%xmm15 590 vpxor %xmm2,%xmm5,%xmm5 591 vpclmulqdq $0x00,%xmm7,%xmm8,%xmm2 592 vpsrldq $8,%xmm7,%xmm7 593 subq $0x10,%rcx 594 jz .Ltail_avx 595 596 vpunpckhqdq %xmm15,%xmm15,%xmm8 597 vpxor %xmm0,%xmm3,%xmm3 598 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm0 599 vpxor %xmm15,%xmm8,%xmm8 600 vmovdqu -112(%rdx),%xmm14 601 vpxor %xmm1,%xmm4,%xmm4 602 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm1 603 vmovdqu 144-64(%rsi),%xmm6 604 vpshufb %xmm13,%xmm14,%xmm15 605 vpxor %xmm2,%xmm5,%xmm5 606 vpclmulqdq $0x00,%xmm7,%xmm8,%xmm2 607 vmovq 184-64(%rsi),%xmm7 608 subq $0x10,%rcx 609 jmp .Ltail_avx 610 611.align 32 612.Ltail_avx: 613 vpxor %xmm10,%xmm15,%xmm15 614.Ltail_no_xor_avx: 615 vpunpckhqdq %xmm15,%xmm15,%xmm8 616 vpxor %xmm0,%xmm3,%xmm3 617 vpclmulqdq $0x00,%xmm6,%xmm15,%xmm0 618 vpxor %xmm15,%xmm8,%xmm8 619 vpxor %xmm1,%xmm4,%xmm4 620 vpclmulqdq $0x11,%xmm6,%xmm15,%xmm1 621 vpxor %xmm2,%xmm5,%xmm5 622 vpclmulqdq $0x00,%xmm7,%xmm8,%xmm2 623 624 vmovdqu (%r10),%xmm12 625 626 vpxor %xmm0,%xmm3,%xmm10 627 vpxor %xmm1,%xmm4,%xmm11 628 vpxor %xmm2,%xmm5,%xmm5 629 630 vpxor %xmm10,%xmm5,%xmm5 631 vpxor %xmm11,%xmm5,%xmm5 632 vpslldq $8,%xmm5,%xmm9 633 vpsrldq $8,%xmm5,%xmm5 634 vpxor %xmm9,%xmm10,%xmm10 635 vpxor %xmm5,%xmm11,%xmm11 636 637 vpclmulqdq $0x10,%xmm12,%xmm10,%xmm9 638 vpalignr $8,%xmm10,%xmm10,%xmm10 639 vpxor %xmm9,%xmm10,%xmm10 640 641 vpclmulqdq $0x10,%xmm12,%xmm10,%xmm9 642 vpalignr $8,%xmm10,%xmm10,%xmm10 643 vpxor %xmm11,%xmm10,%xmm10 644 vpxor %xmm9,%xmm10,%xmm10 645 646 cmpq $0,%rcx 647 jne .Lshort_avx 648 649 vpshufb %xmm13,%xmm10,%xmm10 650 vmovdqu %xmm10,(%rdi) 651 vzeroupper 652 .byte 0xf3,0xc3 653.cfi_endproc 654.size gcm_ghash_avx,.-gcm_ghash_avx 655.align 64 656.Lbswap_mask: 657.byte 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0 658.L0x1c2_polynomial: 659.byte 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0xc2 660.L7_mask: 661.long 7,0,7,0 662.L7_mask_poly: 663.long 7,0,450,0 664.align 64 665.type .Lrem_4bit,@object 666.Lrem_4bit: 667.long 0,0,0,471859200,0,943718400,0,610271232 668.long 0,1887436800,0,1822425088,0,1220542464,0,1423966208 669.long 0,3774873600,0,4246732800,0,3644850176,0,3311403008 670.long 0,2441084928,0,2376073216,0,2847932416,0,3051356160 671.type .Lrem_8bit,@object 672.Lrem_8bit: 673.value 0x0000,0x01C2,0x0384,0x0246,0x0708,0x06CA,0x048C,0x054E 674.value 0x0E10,0x0FD2,0x0D94,0x0C56,0x0918,0x08DA,0x0A9C,0x0B5E 675.value 0x1C20,0x1DE2,0x1FA4,0x1E66,0x1B28,0x1AEA,0x18AC,0x196E 676.value 0x1230,0x13F2,0x11B4,0x1076,0x1538,0x14FA,0x16BC,0x177E 677.value 0x3840,0x3982,0x3BC4,0x3A06,0x3F48,0x3E8A,0x3CCC,0x3D0E 678.value 0x3650,0x3792,0x35D4,0x3416,0x3158,0x309A,0x32DC,0x331E 679.value 0x2460,0x25A2,0x27E4,0x2626,0x2368,0x22AA,0x20EC,0x212E 680.value 0x2A70,0x2BB2,0x29F4,0x2836,0x2D78,0x2CBA,0x2EFC,0x2F3E 681.value 0x7080,0x7142,0x7304,0x72C6,0x7788,0x764A,0x740C,0x75CE 682.value 0x7E90,0x7F52,0x7D14,0x7CD6,0x7998,0x785A,0x7A1C,0x7BDE 683.value 0x6CA0,0x6D62,0x6F24,0x6EE6,0x6BA8,0x6A6A,0x682C,0x69EE 684.value 0x62B0,0x6372,0x6134,0x60F6,0x65B8,0x647A,0x663C,0x67FE 685.value 0x48C0,0x4902,0x4B44,0x4A86,0x4FC8,0x4E0A,0x4C4C,0x4D8E 686.value 0x46D0,0x4712,0x4554,0x4496,0x41D8,0x401A,0x425C,0x439E 687.value 0x54E0,0x5522,0x5764,0x56A6,0x53E8,0x522A,0x506C,0x51AE 688.value 0x5AF0,0x5B32,0x5974,0x58B6,0x5DF8,0x5C3A,0x5E7C,0x5FBE 689.value 0xE100,0xE0C2,0xE284,0xE346,0xE608,0xE7CA,0xE58C,0xE44E 690.value 0xEF10,0xEED2,0xEC94,0xED56,0xE818,0xE9DA,0xEB9C,0xEA5E 691.value 0xFD20,0xFCE2,0xFEA4,0xFF66,0xFA28,0xFBEA,0xF9AC,0xF86E 692.value 0xF330,0xF2F2,0xF0B4,0xF176,0xF438,0xF5FA,0xF7BC,0xF67E 693.value 0xD940,0xD882,0xDAC4,0xDB06,0xDE48,0xDF8A,0xDDCC,0xDC0E 694.value 0xD750,0xD692,0xD4D4,0xD516,0xD058,0xD19A,0xD3DC,0xD21E 695.value 0xC560,0xC4A2,0xC6E4,0xC726,0xC268,0xC3AA,0xC1EC,0xC02E 696.value 0xCB70,0xCAB2,0xC8F4,0xC936,0xCC78,0xCDBA,0xCFFC,0xCE3E 697.value 0x9180,0x9042,0x9204,0x93C6,0x9688,0x974A,0x950C,0x94CE 698.value 0x9F90,0x9E52,0x9C14,0x9DD6,0x9898,0x995A,0x9B1C,0x9ADE 699.value 0x8DA0,0x8C62,0x8E24,0x8FE6,0x8AA8,0x8B6A,0x892C,0x88EE 700.value 0x83B0,0x8272,0x8034,0x81F6,0x84B8,0x857A,0x873C,0x86FE 701.value 0xA9C0,0xA802,0xAA44,0xAB86,0xAEC8,0xAF0A,0xAD4C,0xAC8E 702.value 0xA7D0,0xA612,0xA454,0xA596,0xA0D8,0xA11A,0xA35C,0xA29E 703.value 0xB5E0,0xB422,0xB664,0xB7A6,0xB2E8,0xB32A,0xB16C,0xB0AE 704.value 0xBBF0,0xBA32,0xB874,0xB9B6,0xBCF8,0xBD3A,0xBF7C,0xBEBE 705 706.byte 71,72,65,83,72,32,102,111,114,32,120,56,54,95,54,52,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0 707.align 64 708 709/* Mark the stack non-executable. */ 710#if defined(__linux__) && defined(__ELF__) 711.section .note.GNU-stack,"",%progbits 712#endif 713 714#endif /* defined(__x86_64__) && defined(HAVE_AVX) && defined(HAVE_AES) ... */ 715