xref: /freebsd-src/sys/contrib/device-tree/src/riscv/microchip/mpfs-polarberry.dts (revision d5b0e70f7e04d971691517ce1304d86a1e367e2e)

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2022 Microchip Technology Inc */

/dts-v1/;

#include "mpfs.dtsi"
#include "mpfs-polarberry-fabric.dtsi"

/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ	1000000

/ {
	model = "Sundance PolarBerry";
	compatible = "sundance,polarberry", "microchip,mpfs";

	aliases {
		ethernet0 = &mac1;
		serial0 = &mmuart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	cpus {
		timebase-frequency = <MTIMER_FREQ>;
	};

	ddrc_cache_lo: memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x2e000000>;
	};

	ddrc_cache_hi: memory@1000000000 {
		device_type = "memory";
		reg = <0x10 0x00000000 0x0 0xC0000000>;
	};
};

/*
 * phy0 is connected to mac0, but the port itself is on the (optional) carrier
 * board.
 */
&mac0 {
	phy-mode = "sgmii";
	phy-handle = <&phy0>;
	status = "disabled";
};

&mac1 {
	phy-mode = "sgmii";
	phy-handle = <&phy1>;
	status = "okay";

	phy1: ethernet-phy@5 {
		reg = <5>;
		ti,fifo-depth = <0x01>;
	};

	phy0: ethernet-phy@4 {
		reg = <4>;
		ti,fifo-depth = <0x01>;
	};
};

&mbox {
	status = "okay";
};

&mmc {
	bus-width = <4>;
	disable-wp;
	cap-sd-highspeed;
	cap-mmc-highspeed;
	card-detect-delay = <200>;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	status = "okay";
};

&mmuart0 {
	status = "okay";
};

&refclk {
	clock-frequency = <125000000>;
};

&rtc {
	status = "okay";
};

&syscontroller {
	status = "okay";
};