1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * Device Tree Source for the GR-Peach audiocamera shield expansion board 4*f126890aSEmmanuel Vadot * 5*f126890aSEmmanuel Vadot * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org> 6*f126890aSEmmanuel Vadot */ 7*f126890aSEmmanuel Vadot 8*f126890aSEmmanuel Vadot#include "r7s72100.dtsi" 9*f126890aSEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 10*f126890aSEmmanuel Vadot#include <dt-bindings/pinctrl/r7s72100-pinctrl.h> 11*f126890aSEmmanuel Vadot 12*f126890aSEmmanuel Vadot/ { 13*f126890aSEmmanuel Vadot /* On-board camera clock. */ 14*f126890aSEmmanuel Vadot camera_clk: camera_clk { 15*f126890aSEmmanuel Vadot compatible = "fixed-clock"; 16*f126890aSEmmanuel Vadot #clock-cells = <0>; 17*f126890aSEmmanuel Vadot clock-frequency = <27000000>; 18*f126890aSEmmanuel Vadot }; 19*f126890aSEmmanuel Vadot}; 20*f126890aSEmmanuel Vadot 21*f126890aSEmmanuel Vadot&pinctrl { 22*f126890aSEmmanuel Vadot i2c1_pins: i2c1 { 23*f126890aSEmmanuel Vadot /* P1_2 as SCL; P1_3 as SDA */ 24*f126890aSEmmanuel Vadot pinmux = <RZA1_PINMUX(1, 2, 1)>, <RZA1_PINMUX(1, 3, 1)>; 25*f126890aSEmmanuel Vadot }; 26*f126890aSEmmanuel Vadot 27*f126890aSEmmanuel Vadot vio_pins: vio { 28*f126890aSEmmanuel Vadot /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */ 29*f126890aSEmmanuel Vadot pinmux = <RZA1_PINMUX(1, 0, 5)>, /* VIO_VD */ 30*f126890aSEmmanuel Vadot <RZA1_PINMUX(1, 1, 5)>, /* VIO_HD */ 31*f126890aSEmmanuel Vadot <RZA1_PINMUX(2, 0, 7)>, /* VIO_D0 */ 32*f126890aSEmmanuel Vadot <RZA1_PINMUX(2, 1, 7)>, /* VIO_D1 */ 33*f126890aSEmmanuel Vadot <RZA1_PINMUX(2, 2, 7)>, /* VIO_D2 */ 34*f126890aSEmmanuel Vadot <RZA1_PINMUX(2, 3, 7)>, /* VIO_D3 */ 35*f126890aSEmmanuel Vadot <RZA1_PINMUX(2, 4, 7)>, /* VIO_D4 */ 36*f126890aSEmmanuel Vadot <RZA1_PINMUX(2, 5, 7)>, /* VIO_D5 */ 37*f126890aSEmmanuel Vadot <RZA1_PINMUX(2, 6, 7)>, /* VIO_D6 */ 38*f126890aSEmmanuel Vadot <RZA1_PINMUX(2, 7, 7)>, /* VIO_D7 */ 39*f126890aSEmmanuel Vadot <RZA1_PINMUX(10, 0, 6)>; /* VIO_CLK */ 40*f126890aSEmmanuel Vadot }; 41*f126890aSEmmanuel Vadot}; 42*f126890aSEmmanuel Vadot 43*f126890aSEmmanuel Vadot&i2c1 { 44*f126890aSEmmanuel Vadot pinctrl-names = "default"; 45*f126890aSEmmanuel Vadot pinctrl-0 = <&i2c1_pins>; 46*f126890aSEmmanuel Vadot 47*f126890aSEmmanuel Vadot status = "okay"; 48*f126890aSEmmanuel Vadot clock-frequency = <100000>; 49*f126890aSEmmanuel Vadot 50*f126890aSEmmanuel Vadot camera@48 { 51*f126890aSEmmanuel Vadot compatible = "aptina,mt9v111"; 52*f126890aSEmmanuel Vadot reg = <0x48>; 53*f126890aSEmmanuel Vadot 54*f126890aSEmmanuel Vadot clocks = <&camera_clk>; 55*f126890aSEmmanuel Vadot 56*f126890aSEmmanuel Vadot port { 57*f126890aSEmmanuel Vadot mt9v111_out: endpoint { 58*f126890aSEmmanuel Vadot remote-endpoint = <&ceu_in>; 59*f126890aSEmmanuel Vadot }; 60*f126890aSEmmanuel Vadot }; 61*f126890aSEmmanuel Vadot }; 62*f126890aSEmmanuel Vadot}; 63*f126890aSEmmanuel Vadot 64*f126890aSEmmanuel Vadot&ceu { 65*f126890aSEmmanuel Vadot pinctrl-names = "default"; 66*f126890aSEmmanuel Vadot pinctrl-0 = <&vio_pins>; 67*f126890aSEmmanuel Vadot 68*f126890aSEmmanuel Vadot status = "okay"; 69*f126890aSEmmanuel Vadot 70*f126890aSEmmanuel Vadot port { 71*f126890aSEmmanuel Vadot ceu_in: endpoint { 72*f126890aSEmmanuel Vadot remote-endpoint = <&mt9v111_out>; 73*f126890aSEmmanuel Vadot }; 74*f126890aSEmmanuel Vadot }; 75*f126890aSEmmanuel Vadot}; 76