1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2*f126890aSEmmanuel Vadot// 3*f126890aSEmmanuel Vadot// Copyright 2019 NXP 4*f126890aSEmmanuel Vadot 5*f126890aSEmmanuel Vadot/dts-v1/; 6*f126890aSEmmanuel Vadot 7*f126890aSEmmanuel Vadot#include "imx7ulp.dtsi" 8*f126890aSEmmanuel Vadot#include <dt-bindings/input/input.h> 9*f126890aSEmmanuel Vadot 10*f126890aSEmmanuel Vadot/ { 11*f126890aSEmmanuel Vadot model = "Embedded Artists i.MX7ULP COM"; 12*f126890aSEmmanuel Vadot compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; 13*f126890aSEmmanuel Vadot 14*f126890aSEmmanuel Vadot chosen { 15*f126890aSEmmanuel Vadot stdout-path = &lpuart4; 16*f126890aSEmmanuel Vadot }; 17*f126890aSEmmanuel Vadot 18*f126890aSEmmanuel Vadot memory@60000000 { 19*f126890aSEmmanuel Vadot device_type = "memory"; 20*f126890aSEmmanuel Vadot reg = <0x60000000 0x4000000>; 21*f126890aSEmmanuel Vadot }; 22*f126890aSEmmanuel Vadot}; 23*f126890aSEmmanuel Vadot 24*f126890aSEmmanuel Vadot&lpuart4 { 25*f126890aSEmmanuel Vadot pinctrl-names = "default"; 26*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_lpuart4>; 27*f126890aSEmmanuel Vadot status = "okay"; 28*f126890aSEmmanuel Vadot}; 29*f126890aSEmmanuel Vadot 30*f126890aSEmmanuel Vadot&usbotg1 { 31*f126890aSEmmanuel Vadot pinctrl-names = "default"; 32*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_usbotg1_id>; 33*f126890aSEmmanuel Vadot srp-disable; 34*f126890aSEmmanuel Vadot hnp-disable; 35*f126890aSEmmanuel Vadot adp-disable; 36*f126890aSEmmanuel Vadot status = "okay"; 37*f126890aSEmmanuel Vadot}; 38*f126890aSEmmanuel Vadot 39*f126890aSEmmanuel Vadot&usdhc0 { 40*f126890aSEmmanuel Vadot assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; 41*f126890aSEmmanuel Vadot assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; 42*f126890aSEmmanuel Vadot pinctrl-names = "default"; 43*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc0>; 44*f126890aSEmmanuel Vadot non-removable; 45*f126890aSEmmanuel Vadot bus-width = <8>; 46*f126890aSEmmanuel Vadot no-1-8-v; 47*f126890aSEmmanuel Vadot status = "okay"; 48*f126890aSEmmanuel Vadot}; 49*f126890aSEmmanuel Vadot 50*f126890aSEmmanuel Vadot&iomuxc1 { 51*f126890aSEmmanuel Vadot pinctrl_lpuart4: lpuart4grp { 52*f126890aSEmmanuel Vadot fsl,pins = < 53*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 54*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 55*f126890aSEmmanuel Vadot >; 56*f126890aSEmmanuel Vadot }; 57*f126890aSEmmanuel Vadot 58*f126890aSEmmanuel Vadot pinctrl_usbotg1_id: otg1idgrp { 59*f126890aSEmmanuel Vadot fsl,pins = < 60*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTC13__USB0_ID 0x10003 61*f126890aSEmmanuel Vadot >; 62*f126890aSEmmanuel Vadot }; 63*f126890aSEmmanuel Vadot 64*f126890aSEmmanuel Vadot pinctrl_usdhc0: usdhc0grp { 65*f126890aSEmmanuel Vadot fsl,pins = < 66*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 67*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 68*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 69*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 70*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 71*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 72*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 73*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 74*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 75*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 76*f126890aSEmmanuel Vadot IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 77*f126890aSEmmanuel Vadot >; 78*f126890aSEmmanuel Vadot }; 79*f126890aSEmmanuel Vadot}; 80