1*f126890aSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*f126890aSEmmanuel Vadot /* 3*f126890aSEmmanuel Vadot * Copyright (C) 2016 Freescale Semiconductor, Inc. 4*f126890aSEmmanuel Vadot * Copyright (C) 2017 NXP 5*f126890aSEmmanuel Vadot */ 6*f126890aSEmmanuel Vadot 7*f126890aSEmmanuel Vadot #ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H 8*f126890aSEmmanuel Vadot #define __DTS_IMX6ULL_PINFUNC_SNVS_H 9*f126890aSEmmanuel Vadot /* 10*f126890aSEmmanuel Vadot * The pin function ID is a tuple of 11*f126890aSEmmanuel Vadot * <mux_reg conf_reg input_reg mux_mode input_val> 12*f126890aSEmmanuel Vadot */ 13*f126890aSEmmanuel Vadot #define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 14*f126890aSEmmanuel Vadot #define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 15*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 16*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 17*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 18*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 19*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 20*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 21*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 22*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 23*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 24*f126890aSEmmanuel Vadot #define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 25*f126890aSEmmanuel Vadot 26*f126890aSEmmanuel Vadot #endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ 27