xref: /freebsd-src/sys/contrib/device-tree/src/arm/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi (revision f126890ac5386406dadf7c4cfa9566cbb56537c5)
1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 OR MIT
2*f126890aSEmmanuel Vadot//
3*f126890aSEmmanuel Vadot// Copyright 2019 Armadeus Systems <support@armadeus.com>
4*f126890aSEmmanuel Vadot
5*f126890aSEmmanuel Vadot/ {
6*f126890aSEmmanuel Vadot	memory@80000000 {
7*f126890aSEmmanuel Vadot		device_type = "memory";
8*f126890aSEmmanuel Vadot		reg = <0x80000000 0>; /* will be filled by U-Boot */
9*f126890aSEmmanuel Vadot	};
10*f126890aSEmmanuel Vadot
11*f126890aSEmmanuel Vadot	reg_3v3: regulator-3v3 {
12*f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
13*f126890aSEmmanuel Vadot		regulator-name = "3V3";
14*f126890aSEmmanuel Vadot		regulator-min-microvolt = <3300000>;
15*f126890aSEmmanuel Vadot		regulator-max-microvolt = <3300000>;
16*f126890aSEmmanuel Vadot	};
17*f126890aSEmmanuel Vadot
18*f126890aSEmmanuel Vadot	usdhc3_pwrseq: usdhc3-pwrseq {
19*f126890aSEmmanuel Vadot		compatible = "mmc-pwrseq-simple";
20*f126890aSEmmanuel Vadot		reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
21*f126890aSEmmanuel Vadot	};
22*f126890aSEmmanuel Vadot};
23*f126890aSEmmanuel Vadot
24*f126890aSEmmanuel Vadot&fec1 {
25*f126890aSEmmanuel Vadot	pinctrl-names = "default";
26*f126890aSEmmanuel Vadot	pinctrl-0 = <&pinctrl_enet1>;
27*f126890aSEmmanuel Vadot	phy-mode = "rmii";
28*f126890aSEmmanuel Vadot	phy-reset-duration = <1>;
29*f126890aSEmmanuel Vadot	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
30*f126890aSEmmanuel Vadot	phy-handle = <&ethphy1>;
31*f126890aSEmmanuel Vadot	phy-supply = <&reg_3v3>;
32*f126890aSEmmanuel Vadot	status = "okay";
33*f126890aSEmmanuel Vadot
34*f126890aSEmmanuel Vadot	mdio: mdio {
35*f126890aSEmmanuel Vadot		#address-cells = <1>;
36*f126890aSEmmanuel Vadot		#size-cells = <0>;
37*f126890aSEmmanuel Vadot
38*f126890aSEmmanuel Vadot		ethphy1: ethernet-phy@1 {
39*f126890aSEmmanuel Vadot			compatible = "ethernet-phy-ieee802.3-c22";
40*f126890aSEmmanuel Vadot			reg = <1>;
41*f126890aSEmmanuel Vadot			interrupt-parent = <&gpio4>;
42*f126890aSEmmanuel Vadot			interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
43*f126890aSEmmanuel Vadot			status = "okay";
44*f126890aSEmmanuel Vadot		};
45*f126890aSEmmanuel Vadot	};
46*f126890aSEmmanuel Vadot};
47*f126890aSEmmanuel Vadot
48*f126890aSEmmanuel Vadot/* Bluetooth */
49*f126890aSEmmanuel Vadot&uart8 {
50*f126890aSEmmanuel Vadot	pinctrl-names = "default";
51*f126890aSEmmanuel Vadot	pinctrl-0 = <&pinctrl_uart8>;
52*f126890aSEmmanuel Vadot	uart-has-rtscts;
53*f126890aSEmmanuel Vadot	status = "okay";
54*f126890aSEmmanuel Vadot};
55*f126890aSEmmanuel Vadot
56*f126890aSEmmanuel Vadot/* eMMC */
57*f126890aSEmmanuel Vadot&usdhc1 {
58*f126890aSEmmanuel Vadot	pinctrl-names = "default";
59*f126890aSEmmanuel Vadot	pinctrl-0 = <&pinctrl_usdhc1>;
60*f126890aSEmmanuel Vadot	bus-width = <8>;
61*f126890aSEmmanuel Vadot	no-1-8-v;
62*f126890aSEmmanuel Vadot	non-removable;
63*f126890aSEmmanuel Vadot	status = "okay";
64*f126890aSEmmanuel Vadot};
65*f126890aSEmmanuel Vadot
66*f126890aSEmmanuel Vadot/* WiFi */
67*f126890aSEmmanuel Vadot&usdhc2 {
68*f126890aSEmmanuel Vadot	pinctrl-names = "default";
69*f126890aSEmmanuel Vadot	pinctrl-0 = <&pinctrl_usdhc2>;
70*f126890aSEmmanuel Vadot	bus-width = <4>;
71*f126890aSEmmanuel Vadot	no-1-8-v;
72*f126890aSEmmanuel Vadot	non-removable;
73*f126890aSEmmanuel Vadot	mmc-pwrseq = <&usdhc3_pwrseq>;
74*f126890aSEmmanuel Vadot	status = "okay";
75*f126890aSEmmanuel Vadot
76*f126890aSEmmanuel Vadot	#address-cells = <1>;
77*f126890aSEmmanuel Vadot	#size-cells = <0>;
78*f126890aSEmmanuel Vadot
79*f126890aSEmmanuel Vadot	brcmf: wifi@1 {
80*f126890aSEmmanuel Vadot		compatible = "brcm,bcm4329-fmac";
81*f126890aSEmmanuel Vadot		reg = <1>;
82*f126890aSEmmanuel Vadot		interrupt-parent = <&gpio2>;
83*f126890aSEmmanuel Vadot		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
84*f126890aSEmmanuel Vadot		interrupt-names = "host-wake";
85*f126890aSEmmanuel Vadot	};
86*f126890aSEmmanuel Vadot};
87*f126890aSEmmanuel Vadot
88*f126890aSEmmanuel Vadot&iomuxc {
89*f126890aSEmmanuel Vadot	pinctrl_enet1: enet1grp {
90*f126890aSEmmanuel Vadot		fsl,pins = <
91*f126890aSEmmanuel Vadot			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
92*f126890aSEmmanuel Vadot			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
93*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x130b0
94*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x130b0
95*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x130b0
96*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x130b0
97*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
98*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
99*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
100*f126890aSEmmanuel Vadot			/* INT# */
101*f126890aSEmmanuel Vadot			MX6UL_PAD_NAND_DQS__GPIO4_IO16		0x1b0b0
102*f126890aSEmmanuel Vadot			/* RST# */
103*f126890aSEmmanuel Vadot			MX6UL_PAD_NAND_DATA00__GPIO4_IO02	0x130b0
104*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
105*f126890aSEmmanuel Vadot		>;
106*f126890aSEmmanuel Vadot	};
107*f126890aSEmmanuel Vadot
108*f126890aSEmmanuel Vadot	pinctrl_uart8: uart8grp {
109*f126890aSEmmanuel Vadot		fsl,pins = <
110*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX	0x1b0b0
111*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX	0x1b0b0
112*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS	0x1b0b0
113*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS	0x1b0b0
114*f126890aSEmmanuel Vadot			/* BT_REG_ON */
115*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10	0x130b0
116*f126890aSEmmanuel Vadot		>;
117*f126890aSEmmanuel Vadot	};
118*f126890aSEmmanuel Vadot
119*f126890aSEmmanuel Vadot	pinctrl_usdhc1: usdhc1grp {
120*f126890aSEmmanuel Vadot		fsl,pins = <
121*f126890aSEmmanuel Vadot			MX6UL_PAD_SD1_CMD__USDHC1_CMD		0x17059
122*f126890aSEmmanuel Vadot			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10059
123*f126890aSEmmanuel Vadot			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0	0x17059
124*f126890aSEmmanuel Vadot			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1	0x17059
125*f126890aSEmmanuel Vadot			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2	0x17059
126*f126890aSEmmanuel Vadot			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3	0x17059
127*f126890aSEmmanuel Vadot			MX6UL_PAD_NAND_READY_B__USDHC1_DATA4	0x17059
128*f126890aSEmmanuel Vadot			MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5	0x17059
129*f126890aSEmmanuel Vadot			MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6	0x17059
130*f126890aSEmmanuel Vadot			MX6UL_PAD_NAND_CLE__USDHC1_DATA7	0x17059
131*f126890aSEmmanuel Vadot		>;
132*f126890aSEmmanuel Vadot	};
133*f126890aSEmmanuel Vadot
134*f126890aSEmmanuel Vadot	pinctrl_usdhc2: usdhc2grp {
135*f126890aSEmmanuel Vadot		fsl,pins = <
136*f126890aSEmmanuel Vadot			MX6UL_PAD_LCD_DATA18__USDHC2_CMD	0x1b0b0
137*f126890aSEmmanuel Vadot			MX6UL_PAD_LCD_DATA19__USDHC2_CLK	0x100b0
138*f126890aSEmmanuel Vadot			MX6UL_PAD_LCD_DATA20__USDHC2_DATA0	0x1b0b0
139*f126890aSEmmanuel Vadot			MX6UL_PAD_LCD_DATA21__USDHC2_DATA1	0x1b0b0
140*f126890aSEmmanuel Vadot			MX6UL_PAD_LCD_DATA22__USDHC2_DATA2	0x1b0b0
141*f126890aSEmmanuel Vadot			MX6UL_PAD_LCD_DATA23__USDHC2_DATA3	0x1b0b0
142*f126890aSEmmanuel Vadot			/* WL_REG_ON */
143*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09	0x130b0
144*f126890aSEmmanuel Vadot			/* WL_IRQ */
145*f126890aSEmmanuel Vadot			MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08	0x1b0b0
146*f126890aSEmmanuel Vadot		>;
147*f126890aSEmmanuel Vadot	};
148*f126890aSEmmanuel Vadot};
149