1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*f126890aSEmmanuel Vadot// 3*f126890aSEmmanuel Vadot// Copyright 2015 Armadeus Systems <support@armadeus.com> 4*f126890aSEmmanuel Vadot 5*f126890aSEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 6*f126890aSEmmanuel Vadot#include <dt-bindings/interrupt-controller/irq.h> 7*f126890aSEmmanuel Vadot 8*f126890aSEmmanuel Vadot/ { 9*f126890aSEmmanuel Vadot reg_1p8v: regulator-1p8v { 10*f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 11*f126890aSEmmanuel Vadot regulator-name = "1P8V"; 12*f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 13*f126890aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 14*f126890aSEmmanuel Vadot regulator-always-on; 15*f126890aSEmmanuel Vadot vin-supply = <®_3p3v>; 16*f126890aSEmmanuel Vadot }; 17*f126890aSEmmanuel Vadot 18*f126890aSEmmanuel Vadot usdhc1_pwrseq: usdhc1-pwrseq { 19*f126890aSEmmanuel Vadot compatible = "mmc-pwrseq-simple"; 20*f126890aSEmmanuel Vadot reset-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; 21*f126890aSEmmanuel Vadot post-power-on-delay-ms = <15>; 22*f126890aSEmmanuel Vadot power-off-delay-us = <70>; 23*f126890aSEmmanuel Vadot }; 24*f126890aSEmmanuel Vadot}; 25*f126890aSEmmanuel Vadot 26*f126890aSEmmanuel Vadot&fec { 27*f126890aSEmmanuel Vadot pinctrl-names = "default"; 28*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_enet>; 29*f126890aSEmmanuel Vadot phy-mode = "rgmii-id"; 30*f126890aSEmmanuel Vadot phy-reset-duration = <10>; 31*f126890aSEmmanuel Vadot phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; 32*f126890aSEmmanuel Vadot phy-handle = <ðphy1>; 33*f126890aSEmmanuel Vadot status = "okay"; 34*f126890aSEmmanuel Vadot 35*f126890aSEmmanuel Vadot mdio { 36*f126890aSEmmanuel Vadot #address-cells = <1>; 37*f126890aSEmmanuel Vadot #size-cells = <0>; 38*f126890aSEmmanuel Vadot 39*f126890aSEmmanuel Vadot ethphy1: ethernet-phy@1 { 40*f126890aSEmmanuel Vadot compatible = "ethernet-phy-ieee802.3-c22"; 41*f126890aSEmmanuel Vadot reg = <1>; 42*f126890aSEmmanuel Vadot interrupt-parent = <&gpio1>; 43*f126890aSEmmanuel Vadot interrupts = <28 IRQ_TYPE_LEVEL_LOW>; 44*f126890aSEmmanuel Vadot status = "okay"; 45*f126890aSEmmanuel Vadot }; 46*f126890aSEmmanuel Vadot }; 47*f126890aSEmmanuel Vadot}; 48*f126890aSEmmanuel Vadot 49*f126890aSEmmanuel Vadot/* Bluetooth */ 50*f126890aSEmmanuel Vadot&uart2 { 51*f126890aSEmmanuel Vadot pinctrl-names = "default"; 52*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_uart2>; 53*f126890aSEmmanuel Vadot uart-has-rtscts; 54*f126890aSEmmanuel Vadot status = "okay"; 55*f126890aSEmmanuel Vadot}; 56*f126890aSEmmanuel Vadot 57*f126890aSEmmanuel Vadot/* Wi-Fi */ 58*f126890aSEmmanuel Vadot&usdhc1 { 59*f126890aSEmmanuel Vadot pinctrl-names = "default"; 60*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc1>; 61*f126890aSEmmanuel Vadot bus-width = <4>; 62*f126890aSEmmanuel Vadot mmc-pwrseq = <&usdhc1_pwrseq>; 63*f126890aSEmmanuel Vadot vmmc-supply = <®_3p3v>; 64*f126890aSEmmanuel Vadot vqmmc-supply = <®_1p8v>; 65*f126890aSEmmanuel Vadot cap-power-off-card; 66*f126890aSEmmanuel Vadot keep-power-in-suspend; 67*f126890aSEmmanuel Vadot non-removable; 68*f126890aSEmmanuel Vadot status = "okay"; 69*f126890aSEmmanuel Vadot 70*f126890aSEmmanuel Vadot #address-cells = <1>; 71*f126890aSEmmanuel Vadot #size-cells = <0>; 72*f126890aSEmmanuel Vadot wlcore: wlcore@2 { 73*f126890aSEmmanuel Vadot compatible = "ti,wl1271"; 74*f126890aSEmmanuel Vadot reg = <2>; 75*f126890aSEmmanuel Vadot interrupt-parent = <&gpio2>; 76*f126890aSEmmanuel Vadot interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 77*f126890aSEmmanuel Vadot ref-clock-frequency = <38400000>; 78*f126890aSEmmanuel Vadot tcxo-clock-frequency = <38400000>; 79*f126890aSEmmanuel Vadot }; 80*f126890aSEmmanuel Vadot}; 81*f126890aSEmmanuel Vadot 82*f126890aSEmmanuel Vadot/* eMMC */ 83*f126890aSEmmanuel Vadot&usdhc3 { 84*f126890aSEmmanuel Vadot pinctrl-names = "default"; 85*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_usdhc3>; 86*f126890aSEmmanuel Vadot bus-width = <8>; 87*f126890aSEmmanuel Vadot no-1-8-v; 88*f126890aSEmmanuel Vadot non-removable; 89*f126890aSEmmanuel Vadot status = "okay"; 90*f126890aSEmmanuel Vadot}; 91*f126890aSEmmanuel Vadot 92*f126890aSEmmanuel Vadot&iomuxc { 93*f126890aSEmmanuel Vadot pinctrl_enet: enetgrp { 94*f126890aSEmmanuel Vadot fsl,pins = < 95*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 96*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 97*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 98*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0 99*f126890aSEmmanuel Vadot MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0 100*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 101*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 102*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 103*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 104*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 105*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 106*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030 107*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 108*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 109*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030 110*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030 111*f126890aSEmmanuel Vadot MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 112*f126890aSEmmanuel Vadot >; 113*f126890aSEmmanuel Vadot }; 114*f126890aSEmmanuel Vadot 115*f126890aSEmmanuel Vadot pinctrl_uart2: uart2grp { 116*f126890aSEmmanuel Vadot fsl,pins = < 117*f126890aSEmmanuel Vadot MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0 118*f126890aSEmmanuel Vadot MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0 119*f126890aSEmmanuel Vadot MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0 120*f126890aSEmmanuel Vadot MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0 121*f126890aSEmmanuel Vadot MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */ 122*f126890aSEmmanuel Vadot >; 123*f126890aSEmmanuel Vadot }; 124*f126890aSEmmanuel Vadot 125*f126890aSEmmanuel Vadot pinctrl_usdhc1: usdhc1grp { 126*f126890aSEmmanuel Vadot fsl,pins = < 127*f126890aSEmmanuel Vadot MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 128*f126890aSEmmanuel Vadot MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 129*f126890aSEmmanuel Vadot MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 130*f126890aSEmmanuel Vadot MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 131*f126890aSEmmanuel Vadot MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 132*f126890aSEmmanuel Vadot MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 133*f126890aSEmmanuel Vadot MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x130b0 /* WL_EN */ 134*f126890aSEmmanuel Vadot MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x130b0 /* WL_IRQ */ 135*f126890aSEmmanuel Vadot >; 136*f126890aSEmmanuel Vadot }; 137*f126890aSEmmanuel Vadot 138*f126890aSEmmanuel Vadot pinctrl_usdhc3: usdhc3grp { 139*f126890aSEmmanuel Vadot fsl,pins = < 140*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 141*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 142*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 143*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 144*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 145*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 146*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 147*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 148*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 149*f126890aSEmmanuel Vadot MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 150*f126890aSEmmanuel Vadot >; 151*f126890aSEmmanuel Vadot }; 152*f126890aSEmmanuel Vadot}; 153