1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0-or-later 2*f126890aSEmmanuel Vadot/* 3*f126890aSEmmanuel Vadot * Copyright 2012 Armadeus Systems - <support@armadeus.com> 4*f126890aSEmmanuel Vadot * Copyright 2012 Laurent Cans <laurent.cans@gmail.com> 5*f126890aSEmmanuel Vadot * 6*f126890aSEmmanuel Vadot * Based on mx51-babbage.dts 7*f126890aSEmmanuel Vadot * Copyright 2011 Freescale Semiconductor, Inc. 8*f126890aSEmmanuel Vadot * Copyright 2011 Linaro Ltd. 9*f126890aSEmmanuel Vadot */ 10*f126890aSEmmanuel Vadot 11*f126890aSEmmanuel Vadot/dts-v1/; 12*f126890aSEmmanuel Vadot#include "imx51.dtsi" 13*f126890aSEmmanuel Vadot 14*f126890aSEmmanuel Vadot/ { 15*f126890aSEmmanuel Vadot model = "Armadeus Systems APF51 module"; 16*f126890aSEmmanuel Vadot compatible = "armadeus,imx51-apf51", "fsl,imx51"; 17*f126890aSEmmanuel Vadot 18*f126890aSEmmanuel Vadot memory@90000000 { 19*f126890aSEmmanuel Vadot device_type = "memory"; 20*f126890aSEmmanuel Vadot reg = <0x90000000 0x20000000>; 21*f126890aSEmmanuel Vadot }; 22*f126890aSEmmanuel Vadot 23*f126890aSEmmanuel Vadot clocks { 24*f126890aSEmmanuel Vadot osc { 25*f126890aSEmmanuel Vadot clock-frequency = <33554432>; 26*f126890aSEmmanuel Vadot }; 27*f126890aSEmmanuel Vadot }; 28*f126890aSEmmanuel Vadot}; 29*f126890aSEmmanuel Vadot 30*f126890aSEmmanuel Vadot&fec { 31*f126890aSEmmanuel Vadot pinctrl-names = "default"; 32*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_fec>; 33*f126890aSEmmanuel Vadot phy-mode = "mii"; 34*f126890aSEmmanuel Vadot phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 35*f126890aSEmmanuel Vadot phy-reset-duration = <1>; 36*f126890aSEmmanuel Vadot status = "okay"; 37*f126890aSEmmanuel Vadot}; 38*f126890aSEmmanuel Vadot 39*f126890aSEmmanuel Vadot&iomuxc { 40*f126890aSEmmanuel Vadot imx51-apf51 { 41*f126890aSEmmanuel Vadot pinctrl_fec: fecgrp { 42*f126890aSEmmanuel Vadot fsl,pins = < 43*f126890aSEmmanuel Vadot MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000 44*f126890aSEmmanuel Vadot MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000 45*f126890aSEmmanuel Vadot MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000 46*f126890aSEmmanuel Vadot MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000 47*f126890aSEmmanuel Vadot MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000 48*f126890aSEmmanuel Vadot MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000 49*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000 50*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000 51*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000 52*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000 53*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000 54*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000 55*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000 56*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000 57*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000 58*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000 59*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000 60*f126890aSEmmanuel Vadot MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000 61*f126890aSEmmanuel Vadot >; 62*f126890aSEmmanuel Vadot }; 63*f126890aSEmmanuel Vadot 64*f126890aSEmmanuel Vadot pinctrl_uart3: uart3grp { 65*f126890aSEmmanuel Vadot fsl,pins = < 66*f126890aSEmmanuel Vadot MX51_PAD_UART3_RXD__UART3_RXD 0x1c5 67*f126890aSEmmanuel Vadot MX51_PAD_UART3_TXD__UART3_TXD 0x1c5 68*f126890aSEmmanuel Vadot >; 69*f126890aSEmmanuel Vadot }; 70*f126890aSEmmanuel Vadot }; 71*f126890aSEmmanuel Vadot}; 72*f126890aSEmmanuel Vadot 73*f126890aSEmmanuel Vadot&nfc { 74*f126890aSEmmanuel Vadot nand-bus-width = <8>; 75*f126890aSEmmanuel Vadot nand-ecc-mode = "hw"; 76*f126890aSEmmanuel Vadot nand-on-flash-bbt; 77*f126890aSEmmanuel Vadot status = "okay"; 78*f126890aSEmmanuel Vadot}; 79*f126890aSEmmanuel Vadot 80*f126890aSEmmanuel Vadot&uart3 { 81*f126890aSEmmanuel Vadot pinctrl-names = "default"; 82*f126890aSEmmanuel Vadot pinctrl-0 = <&pinctrl_uart3>; 83*f126890aSEmmanuel Vadot status = "okay"; 84*f126890aSEmmanuel Vadot}; 85