xref: /freebsd-src/sys/contrib/device-tree/src/arm/nvidia/tegra30-asus-transformer-common.dtsi (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145)
1f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0
2f126890aSEmmanuel Vadot
3f126890aSEmmanuel Vadot#include <dt-bindings/input/gpio-keys.h>
4f126890aSEmmanuel Vadot#include <dt-bindings/input/input.h>
5f126890aSEmmanuel Vadot#include <dt-bindings/thermal/thermal.h>
6f126890aSEmmanuel Vadot
7f126890aSEmmanuel Vadot#include "tegra30.dtsi"
8f126890aSEmmanuel Vadot#include "tegra30-cpu-opp.dtsi"
9f126890aSEmmanuel Vadot#include "tegra30-cpu-opp-microvolt.dtsi"
10f126890aSEmmanuel Vadot
11f126890aSEmmanuel Vadot/ {
12f126890aSEmmanuel Vadot	chassis-type = "convertible";
13f126890aSEmmanuel Vadot
14f126890aSEmmanuel Vadot	aliases {
15f126890aSEmmanuel Vadot		mmc0 = "/mmc@78000600"; /* eMMC */
16f126890aSEmmanuel Vadot		mmc1 = "/mmc@78000000"; /* uSD slot */
17f126890aSEmmanuel Vadot		mmc2 = "/mmc@78000400"; /* WiFi */
18f126890aSEmmanuel Vadot
19f126890aSEmmanuel Vadot		rtc0 = &pmic;
20f126890aSEmmanuel Vadot		rtc1 = "/rtc@7000e000";
21f126890aSEmmanuel Vadot
22f126890aSEmmanuel Vadot		display0 = &lcd;
23f126890aSEmmanuel Vadot		display1 = &hdmi;
24f126890aSEmmanuel Vadot
25f126890aSEmmanuel Vadot		serial1 = &uartc; /* Bluetooth */
26f126890aSEmmanuel Vadot		serial2 = &uartb; /* GPS */
27f126890aSEmmanuel Vadot	};
28f126890aSEmmanuel Vadot
29f126890aSEmmanuel Vadot	/*
30f126890aSEmmanuel Vadot	 * The decompressor and also some bootloaders rely on a
31f126890aSEmmanuel Vadot	 * pre-existing /chosen node to be available to insert the
32f126890aSEmmanuel Vadot	 * command line and merge other ATAGS info.
33f126890aSEmmanuel Vadot	 */
34f126890aSEmmanuel Vadot	chosen {};
35f126890aSEmmanuel Vadot
36f126890aSEmmanuel Vadot	firmware {
37f126890aSEmmanuel Vadot		trusted-foundations {
38f126890aSEmmanuel Vadot			compatible = "tlm,trusted-foundations";
39f126890aSEmmanuel Vadot			tlm,version-major = <2>;
40f126890aSEmmanuel Vadot			tlm,version-minor = <8>;
41f126890aSEmmanuel Vadot		};
42f126890aSEmmanuel Vadot	};
43f126890aSEmmanuel Vadot
44f126890aSEmmanuel Vadot	memory@80000000 {
45f126890aSEmmanuel Vadot		reg = <0x80000000 0x40000000>;
46f126890aSEmmanuel Vadot	};
47f126890aSEmmanuel Vadot
48f126890aSEmmanuel Vadot	reserved-memory {
49f126890aSEmmanuel Vadot		#address-cells = <1>;
50f126890aSEmmanuel Vadot		#size-cells = <1>;
51f126890aSEmmanuel Vadot		ranges;
52f126890aSEmmanuel Vadot
53f126890aSEmmanuel Vadot		linux,cma@80000000 {
54f126890aSEmmanuel Vadot			compatible = "shared-dma-pool";
55f126890aSEmmanuel Vadot			alloc-ranges = <0x80000000 0x30000000>;
56f126890aSEmmanuel Vadot			size = <0x10000000>;		/* 256MiB */
57f126890aSEmmanuel Vadot			linux,cma-default;
58f126890aSEmmanuel Vadot			reusable;
59f126890aSEmmanuel Vadot		};
60f126890aSEmmanuel Vadot
61f126890aSEmmanuel Vadot		ramoops@beb00000 {
62f126890aSEmmanuel Vadot			compatible = "ramoops";
63f126890aSEmmanuel Vadot			reg = <0xbeb00000 0x10000>;	/* 64kB */
64f126890aSEmmanuel Vadot			console-size = <0x8000>;	/* 32kB */
65f126890aSEmmanuel Vadot			record-size = <0x400>;		/*  1kB */
66f126890aSEmmanuel Vadot			ecc-size = <16>;
67f126890aSEmmanuel Vadot		};
68f126890aSEmmanuel Vadot
69f126890aSEmmanuel Vadot		trustzone@bfe00000 {
70f126890aSEmmanuel Vadot			reg = <0xbfe00000 0x200000>;	/* 2MB */
71f126890aSEmmanuel Vadot			no-map;
72f126890aSEmmanuel Vadot		};
73f126890aSEmmanuel Vadot	};
74f126890aSEmmanuel Vadot
75f126890aSEmmanuel Vadot	host1x@50000000 {
76f126890aSEmmanuel Vadot		hdmi: hdmi@54280000 {
77f126890aSEmmanuel Vadot			status = "okay";
78f126890aSEmmanuel Vadot
79f126890aSEmmanuel Vadot			hdmi-supply = <&hdmi_5v0_sys>;
80f126890aSEmmanuel Vadot			pll-supply = <&vdd_1v8_vio>;
81f126890aSEmmanuel Vadot			vdd-supply = <&vdd_3v3_sys>;
82f126890aSEmmanuel Vadot
83f126890aSEmmanuel Vadot			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
84f126890aSEmmanuel Vadot			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
85f126890aSEmmanuel Vadot		};
86f126890aSEmmanuel Vadot	};
87f126890aSEmmanuel Vadot
88f126890aSEmmanuel Vadot	gpio@6000d000 {
89f126890aSEmmanuel Vadot		init-lpm-in-hog {
90f126890aSEmmanuel Vadot			gpio-hog;
91f126890aSEmmanuel Vadot			gpios = <TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>,
92f126890aSEmmanuel Vadot				<TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
93f126890aSEmmanuel Vadot			input;
94f126890aSEmmanuel Vadot		};
95f126890aSEmmanuel Vadot
96f126890aSEmmanuel Vadot		init-lpm-out-hog {
97f126890aSEmmanuel Vadot			gpio-hog;
98f126890aSEmmanuel Vadot			gpios = <TEGRA_GPIO(K, 7) GPIO_ACTIVE_HIGH>,
99f126890aSEmmanuel Vadot				<TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
100f126890aSEmmanuel Vadot			output-low;
101f126890aSEmmanuel Vadot		};
102f126890aSEmmanuel Vadot
103f126890aSEmmanuel Vadot		usb-charge-limit-hog {
104f126890aSEmmanuel Vadot			gpio-hog;
105f126890aSEmmanuel Vadot			gpios = <TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
106f126890aSEmmanuel Vadot			output-high;
107f126890aSEmmanuel Vadot		};
108f126890aSEmmanuel Vadot	};
109f126890aSEmmanuel Vadot
110f126890aSEmmanuel Vadot	vde@6001a000 {
111f126890aSEmmanuel Vadot		assigned-clocks = <&tegra_car TEGRA30_CLK_VDE>;
112f126890aSEmmanuel Vadot		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_P>;
113f126890aSEmmanuel Vadot		assigned-clock-rates = <408000000>;
114f126890aSEmmanuel Vadot	};
115f126890aSEmmanuel Vadot
116f126890aSEmmanuel Vadot	pinmux@70000868 {
117f126890aSEmmanuel Vadot		pinctrl-names = "default";
118f126890aSEmmanuel Vadot		pinctrl-0 = <&state_default>;
119f126890aSEmmanuel Vadot
120f126890aSEmmanuel Vadot		state_default: pinmux {
121f126890aSEmmanuel Vadot			/* SDMMC1 pinmux */
122f126890aSEmmanuel Vadot			sdmmc1_clk {
123f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc1_clk_pz0";
124f126890aSEmmanuel Vadot				nvidia,function = "sdmmc1";
125f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
127f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128f126890aSEmmanuel Vadot			};
129f126890aSEmmanuel Vadot
130f126890aSEmmanuel Vadot			sdmmc1_cmd {
131f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc1_dat3_py4",
132f126890aSEmmanuel Vadot						"sdmmc1_dat2_py5",
133f126890aSEmmanuel Vadot						"sdmmc1_dat1_py6",
134f126890aSEmmanuel Vadot						"sdmmc1_dat0_py7",
135f126890aSEmmanuel Vadot						"sdmmc1_cmd_pz1";
136f126890aSEmmanuel Vadot				nvidia,function = "sdmmc1";
137f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
138f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
139f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
140f126890aSEmmanuel Vadot			};
141f126890aSEmmanuel Vadot
142f126890aSEmmanuel Vadot			sdmmc1_cd {
143f126890aSEmmanuel Vadot				nvidia,pins = "gmi_iordy_pi5";
144f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
145f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
146f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
147f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
148f126890aSEmmanuel Vadot			};
149f126890aSEmmanuel Vadot
150f126890aSEmmanuel Vadot			sdmmc1_wp {
151f126890aSEmmanuel Vadot				nvidia,pins = "vi_d11_pt3";
152f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
153f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
154f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
155f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
156f126890aSEmmanuel Vadot			};
157f126890aSEmmanuel Vadot
158f126890aSEmmanuel Vadot			/* SDMMC2 pinmux */
159f126890aSEmmanuel Vadot			vi_d1_pd5 {
160f126890aSEmmanuel Vadot				nvidia,pins = "vi_d1_pd5",
161f126890aSEmmanuel Vadot						"vi_d2_pl0",
162f126890aSEmmanuel Vadot						"vi_d3_pl1",
163f126890aSEmmanuel Vadot						"vi_d5_pl3",
164f126890aSEmmanuel Vadot						"vi_d7_pl5";
165f126890aSEmmanuel Vadot				nvidia,function = "sdmmc2";
166f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
168f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
169f126890aSEmmanuel Vadot			};
170f126890aSEmmanuel Vadot
171f126890aSEmmanuel Vadot			vi_d8_pl6 {
172f126890aSEmmanuel Vadot				nvidia,pins = "vi_d8_pl6",
173f126890aSEmmanuel Vadot						"vi_d9_pl7";
174f126890aSEmmanuel Vadot				nvidia,function = "sdmmc2";
175f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
177f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
178f126890aSEmmanuel Vadot				nvidia,lock = <0>;
179f126890aSEmmanuel Vadot				nvidia,io-reset = <0>;
180f126890aSEmmanuel Vadot			};
181f126890aSEmmanuel Vadot
182f126890aSEmmanuel Vadot			/* SDMMC3 pinmux */
183f126890aSEmmanuel Vadot			sdmmc3_clk {
184f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc3_clk_pa6";
185f126890aSEmmanuel Vadot				nvidia,function = "sdmmc3";
186f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
187f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
188f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
189f126890aSEmmanuel Vadot			};
190f126890aSEmmanuel Vadot
191f126890aSEmmanuel Vadot			sdmmc3_cmd {
192f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc3_cmd_pa7",
193f126890aSEmmanuel Vadot						"sdmmc3_dat0_pb7",
194f126890aSEmmanuel Vadot						"sdmmc3_dat1_pb6",
195f126890aSEmmanuel Vadot						"sdmmc3_dat2_pb5",
196f126890aSEmmanuel Vadot						"sdmmc3_dat3_pb4",
197f126890aSEmmanuel Vadot						"sdmmc3_dat4_pd1",
198f126890aSEmmanuel Vadot						"sdmmc3_dat5_pd0",
199f126890aSEmmanuel Vadot						"sdmmc3_dat6_pd3",
200f126890aSEmmanuel Vadot						"sdmmc3_dat7_pd4";
201f126890aSEmmanuel Vadot				nvidia,function = "sdmmc3";
202f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
203f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
204f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
205f126890aSEmmanuel Vadot			};
206f126890aSEmmanuel Vadot
207f126890aSEmmanuel Vadot			/* SDMMC4 pinmux */
208f126890aSEmmanuel Vadot			sdmmc4_clk {
209f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc4_clk_pcc4";
210f126890aSEmmanuel Vadot				nvidia,function = "sdmmc4";
211f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
212f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
213f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
214f126890aSEmmanuel Vadot			};
215f126890aSEmmanuel Vadot
216f126890aSEmmanuel Vadot			sdmmc4_cmd {
217f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc4_cmd_pt7",
218f126890aSEmmanuel Vadot						"sdmmc4_dat0_paa0",
219f126890aSEmmanuel Vadot						"sdmmc4_dat1_paa1",
220f126890aSEmmanuel Vadot						"sdmmc4_dat2_paa2",
221f126890aSEmmanuel Vadot						"sdmmc4_dat3_paa3",
222f126890aSEmmanuel Vadot						"sdmmc4_dat4_paa4",
223f126890aSEmmanuel Vadot						"sdmmc4_dat5_paa5",
224f126890aSEmmanuel Vadot						"sdmmc4_dat6_paa6",
225f126890aSEmmanuel Vadot						"sdmmc4_dat7_paa7";
226f126890aSEmmanuel Vadot				nvidia,function = "sdmmc4";
227f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
228f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
229f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
230f126890aSEmmanuel Vadot			};
231f126890aSEmmanuel Vadot
232f126890aSEmmanuel Vadot			sdmmc4_rst_n {
233f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc4_rst_n_pcc3";
234f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
235f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
236f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
237f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
238f126890aSEmmanuel Vadot			};
239f126890aSEmmanuel Vadot
240f126890aSEmmanuel Vadot			cam_mclk {
241f126890aSEmmanuel Vadot				nvidia,pins = "cam_mclk_pcc0";
242f126890aSEmmanuel Vadot				nvidia,function = "vi_alt3";
243f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
244f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
245f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
246f126890aSEmmanuel Vadot			};
247f126890aSEmmanuel Vadot
248f126890aSEmmanuel Vadot			drive_sdmmc4 {
249f126890aSEmmanuel Vadot				nvidia,pins = "drive_gma",
250f126890aSEmmanuel Vadot						"drive_gmb",
251f126890aSEmmanuel Vadot						"drive_gmc",
252f126890aSEmmanuel Vadot						"drive_gmd";
253f126890aSEmmanuel Vadot				nvidia,pull-down-strength = <9>;
254f126890aSEmmanuel Vadot				nvidia,pull-up-strength = <9>;
255f126890aSEmmanuel Vadot				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
256f126890aSEmmanuel Vadot				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
257f126890aSEmmanuel Vadot			};
258f126890aSEmmanuel Vadot
259f126890aSEmmanuel Vadot			/* I2C pinmux */
260f126890aSEmmanuel Vadot			gen1_i2c {
261f126890aSEmmanuel Vadot				nvidia,pins = "gen1_i2c_scl_pc4",
262f126890aSEmmanuel Vadot						"gen1_i2c_sda_pc5";
263f126890aSEmmanuel Vadot				nvidia,function = "i2c1";
264f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
265f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
266f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
267f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
268f126890aSEmmanuel Vadot				nvidia,lock = <0>;
269f126890aSEmmanuel Vadot			};
270f126890aSEmmanuel Vadot
271f126890aSEmmanuel Vadot			gen2_i2c {
272f126890aSEmmanuel Vadot				nvidia,pins = "gen2_i2c_scl_pt5",
273f126890aSEmmanuel Vadot						"gen2_i2c_sda_pt6";
274f126890aSEmmanuel Vadot				nvidia,function = "i2c2";
275f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
276f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
277f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
278f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
279f126890aSEmmanuel Vadot				nvidia,lock = <0>;
280f126890aSEmmanuel Vadot			};
281f126890aSEmmanuel Vadot
282f126890aSEmmanuel Vadot			cam_i2c {
283f126890aSEmmanuel Vadot				nvidia,pins = "cam_i2c_scl_pbb1",
284f126890aSEmmanuel Vadot						"cam_i2c_sda_pbb2";
285f126890aSEmmanuel Vadot				nvidia,function = "i2c3";
286f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
287f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
288f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
289f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
290f126890aSEmmanuel Vadot				nvidia,lock = <0>;
291f126890aSEmmanuel Vadot			};
292f126890aSEmmanuel Vadot
293f126890aSEmmanuel Vadot			ddc_i2c {
294f126890aSEmmanuel Vadot				nvidia,pins = "ddc_scl_pv4",
295f126890aSEmmanuel Vadot						"ddc_sda_pv5";
296f126890aSEmmanuel Vadot				nvidia,function = "i2c4";
297f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
299f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
300f126890aSEmmanuel Vadot				nvidia,lock = <0>;
301f126890aSEmmanuel Vadot			};
302f126890aSEmmanuel Vadot
303f126890aSEmmanuel Vadot			pwr_i2c {
304f126890aSEmmanuel Vadot				nvidia,pins = "pwr_i2c_scl_pz6",
305f126890aSEmmanuel Vadot						"pwr_i2c_sda_pz7";
306f126890aSEmmanuel Vadot				nvidia,function = "i2cpwr";
307f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
309f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
310f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
311f126890aSEmmanuel Vadot				nvidia,lock = <0>;
312f126890aSEmmanuel Vadot			};
313f126890aSEmmanuel Vadot
314f126890aSEmmanuel Vadot			hotplug_i2c {
315f126890aSEmmanuel Vadot				nvidia,pins = "pu4";
316f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
317f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
318f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
319f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
320f126890aSEmmanuel Vadot			};
321f126890aSEmmanuel Vadot
322f126890aSEmmanuel Vadot			/* HDMI pinmux */
323f126890aSEmmanuel Vadot			hdmi_cec {
324f126890aSEmmanuel Vadot				nvidia,pins = "hdmi_cec_pee3";
325f126890aSEmmanuel Vadot				nvidia,function = "cec";
326f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
327f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
328f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
329f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
330f126890aSEmmanuel Vadot				nvidia,lock = <0>;
331f126890aSEmmanuel Vadot			};
332f126890aSEmmanuel Vadot
333f126890aSEmmanuel Vadot			hdmi_hpd {
334f126890aSEmmanuel Vadot				nvidia,pins = "hdmi_int_pn7";
335f126890aSEmmanuel Vadot				nvidia,function = "hdmi";
336f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
337f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
338f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
339f126890aSEmmanuel Vadot			};
340f126890aSEmmanuel Vadot
341f126890aSEmmanuel Vadot			/* UART-A */
342f126890aSEmmanuel Vadot			ulpi_data0_po1 {
343f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_data0_po1";
344f126890aSEmmanuel Vadot				nvidia,function = "uarta";
345f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
346f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
347f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
348f126890aSEmmanuel Vadot			};
349f126890aSEmmanuel Vadot
350f126890aSEmmanuel Vadot			ulpi_data1_po2 {
351f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_data1_po2";
352f126890aSEmmanuel Vadot				nvidia,function = "uarta";
353f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
354f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
355f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
356f126890aSEmmanuel Vadot			};
357f126890aSEmmanuel Vadot
358f126890aSEmmanuel Vadot			ulpi_data5_po6 {
359f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_data5_po6";
360f126890aSEmmanuel Vadot				nvidia,function = "uarta";
361f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
363f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364f126890aSEmmanuel Vadot			};
365f126890aSEmmanuel Vadot
366f126890aSEmmanuel Vadot			ulpi_data7_po0 {
367f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_data7_po0",
368f126890aSEmmanuel Vadot						"ulpi_data2_po3",
369f126890aSEmmanuel Vadot						"ulpi_data3_po4",
370f126890aSEmmanuel Vadot						"ulpi_data4_po5",
371f126890aSEmmanuel Vadot						"ulpi_data6_po7";
372f126890aSEmmanuel Vadot				nvidia,function = "uarta";
373f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
374f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
375f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
376f126890aSEmmanuel Vadot			};
377f126890aSEmmanuel Vadot
378f126890aSEmmanuel Vadot			/* UART-B */
379f126890aSEmmanuel Vadot			uartb_txd_rts {
380f126890aSEmmanuel Vadot				nvidia,pins = "uart2_txd_pc2",
381f126890aSEmmanuel Vadot						"uart2_rts_n_pj6";
382f126890aSEmmanuel Vadot				nvidia,function = "uartb";
383f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
384f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
385f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
386f126890aSEmmanuel Vadot			};
387f126890aSEmmanuel Vadot
388f126890aSEmmanuel Vadot			uartb_rxd_cts {
389f126890aSEmmanuel Vadot				nvidia,pins = "uart2_rxd_pc3",
390f126890aSEmmanuel Vadot						"uart2_cts_n_pj5";
391f126890aSEmmanuel Vadot				nvidia,function = "uartb";
392f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
394f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
395f126890aSEmmanuel Vadot			};
396f126890aSEmmanuel Vadot
397f126890aSEmmanuel Vadot			/* UART-C */
398f126890aSEmmanuel Vadot			uartc_rxd_cts {
399f126890aSEmmanuel Vadot				nvidia,pins = "uart3_cts_n_pa1",
400f126890aSEmmanuel Vadot						"uart3_rxd_pw7";
401f126890aSEmmanuel Vadot				nvidia,function = "uartc";
402f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
403f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
404f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
405f126890aSEmmanuel Vadot			};
406f126890aSEmmanuel Vadot
407f126890aSEmmanuel Vadot			uartc_txd_rts {
408f126890aSEmmanuel Vadot				nvidia,pins = "uart3_rts_n_pc0",
409f126890aSEmmanuel Vadot						"uart3_txd_pw6";
410f126890aSEmmanuel Vadot				nvidia,function = "uartc";
411f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
412f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
413f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
414f126890aSEmmanuel Vadot			};
415f126890aSEmmanuel Vadot
416f126890aSEmmanuel Vadot			/* UART-D */
417f126890aSEmmanuel Vadot			ulpi_nxt_py2 {
418f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_nxt_py2";
419f126890aSEmmanuel Vadot				nvidia,function = "uartd";
420f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
422f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423f126890aSEmmanuel Vadot			};
424f126890aSEmmanuel Vadot
425f126890aSEmmanuel Vadot			ulpi_clk_py0 {
426f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_clk_py0",
427f126890aSEmmanuel Vadot						"ulpi_dir_py1",
428f126890aSEmmanuel Vadot						"ulpi_stp_py3";
429f126890aSEmmanuel Vadot				nvidia,function = "uartd";
430f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
431f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
432f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
433f126890aSEmmanuel Vadot			};
434f126890aSEmmanuel Vadot
435f126890aSEmmanuel Vadot			/* I2S pinmux */
436f126890aSEmmanuel Vadot			dap_i2s0 {
437f126890aSEmmanuel Vadot				nvidia,pins = "dap1_fs_pn0",
438f126890aSEmmanuel Vadot						"dap1_din_pn1",
439f126890aSEmmanuel Vadot						"dap1_dout_pn2",
440f126890aSEmmanuel Vadot						"dap1_sclk_pn3";
441f126890aSEmmanuel Vadot				nvidia,function = "i2s0";
442f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
443f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
444f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
445f126890aSEmmanuel Vadot			};
446f126890aSEmmanuel Vadot
447f126890aSEmmanuel Vadot			dap_i2s1 {
448f126890aSEmmanuel Vadot				nvidia,pins = "dap2_fs_pa2",
449f126890aSEmmanuel Vadot						"dap2_sclk_pa3",
450f126890aSEmmanuel Vadot						"dap2_din_pa4",
451f126890aSEmmanuel Vadot						"dap2_dout_pa5";
452f126890aSEmmanuel Vadot				nvidia,function = "i2s1";
453f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
454f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
455f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
456f126890aSEmmanuel Vadot			};
457f126890aSEmmanuel Vadot
458f126890aSEmmanuel Vadot			dap3_fs {
459f126890aSEmmanuel Vadot				nvidia,pins = "dap3_fs_pp0",
460f126890aSEmmanuel Vadot						"dap3_din_pp1";
461f126890aSEmmanuel Vadot				nvidia,function = "i2s2";
462f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
463f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
464f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
465f126890aSEmmanuel Vadot			};
466f126890aSEmmanuel Vadot
467f126890aSEmmanuel Vadot			dap3_dout {
468f126890aSEmmanuel Vadot				nvidia,pins = "dap3_dout_pp2",
469f126890aSEmmanuel Vadot						"dap3_sclk_pp3";
470f126890aSEmmanuel Vadot				nvidia,function = "i2s2";
471f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
472f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
473f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
474f126890aSEmmanuel Vadot			};
475f126890aSEmmanuel Vadot
476f126890aSEmmanuel Vadot			dap_i2s3 {
477f126890aSEmmanuel Vadot				nvidia,pins = "dap4_fs_pp4",
478f126890aSEmmanuel Vadot						"dap4_din_pp5",
479f126890aSEmmanuel Vadot						"dap4_dout_pp6",
480f126890aSEmmanuel Vadot						"dap4_sclk_pp7";
481f126890aSEmmanuel Vadot				nvidia,function = "i2s3";
482f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
483f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
484f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
485f126890aSEmmanuel Vadot			};
486f126890aSEmmanuel Vadot
487f126890aSEmmanuel Vadot			/* Sensors pinmux */
488f126890aSEmmanuel Vadot			nct_irq {
489f126890aSEmmanuel Vadot				nvidia,pins = "pcc2";
490f126890aSEmmanuel Vadot				nvidia,function = "i2s4";
491f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
492f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
493f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
494f126890aSEmmanuel Vadot			};
495f126890aSEmmanuel Vadot
496f126890aSEmmanuel Vadot			/* Asus EC pinmux */
497f126890aSEmmanuel Vadot			ec_irqs {
498f126890aSEmmanuel Vadot				nvidia,pins = "kb_row10_ps2",
499f126890aSEmmanuel Vadot						"kb_row15_ps7";
500f126890aSEmmanuel Vadot				nvidia,function = "kbc";
501f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
502f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
503f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
504f126890aSEmmanuel Vadot			};
505f126890aSEmmanuel Vadot
506f126890aSEmmanuel Vadot			ec_reqs {
507f126890aSEmmanuel Vadot				nvidia,pins = "kb_col1_pq1";
508f126890aSEmmanuel Vadot				nvidia,function = "kbc";
509f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
510f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
511f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
512f126890aSEmmanuel Vadot			};
513f126890aSEmmanuel Vadot
514f126890aSEmmanuel Vadot			/* Memory type bootstrap */
515f126890aSEmmanuel Vadot			mem_boostraps {
516f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad4_pg4",
517f126890aSEmmanuel Vadot						"gmi_ad5_pg5";
518f126890aSEmmanuel Vadot				nvidia,function = "nand";
519f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
520f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
521f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
522f126890aSEmmanuel Vadot			};
523f126890aSEmmanuel Vadot
524f126890aSEmmanuel Vadot			/* PCI-e pinmux */
525f126890aSEmmanuel Vadot			pex_l2_rst_n {
526f126890aSEmmanuel Vadot				nvidia,pins = "pex_l2_rst_n_pcc6",
527f126890aSEmmanuel Vadot						"pex_l0_rst_n_pdd1",
528f126890aSEmmanuel Vadot						"pex_l1_rst_n_pdd5";
529f126890aSEmmanuel Vadot				nvidia,function = "pcie";
530f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
531f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
532f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
533f126890aSEmmanuel Vadot			};
534f126890aSEmmanuel Vadot
535f126890aSEmmanuel Vadot			pex_l2_clkreq_n {
536f126890aSEmmanuel Vadot				nvidia,pins = "pex_l2_clkreq_n_pcc7",
537f126890aSEmmanuel Vadot						"pex_l0_prsnt_n_pdd0",
538f126890aSEmmanuel Vadot						"pex_l0_clkreq_n_pdd2",
539f126890aSEmmanuel Vadot						"pex_wake_n_pdd3",
540f126890aSEmmanuel Vadot						"pex_l1_prsnt_n_pdd4",
541f126890aSEmmanuel Vadot						"pex_l1_clkreq_n_pdd6",
542f126890aSEmmanuel Vadot						"pex_l2_prsnt_n_pdd7";
543f126890aSEmmanuel Vadot				nvidia,function = "pcie";
544f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
545f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
546f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
547f126890aSEmmanuel Vadot			};
548f126890aSEmmanuel Vadot
549f126890aSEmmanuel Vadot			/* SPI pinmux */
550f126890aSEmmanuel Vadot			spi1_mosi_px4 {
551f126890aSEmmanuel Vadot				nvidia,pins = "spi1_mosi_px4",
552f126890aSEmmanuel Vadot						"spi1_sck_px5",
553f126890aSEmmanuel Vadot						"spi1_cs0_n_px6",
554f126890aSEmmanuel Vadot						"spi1_miso_px7";
555f126890aSEmmanuel Vadot				nvidia,function = "spi1";
556f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
557f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
558f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
559f126890aSEmmanuel Vadot			};
560f126890aSEmmanuel Vadot
561f126890aSEmmanuel Vadot			hp_detect {
562f126890aSEmmanuel Vadot				nvidia,pins = "spi2_cs1_n_pw2";
563f126890aSEmmanuel Vadot				nvidia,function = "spi2";
564f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
565f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
566f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
567f126890aSEmmanuel Vadot			};
568f126890aSEmmanuel Vadot
569f126890aSEmmanuel Vadot			mic_detect {
570f126890aSEmmanuel Vadot				nvidia,pins = "spi2_sck_px2";
571f126890aSEmmanuel Vadot				nvidia,function = "spi2";
572f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
573f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
574f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
575f126890aSEmmanuel Vadot			};
576f126890aSEmmanuel Vadot
577f126890aSEmmanuel Vadot			gmi_a17_pb0 {
578f126890aSEmmanuel Vadot				nvidia,pins = "gmi_a17_pb0",
579f126890aSEmmanuel Vadot						"gmi_a16_pj7";
580f126890aSEmmanuel Vadot				nvidia,function = "spi4";
581f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
582f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
583f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
584f126890aSEmmanuel Vadot			};
585f126890aSEmmanuel Vadot
586f126890aSEmmanuel Vadot			gmi_a18_pb1 {
587f126890aSEmmanuel Vadot				nvidia,pins = "gmi_a18_pb1";
588f126890aSEmmanuel Vadot				nvidia,function = "spi4";
589f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
590f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
591f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
592f126890aSEmmanuel Vadot			};
593f126890aSEmmanuel Vadot
594f126890aSEmmanuel Vadot			gmi_a19_pk7 {
595f126890aSEmmanuel Vadot				nvidia,pins = "gmi_a19_pk7";
596f126890aSEmmanuel Vadot				nvidia,function = "spi4";
597f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
599f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600f126890aSEmmanuel Vadot			};
601f126890aSEmmanuel Vadot
602f126890aSEmmanuel Vadot			/* Display A pinmux */
603f126890aSEmmanuel Vadot			lcd_pwr0_pb2 {
604f126890aSEmmanuel Vadot				nvidia,pins = "lcd_pwr0_pb2",
605f126890aSEmmanuel Vadot						"lcd_pclk_pb3",
606f126890aSEmmanuel Vadot						"lcd_pwr1_pc1",
607f126890aSEmmanuel Vadot						"lcd_d0_pe0",
608f126890aSEmmanuel Vadot						"lcd_d1_pe1",
609f126890aSEmmanuel Vadot						"lcd_d2_pe2",
610f126890aSEmmanuel Vadot						"lcd_d3_pe3",
611f126890aSEmmanuel Vadot						"lcd_d4_pe4",
612f126890aSEmmanuel Vadot						"lcd_d5_pe5",
613f126890aSEmmanuel Vadot						"lcd_d6_pe6",
614f126890aSEmmanuel Vadot						"lcd_d7_pe7",
615f126890aSEmmanuel Vadot						"lcd_d8_pf0",
616f126890aSEmmanuel Vadot						"lcd_d9_pf1",
617f126890aSEmmanuel Vadot						"lcd_d10_pf2",
618f126890aSEmmanuel Vadot						"lcd_d11_pf3",
619f126890aSEmmanuel Vadot						"lcd_d12_pf4",
620f126890aSEmmanuel Vadot						"lcd_d13_pf5",
621f126890aSEmmanuel Vadot						"lcd_d14_pf6",
622f126890aSEmmanuel Vadot						"lcd_d15_pf7",
623f126890aSEmmanuel Vadot						"lcd_de_pj1",
624f126890aSEmmanuel Vadot						"lcd_hsync_pj3",
625f126890aSEmmanuel Vadot						"lcd_vsync_pj4",
626f126890aSEmmanuel Vadot						"lcd_d16_pm0",
627f126890aSEmmanuel Vadot						"lcd_d17_pm1",
628f126890aSEmmanuel Vadot						"lcd_d18_pm2",
629f126890aSEmmanuel Vadot						"lcd_d19_pm3",
630f126890aSEmmanuel Vadot						"lcd_d20_pm4",
631f126890aSEmmanuel Vadot						"lcd_d21_pm5",
632f126890aSEmmanuel Vadot						"lcd_d22_pm6",
633f126890aSEmmanuel Vadot						"lcd_d23_pm7",
634f126890aSEmmanuel Vadot						"lcd_dc0_pn6",
635f126890aSEmmanuel Vadot						"lcd_sdin_pz2";
636f126890aSEmmanuel Vadot				nvidia,function = "displaya";
637f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
638f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
639f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
640f126890aSEmmanuel Vadot			};
641f126890aSEmmanuel Vadot
642f126890aSEmmanuel Vadot			lcd_cs0_n_pn4 {
643f126890aSEmmanuel Vadot				nvidia,pins = "lcd_cs0_n_pn4",
644f126890aSEmmanuel Vadot						"lcd_sdout_pn5",
645f126890aSEmmanuel Vadot						"lcd_wr_n_pz3";
646f126890aSEmmanuel Vadot				nvidia,function = "displaya";
647f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
648f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
649f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
650f126890aSEmmanuel Vadot			};
651f126890aSEmmanuel Vadot
652f126890aSEmmanuel Vadot			blink {
653f126890aSEmmanuel Vadot				nvidia,pins = "clk_32k_out_pa0";
654f126890aSEmmanuel Vadot				nvidia,function = "blink";
655f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
656f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
657f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
658f126890aSEmmanuel Vadot			};
659f126890aSEmmanuel Vadot
660f126890aSEmmanuel Vadot			/* KBC keys */
661f126890aSEmmanuel Vadot			kb_col0_pq0 {
662f126890aSEmmanuel Vadot				nvidia,pins = "kb_col0_pq0";
663f126890aSEmmanuel Vadot				nvidia,function = "kbc";
664f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
665f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
666f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
667f126890aSEmmanuel Vadot			};
668f126890aSEmmanuel Vadot
669f126890aSEmmanuel Vadot			kb_col1_pq1 {
670f126890aSEmmanuel Vadot				nvidia,pins = "kb_row1_pr1",
671f126890aSEmmanuel Vadot						"kb_row3_pr3",
672f126890aSEmmanuel Vadot						"kb_row8_ps0",
673f126890aSEmmanuel Vadot						"kb_row14_ps6";
674f126890aSEmmanuel Vadot				nvidia,function = "kbc";
675f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
676f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
677f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678f126890aSEmmanuel Vadot			};
679f126890aSEmmanuel Vadot
680f126890aSEmmanuel Vadot			kb_col4_pq4 {
681f126890aSEmmanuel Vadot				nvidia,pins = "kb_col4_pq4",
682f126890aSEmmanuel Vadot						"kb_col5_pq5",
683f126890aSEmmanuel Vadot						"kb_col7_pq7",
684f126890aSEmmanuel Vadot						"kb_row2_pr2",
685f126890aSEmmanuel Vadot						"kb_row4_pr4",
686f126890aSEmmanuel Vadot						"kb_row5_pr5",
687f126890aSEmmanuel Vadot						"kb_row12_ps4",
688f126890aSEmmanuel Vadot						"kb_row13_ps5";
689f126890aSEmmanuel Vadot				nvidia,function = "kbc";
690f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
691f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
692f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
693f126890aSEmmanuel Vadot			};
694f126890aSEmmanuel Vadot
695f126890aSEmmanuel Vadot			gmi_wp_n_pc7 {
696f126890aSEmmanuel Vadot				nvidia,pins = "gmi_wp_n_pc7",
697f126890aSEmmanuel Vadot						"gmi_wait_pi7",
698f126890aSEmmanuel Vadot						"gmi_cs3_n_pk4";
699f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
700f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
702f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
703f126890aSEmmanuel Vadot			};
704f126890aSEmmanuel Vadot
705f126890aSEmmanuel Vadot			gmi_cs0_n_pj0 {
706f126890aSEmmanuel Vadot				nvidia,pins = "gmi_cs0_n_pj0",
707f126890aSEmmanuel Vadot						"gmi_cs1_n_pj2",
708f126890aSEmmanuel Vadot						"gmi_cs2_n_pk3";
709f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
710f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
711f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
712f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
713f126890aSEmmanuel Vadot			};
714f126890aSEmmanuel Vadot
715f126890aSEmmanuel Vadot			vi_pclk_pt0 {
716f126890aSEmmanuel Vadot				nvidia,pins = "vi_pclk_pt0";
717f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
718f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
719f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
720f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
721f126890aSEmmanuel Vadot				nvidia,lock = <0>;
722f126890aSEmmanuel Vadot				nvidia,io-reset = <0>;
723f126890aSEmmanuel Vadot			};
724f126890aSEmmanuel Vadot
725f126890aSEmmanuel Vadot			/* GPIO keys pinmux */
726f126890aSEmmanuel Vadot			power_key {
727f126890aSEmmanuel Vadot				nvidia,pins = "pv0";
728f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
729f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
730f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
731f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
732f126890aSEmmanuel Vadot			};
733f126890aSEmmanuel Vadot
734f126890aSEmmanuel Vadot			vol_keys {
735f126890aSEmmanuel Vadot				nvidia,pins = "kb_col2_pq2",
736f126890aSEmmanuel Vadot						"kb_col3_pq3";
737f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
738f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
739f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
740f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
741f126890aSEmmanuel Vadot			};
742f126890aSEmmanuel Vadot
743f126890aSEmmanuel Vadot			/* Bluetooth */
744f126890aSEmmanuel Vadot			bt_shutdown {
745f126890aSEmmanuel Vadot				nvidia,pins = "pu0";
746f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
747f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
748f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
749f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
750f126890aSEmmanuel Vadot			};
751f126890aSEmmanuel Vadot
752f126890aSEmmanuel Vadot			bt_dev_wake {
753f126890aSEmmanuel Vadot				nvidia,pins = "pu1";
754f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
755f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
756f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
757f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
758f126890aSEmmanuel Vadot			};
759f126890aSEmmanuel Vadot
760f126890aSEmmanuel Vadot			bt_host_wake {
761f126890aSEmmanuel Vadot				nvidia,pins = "pu6";
762f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
763f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
764f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
765f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
766f126890aSEmmanuel Vadot			};
767f126890aSEmmanuel Vadot
768f126890aSEmmanuel Vadot			pu2 {
769f126890aSEmmanuel Vadot				nvidia,pins = "pu2";
770f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
771f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
772f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
773f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
774f126890aSEmmanuel Vadot			};
775f126890aSEmmanuel Vadot
776f126890aSEmmanuel Vadot			pu3 {
777f126890aSEmmanuel Vadot				nvidia,pins = "pu3";
778f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
779f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
780f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
781f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
782f126890aSEmmanuel Vadot			};
783f126890aSEmmanuel Vadot
784f126890aSEmmanuel Vadot			pcc1 {
785f126890aSEmmanuel Vadot				nvidia,pins = "pcc1";
786f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
787f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
788f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
789f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
790f126890aSEmmanuel Vadot			};
791f126890aSEmmanuel Vadot
792f126890aSEmmanuel Vadot			pv2 {
793f126890aSEmmanuel Vadot				nvidia,pins = "pv2";
794f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
795f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
796f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
797f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
798f126890aSEmmanuel Vadot			};
799f126890aSEmmanuel Vadot
800f126890aSEmmanuel Vadot			pv3 {
801f126890aSEmmanuel Vadot				nvidia,pins = "pv3";
802f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
803f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
804f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
805f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
806f126890aSEmmanuel Vadot			};
807f126890aSEmmanuel Vadot
808f126890aSEmmanuel Vadot			vi_vsync_pd6 {
809f126890aSEmmanuel Vadot				nvidia,pins = "vi_vsync_pd6",
810f126890aSEmmanuel Vadot						"vi_hsync_pd7";
811f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
812f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
813f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
814f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
815f126890aSEmmanuel Vadot				nvidia,lock = <0>;
816f126890aSEmmanuel Vadot				nvidia,io-reset = <0>;
817f126890aSEmmanuel Vadot			};
818f126890aSEmmanuel Vadot
819f126890aSEmmanuel Vadot			vi_d10_pt2 {
820f126890aSEmmanuel Vadot				nvidia,pins = "vi_d10_pt2",
821f126890aSEmmanuel Vadot						"vi_d0_pt4", "pbb0";
822f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
823f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
824f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
825f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
826f126890aSEmmanuel Vadot			};
827f126890aSEmmanuel Vadot
828f126890aSEmmanuel Vadot			kb_row0_pr0 {
829f126890aSEmmanuel Vadot				nvidia,pins = "kb_row0_pr0";
830f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
831f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
832f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
833f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
834f126890aSEmmanuel Vadot			};
835f126890aSEmmanuel Vadot
836f126890aSEmmanuel Vadot			gmi_ad0_pg0 {
837f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad0_pg0",
838f126890aSEmmanuel Vadot						"gmi_ad1_pg1",
839f126890aSEmmanuel Vadot						"gmi_ad2_pg2",
840f126890aSEmmanuel Vadot						"gmi_ad3_pg3",
841f126890aSEmmanuel Vadot						"gmi_ad6_pg6",
842f126890aSEmmanuel Vadot						"gmi_ad7_pg7",
843f126890aSEmmanuel Vadot						"gmi_wr_n_pi0",
844f126890aSEmmanuel Vadot						"gmi_oe_n_pi1",
845f126890aSEmmanuel Vadot						"gmi_dqs_pi2",
846f126890aSEmmanuel Vadot						"gmi_adv_n_pk0",
847f126890aSEmmanuel Vadot						"gmi_clk_pk1";
848f126890aSEmmanuel Vadot				nvidia,function = "nand";
849f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
850f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
851f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
852f126890aSEmmanuel Vadot			};
853f126890aSEmmanuel Vadot
854f126890aSEmmanuel Vadot			gmi_ad13_ph5 {
855f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad13_ph5";
856f126890aSEmmanuel Vadot				nvidia,function = "nand";
857f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
858f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
859f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
860f126890aSEmmanuel Vadot			};
861f126890aSEmmanuel Vadot
862f126890aSEmmanuel Vadot			gmi_ad10_ph2 {
863f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad10_ph2",
864f126890aSEmmanuel Vadot						"gmi_ad11_ph3",
865f126890aSEmmanuel Vadot						"gmi_ad14_ph6";
866f126890aSEmmanuel Vadot				nvidia,function = "nand";
867f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
868f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
869f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
870f126890aSEmmanuel Vadot			};
871f126890aSEmmanuel Vadot
872f126890aSEmmanuel Vadot			gmi_ad12_ph4 {
873f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad12_ph4",
874f126890aSEmmanuel Vadot						"gmi_rst_n_pi4",
875f126890aSEmmanuel Vadot						"gmi_cs7_n_pi6";
876f126890aSEmmanuel Vadot				nvidia,function = "nand";
877f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
878f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
879f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
880f126890aSEmmanuel Vadot			};
881f126890aSEmmanuel Vadot
882f126890aSEmmanuel Vadot			/* Vibrator control */
883f126890aSEmmanuel Vadot			vibrator {
884f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad15_ph7";
885f126890aSEmmanuel Vadot				nvidia,function = "nand";
886f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
887f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
888f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
889f126890aSEmmanuel Vadot			};
890f126890aSEmmanuel Vadot
891f126890aSEmmanuel Vadot			/* PWM pimnmux */
892f126890aSEmmanuel Vadot			pwm_0 {
893f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad8_ph0";
894f126890aSEmmanuel Vadot				nvidia,function = "pwm0";
895f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
896f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
897f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
898f126890aSEmmanuel Vadot			};
899f126890aSEmmanuel Vadot
900f126890aSEmmanuel Vadot			pwm_2 {
901f126890aSEmmanuel Vadot				nvidia,pins = "pu5";
902f126890aSEmmanuel Vadot				nvidia,function = "pwm2";
903f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
904f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
905f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
906f126890aSEmmanuel Vadot			};
907f126890aSEmmanuel Vadot
908f126890aSEmmanuel Vadot			gmi_cs6_n_pi3 {
909f126890aSEmmanuel Vadot				nvidia,pins = "gmi_cs6_n_pi3";
910f126890aSEmmanuel Vadot				nvidia,function = "gmi";
911f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
912f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
913f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
914f126890aSEmmanuel Vadot			};
915f126890aSEmmanuel Vadot
916f126890aSEmmanuel Vadot			/* Spdif pinmux */
917f126890aSEmmanuel Vadot			spdif_out {
918f126890aSEmmanuel Vadot				nvidia,pins = "spdif_out_pk5";
919f126890aSEmmanuel Vadot				nvidia,function = "spdif";
920f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
921f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
922f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
923f126890aSEmmanuel Vadot			};
924f126890aSEmmanuel Vadot
925f126890aSEmmanuel Vadot			spdif_in {
926f126890aSEmmanuel Vadot				nvidia,pins = "spdif_in_pk6";
927f126890aSEmmanuel Vadot				nvidia,function = "spdif";
928f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
929f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
930f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
931f126890aSEmmanuel Vadot			};
932f126890aSEmmanuel Vadot
933f126890aSEmmanuel Vadot			vi_d4_pl2 {
934f126890aSEmmanuel Vadot				nvidia,pins = "vi_d4_pl2";
935f126890aSEmmanuel Vadot				nvidia,function = "vi";
936f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
937f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
938f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
939f126890aSEmmanuel Vadot			};
940f126890aSEmmanuel Vadot
941f126890aSEmmanuel Vadot			vi_d6_pl4 {
942f126890aSEmmanuel Vadot				nvidia,pins = "vi_d6_pl4";
943f126890aSEmmanuel Vadot				nvidia,function = "vi";
944f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
945f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
946f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
947f126890aSEmmanuel Vadot				nvidia,lock = <0>;
948f126890aSEmmanuel Vadot				nvidia,io-reset = <0>;
949f126890aSEmmanuel Vadot			};
950f126890aSEmmanuel Vadot
951f126890aSEmmanuel Vadot			vi_mclk_pt1 {
952f126890aSEmmanuel Vadot				nvidia,pins = "vi_mclk_pt1";
953f126890aSEmmanuel Vadot				nvidia,function = "vi";
954f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
955f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
956f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
957f126890aSEmmanuel Vadot			};
958f126890aSEmmanuel Vadot
959f126890aSEmmanuel Vadot			jtag_rtck {
960f126890aSEmmanuel Vadot				nvidia,pins = "jtag_rtck_pu7";
961f126890aSEmmanuel Vadot				nvidia,function = "rtck";
962f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
963f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
964f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
965f126890aSEmmanuel Vadot			};
966f126890aSEmmanuel Vadot
967f126890aSEmmanuel Vadot			crt_hsync_pv6 {
968f126890aSEmmanuel Vadot				nvidia,pins = "crt_hsync_pv6",
969f126890aSEmmanuel Vadot						"crt_vsync_pv7";
970f126890aSEmmanuel Vadot				nvidia,function = "crt";
971f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
972f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
973f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
974f126890aSEmmanuel Vadot			};
975f126890aSEmmanuel Vadot
976f126890aSEmmanuel Vadot			clk1_out {
977f126890aSEmmanuel Vadot				nvidia,pins = "clk1_out_pw4";
978f126890aSEmmanuel Vadot				nvidia,function = "extperiph1";
979f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
980f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
981f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
982f126890aSEmmanuel Vadot			};
983f126890aSEmmanuel Vadot
984f126890aSEmmanuel Vadot			clk2_out {
985f126890aSEmmanuel Vadot				nvidia,pins = "clk2_out_pw5";
986f126890aSEmmanuel Vadot				nvidia,function = "extperiph2";
987f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
988f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
989f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
990f126890aSEmmanuel Vadot			};
991f126890aSEmmanuel Vadot
992f126890aSEmmanuel Vadot			clk3_out {
993f126890aSEmmanuel Vadot				nvidia,pins = "clk3_out_pee0";
994f126890aSEmmanuel Vadot				nvidia,function = "extperiph3";
995f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
996f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
997f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
998f126890aSEmmanuel Vadot			};
999f126890aSEmmanuel Vadot
1000f126890aSEmmanuel Vadot			sys_clk_req {
1001f126890aSEmmanuel Vadot				nvidia,pins = "sys_clk_req_pz5";
1002f126890aSEmmanuel Vadot				nvidia,function = "sysclk";
1003f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1004f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1005f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1006f126890aSEmmanuel Vadot			};
1007f126890aSEmmanuel Vadot
1008f126890aSEmmanuel Vadot			pbb4 {
1009f126890aSEmmanuel Vadot				nvidia,pins = "pbb4";
1010f126890aSEmmanuel Vadot				nvidia,function = "vgp4";
1011f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1012f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1013f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1014f126890aSEmmanuel Vadot			};
1015f126890aSEmmanuel Vadot
1016f126890aSEmmanuel Vadot			pbb5 {
1017f126890aSEmmanuel Vadot				nvidia,pins = "pbb5";
1018f126890aSEmmanuel Vadot				nvidia,function = "vgp5";
1019f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1020f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1021f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1022f126890aSEmmanuel Vadot			};
1023f126890aSEmmanuel Vadot
1024f126890aSEmmanuel Vadot			pbb6 {
1025f126890aSEmmanuel Vadot				nvidia,pins = "pbb6";
1026f126890aSEmmanuel Vadot				nvidia,function = "vgp6";
1027f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1028f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1029f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1030f126890aSEmmanuel Vadot			};
1031f126890aSEmmanuel Vadot
1032f126890aSEmmanuel Vadot			clk2_req_pcc5 {
1033f126890aSEmmanuel Vadot				nvidia,pins = "clk2_req_pcc5",
1034f126890aSEmmanuel Vadot						"clk1_req_pee2";
1035f126890aSEmmanuel Vadot				nvidia,function = "dap";
1036f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1037f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1038f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1039f126890aSEmmanuel Vadot			};
1040f126890aSEmmanuel Vadot
1041f126890aSEmmanuel Vadot			clk3_req_pee1 {
1042f126890aSEmmanuel Vadot				nvidia,pins = "clk3_req_pee1";
1043f126890aSEmmanuel Vadot				nvidia,function = "dev3";
1044f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1045f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
1046f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1047f126890aSEmmanuel Vadot			};
1048f126890aSEmmanuel Vadot
1049f126890aSEmmanuel Vadot			owr {
1050f126890aSEmmanuel Vadot				nvidia,pins = "owr";
1051f126890aSEmmanuel Vadot				nvidia,function = "owr";
1052f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1053f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
1054f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1055f126890aSEmmanuel Vadot			};
1056f126890aSEmmanuel Vadot
1057f126890aSEmmanuel Vadot			/* GPIO power/drive control */
1058f126890aSEmmanuel Vadot			drive_dap1 {
1059f126890aSEmmanuel Vadot				nvidia,pins = "drive_dap1",
1060f126890aSEmmanuel Vadot						"drive_dap2",
1061f126890aSEmmanuel Vadot						"drive_dbg",
1062f126890aSEmmanuel Vadot						"drive_at5",
1063f126890aSEmmanuel Vadot						"drive_gme",
1064f126890aSEmmanuel Vadot						"drive_ddc",
1065f126890aSEmmanuel Vadot						"drive_ao1",
1066f126890aSEmmanuel Vadot						"drive_uart3";
1067f126890aSEmmanuel Vadot				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1068f126890aSEmmanuel Vadot				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
1069f126890aSEmmanuel Vadot				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
1070f126890aSEmmanuel Vadot				nvidia,pull-down-strength = <31>;
1071f126890aSEmmanuel Vadot				nvidia,pull-up-strength = <31>;
1072f126890aSEmmanuel Vadot				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1073f126890aSEmmanuel Vadot				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
1074f126890aSEmmanuel Vadot			};
1075f126890aSEmmanuel Vadot
1076f126890aSEmmanuel Vadot			drive_sdio1 {
1077f126890aSEmmanuel Vadot				nvidia,pins = "drive_sdio1",
1078f126890aSEmmanuel Vadot						"drive_sdio3";
1079f126890aSEmmanuel Vadot				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
1080f126890aSEmmanuel Vadot				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
1081f126890aSEmmanuel Vadot				nvidia,pull-down-strength = <46>;
1082f126890aSEmmanuel Vadot				nvidia,pull-up-strength = <42>;
1083f126890aSEmmanuel Vadot				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
1084f126890aSEmmanuel Vadot				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
1085f126890aSEmmanuel Vadot			};
1086f126890aSEmmanuel Vadot		};
1087f126890aSEmmanuel Vadot	};
1088f126890aSEmmanuel Vadot
1089f126890aSEmmanuel Vadot	serial@70006040 {
1090f126890aSEmmanuel Vadot		compatible = "nvidia,tegra30-hsuart";
1091*aa1a8ff2SEmmanuel Vadot		reset-names = "serial";
1092f126890aSEmmanuel Vadot		/delete-property/ reg-shift;
1093f126890aSEmmanuel Vadot		status = "okay";
1094f126890aSEmmanuel Vadot
1095f126890aSEmmanuel Vadot		/* Broadcom GPS BCM47511 */
1096f126890aSEmmanuel Vadot	};
1097f126890aSEmmanuel Vadot
1098f126890aSEmmanuel Vadot	serial@70006200 {
1099f126890aSEmmanuel Vadot		compatible = "nvidia,tegra30-hsuart";
1100*aa1a8ff2SEmmanuel Vadot		reset-names = "serial";
1101f126890aSEmmanuel Vadot		/delete-property/ reg-shift;
1102f126890aSEmmanuel Vadot		status = "okay";
1103f126890aSEmmanuel Vadot
1104f126890aSEmmanuel Vadot		nvidia,adjust-baud-rates = <0 9600 100>,
1105f126890aSEmmanuel Vadot					   <9600 115200 200>,
1106f126890aSEmmanuel Vadot					   <1000000 4000000 136>;
1107f126890aSEmmanuel Vadot
1108f126890aSEmmanuel Vadot		bluetooth {
1109f126890aSEmmanuel Vadot			max-speed = <4000000>;
1110f126890aSEmmanuel Vadot
1111f126890aSEmmanuel Vadot			clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1112f126890aSEmmanuel Vadot			clock-names = "txco";
1113f126890aSEmmanuel Vadot
1114f126890aSEmmanuel Vadot			interrupt-parent = <&gpio>;
1115f126890aSEmmanuel Vadot			interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>;
1116f126890aSEmmanuel Vadot			interrupt-names = "host-wakeup";
1117f126890aSEmmanuel Vadot
1118f126890aSEmmanuel Vadot			device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
1119f126890aSEmmanuel Vadot			shutdown-gpios =      <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
1120f126890aSEmmanuel Vadot
1121f126890aSEmmanuel Vadot			vbat-supply  = <&vdd_3v3_com>;
1122f126890aSEmmanuel Vadot			vddio-supply = <&vdd_1v8_vio>;
1123f126890aSEmmanuel Vadot		};
1124f126890aSEmmanuel Vadot	};
1125f126890aSEmmanuel Vadot
1126f126890aSEmmanuel Vadot	pwm@7000a000 {
1127f126890aSEmmanuel Vadot		status = "okay";
1128f126890aSEmmanuel Vadot	};
1129f126890aSEmmanuel Vadot
1130f126890aSEmmanuel Vadot	lcd_ddc: i2c@7000c000 {
1131f126890aSEmmanuel Vadot		status = "okay";
1132f126890aSEmmanuel Vadot		clock-frequency = <100000>;
1133f126890aSEmmanuel Vadot	};
1134f126890aSEmmanuel Vadot
1135f126890aSEmmanuel Vadot	i2c@7000c400 {
1136f126890aSEmmanuel Vadot		status = "okay";
1137f126890aSEmmanuel Vadot		clock-frequency = <400000>;
1138f126890aSEmmanuel Vadot	};
1139f126890aSEmmanuel Vadot
1140f126890aSEmmanuel Vadot	i2c@7000c500 {
1141f126890aSEmmanuel Vadot		status = "okay";
1142f126890aSEmmanuel Vadot
1143f126890aSEmmanuel Vadot		/* Aichi AMI306 digital compass */
1144f126890aSEmmanuel Vadot		magnetometer@e {
1145f126890aSEmmanuel Vadot			compatible = "asahi-kasei,ak8974";
1146f126890aSEmmanuel Vadot			reg = <0x0e>;
1147f126890aSEmmanuel Vadot
1148f126890aSEmmanuel Vadot			avdd-supply = <&vdd_3v3_sys>;
1149f126890aSEmmanuel Vadot			dvdd-supply = <&vdd_1v8_vio>;
1150f126890aSEmmanuel Vadot		};
1151f126890aSEmmanuel Vadot
1152f126890aSEmmanuel Vadot		/* Dynaimage ambient light sensor */
1153f126890aSEmmanuel Vadot		light-sensor@1c {
1154f126890aSEmmanuel Vadot			compatible = "dynaimage,al3010";
1155f126890aSEmmanuel Vadot			reg = <0x1c>;
1156f126890aSEmmanuel Vadot
1157f126890aSEmmanuel Vadot			interrupt-parent = <&gpio>;
1158f126890aSEmmanuel Vadot			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
1159f126890aSEmmanuel Vadot
1160f126890aSEmmanuel Vadot			vdd-supply = <&vdd_3v3_sys>;
1161f126890aSEmmanuel Vadot		};
1162f126890aSEmmanuel Vadot
1163f126890aSEmmanuel Vadot		gyroscope@68 {
1164f126890aSEmmanuel Vadot			compatible = "invensense,mpu3050";
1165f126890aSEmmanuel Vadot			reg = <0x68>;
1166f126890aSEmmanuel Vadot
1167f126890aSEmmanuel Vadot			interrupt-parent = <&gpio>;
1168f126890aSEmmanuel Vadot			interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_EDGE_RISING>;
1169f126890aSEmmanuel Vadot
1170f126890aSEmmanuel Vadot			vdd-supply    = <&vdd_3v3_sys>;
1171f126890aSEmmanuel Vadot			vlogic-supply = <&vdd_1v8_vio>;
1172f126890aSEmmanuel Vadot
1173f126890aSEmmanuel Vadot			i2c-gate {
1174f126890aSEmmanuel Vadot				#address-cells = <1>;
1175f126890aSEmmanuel Vadot				#size-cells = <0>;
1176f126890aSEmmanuel Vadot
1177f126890aSEmmanuel Vadot				accelerometer@f {
1178f126890aSEmmanuel Vadot					compatible = "kionix,kxtf9";
1179f126890aSEmmanuel Vadot					reg = <0x0f>;
1180f126890aSEmmanuel Vadot
1181f126890aSEmmanuel Vadot					interrupt-parent = <&gpio>;
1182f126890aSEmmanuel Vadot					interrupts = <TEGRA_GPIO(O, 5) IRQ_TYPE_EDGE_RISING>;
1183f126890aSEmmanuel Vadot
1184f126890aSEmmanuel Vadot					vdd-supply = <&vdd_1v8_vio>;
1185f126890aSEmmanuel Vadot					vddio-supply = <&vdd_1v8_vio>;
1186f126890aSEmmanuel Vadot				};
1187f126890aSEmmanuel Vadot			};
1188f126890aSEmmanuel Vadot		};
1189f126890aSEmmanuel Vadot	};
1190f126890aSEmmanuel Vadot
1191f126890aSEmmanuel Vadot	hdmi_ddc: i2c@7000c700 {
1192f126890aSEmmanuel Vadot		status = "okay";
1193f126890aSEmmanuel Vadot		clock-frequency = <93750>;
1194f126890aSEmmanuel Vadot	};
1195f126890aSEmmanuel Vadot
1196f126890aSEmmanuel Vadot	i2c@7000d000 {
1197f126890aSEmmanuel Vadot		status = "okay";
1198f126890aSEmmanuel Vadot		clock-frequency = <400000>;
1199f126890aSEmmanuel Vadot
1200f126890aSEmmanuel Vadot		/* Texas Instruments TPS659110 PMIC */
1201f126890aSEmmanuel Vadot		pmic: pmic@2d {
1202f126890aSEmmanuel Vadot			compatible = "ti,tps65911";
1203f126890aSEmmanuel Vadot			reg = <0x2d>;
1204f126890aSEmmanuel Vadot
1205f126890aSEmmanuel Vadot			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1206f126890aSEmmanuel Vadot			#interrupt-cells = <2>;
1207f126890aSEmmanuel Vadot			interrupt-controller;
1208f126890aSEmmanuel Vadot			wakeup-source;
1209f126890aSEmmanuel Vadot
1210f126890aSEmmanuel Vadot			ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
1211f126890aSEmmanuel Vadot			ti,system-power-controller;
1212f126890aSEmmanuel Vadot			ti,sleep-keep-ck32k;
1213f126890aSEmmanuel Vadot			ti,sleep-enable;
1214f126890aSEmmanuel Vadot
1215f126890aSEmmanuel Vadot			#gpio-cells = <2>;
1216f126890aSEmmanuel Vadot			gpio-controller;
1217f126890aSEmmanuel Vadot
1218f126890aSEmmanuel Vadot			vcc1-supply = <&vdd_5v0_bat>;
1219f126890aSEmmanuel Vadot			vcc2-supply = <&vdd_5v0_bat>;
1220f126890aSEmmanuel Vadot			vcc3-supply = <&vdd_1v8_vio>;
1221f126890aSEmmanuel Vadot			vcc4-supply = <&vdd_5v0_sys>;
1222f126890aSEmmanuel Vadot			vcc5-supply = <&vdd_5v0_bat>;
1223f126890aSEmmanuel Vadot			vcc6-supply = <&vdd_3v3_sys>;
1224f126890aSEmmanuel Vadot			vcc7-supply = <&vdd_5v0_bat>;
1225f126890aSEmmanuel Vadot			vccio-supply = <&vdd_5v0_bat>;
1226f126890aSEmmanuel Vadot
1227f126890aSEmmanuel Vadot			pmic-sleep-hog {
1228f126890aSEmmanuel Vadot				gpio-hog;
1229f126890aSEmmanuel Vadot				gpios = <2 GPIO_ACTIVE_HIGH>;
1230f126890aSEmmanuel Vadot				output-high;
1231f126890aSEmmanuel Vadot			};
1232f126890aSEmmanuel Vadot
1233f126890aSEmmanuel Vadot			regulators {
1234f126890aSEmmanuel Vadot				/* VDD1 is not used by Transformers */
1235f126890aSEmmanuel Vadot
1236f126890aSEmmanuel Vadot				vddio_ddr: vdd2 {
1237f126890aSEmmanuel Vadot					regulator-name = "vddio_ddr";
1238f126890aSEmmanuel Vadot					regulator-min-microvolt = <1200000>;
1239f126890aSEmmanuel Vadot					regulator-max-microvolt = <1200000>;
1240f126890aSEmmanuel Vadot					regulator-always-on;
1241f126890aSEmmanuel Vadot					regulator-boot-on;
1242f126890aSEmmanuel Vadot				};
1243f126890aSEmmanuel Vadot
1244f126890aSEmmanuel Vadot				vdd_cpu: vddctrl {
1245f126890aSEmmanuel Vadot					regulator-name = "vdd_cpu,vdd_sys";
1246f126890aSEmmanuel Vadot					regulator-min-microvolt = <600000>;
1247f126890aSEmmanuel Vadot					regulator-max-microvolt = <1400000>;
1248f126890aSEmmanuel Vadot					regulator-coupled-with = <&vdd_core>;
1249f126890aSEmmanuel Vadot					regulator-coupled-max-spread = <300000>;
1250f126890aSEmmanuel Vadot					regulator-max-step-microvolt = <100000>;
1251f126890aSEmmanuel Vadot					regulator-always-on;
1252f126890aSEmmanuel Vadot					regulator-boot-on;
1253f126890aSEmmanuel Vadot					ti,regulator-ext-sleep-control = <1>;
1254f126890aSEmmanuel Vadot
1255f126890aSEmmanuel Vadot					nvidia,tegra-cpu-regulator;
1256f126890aSEmmanuel Vadot				};
1257f126890aSEmmanuel Vadot
1258f126890aSEmmanuel Vadot				vdd_1v8_vio: vio {
1259f126890aSEmmanuel Vadot					regulator-name = "vdd_1v8_gen";
1260f126890aSEmmanuel Vadot					/* FIXME: eMMC won't work, if set to 1.8 V */
1261f126890aSEmmanuel Vadot					regulator-min-microvolt = <1500000>;
1262f126890aSEmmanuel Vadot					regulator-max-microvolt = <3300000>;
1263f126890aSEmmanuel Vadot					regulator-always-on;
1264f126890aSEmmanuel Vadot					regulator-boot-on;
1265f126890aSEmmanuel Vadot				};
1266f126890aSEmmanuel Vadot
1267f126890aSEmmanuel Vadot				/* eMMC VDD */
1268f126890aSEmmanuel Vadot				vcore_emmc: ldo1 {
1269f126890aSEmmanuel Vadot					regulator-name = "vdd_emmc_core";
1270f126890aSEmmanuel Vadot					regulator-min-microvolt = <3300000>;
1271f126890aSEmmanuel Vadot					regulator-max-microvolt = <3300000>;
1272f126890aSEmmanuel Vadot					regulator-always-on;
1273f126890aSEmmanuel Vadot				};
1274f126890aSEmmanuel Vadot
1275f126890aSEmmanuel Vadot				/* uSD slot VDD */
1276f126890aSEmmanuel Vadot				vdd_usd: ldo2 {
1277f126890aSEmmanuel Vadot					regulator-name = "vdd_usd";
1278f126890aSEmmanuel Vadot					regulator-min-microvolt = <3100000>;
1279f126890aSEmmanuel Vadot					regulator-max-microvolt = <3100000>;
1280f126890aSEmmanuel Vadot					/* FIXME: Without this, voltage switching fails */
1281f126890aSEmmanuel Vadot					regulator-always-on;
1282f126890aSEmmanuel Vadot				};
1283f126890aSEmmanuel Vadot
1284f126890aSEmmanuel Vadot				/* uSD slot VDDIO */
1285f126890aSEmmanuel Vadot				vddio_usd: ldo3 {
1286f126890aSEmmanuel Vadot					regulator-name = "vddio_usd";
1287f126890aSEmmanuel Vadot					regulator-min-microvolt = <1800000>;
1288f126890aSEmmanuel Vadot					regulator-max-microvolt = <3100000>;
1289f126890aSEmmanuel Vadot				};
1290f126890aSEmmanuel Vadot
1291f126890aSEmmanuel Vadot				ldo4 {
1292f126890aSEmmanuel Vadot					regulator-name = "vdd_rtc";
1293f126890aSEmmanuel Vadot					regulator-min-microvolt = <1200000>;
1294f126890aSEmmanuel Vadot					regulator-max-microvolt = <1200000>;
1295f126890aSEmmanuel Vadot					regulator-always-on;
1296f126890aSEmmanuel Vadot				};
1297f126890aSEmmanuel Vadot
1298f126890aSEmmanuel Vadot				/* LDO5 is not used by Transformers */
1299f126890aSEmmanuel Vadot
1300f126890aSEmmanuel Vadot				ldo6 {
1301f126890aSEmmanuel Vadot					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
1302f126890aSEmmanuel Vadot					regulator-min-microvolt = <1200000>;
1303f126890aSEmmanuel Vadot					regulator-max-microvolt = <1200000>;
1304f126890aSEmmanuel Vadot				};
1305f126890aSEmmanuel Vadot
1306f126890aSEmmanuel Vadot				ldo7 {
1307f126890aSEmmanuel Vadot					regulator-name = "vdd_pllm,x,u,a_p_c_s";
1308f126890aSEmmanuel Vadot					regulator-min-microvolt = <1200000>;
1309f126890aSEmmanuel Vadot					regulator-max-microvolt = <1200000>;
1310f126890aSEmmanuel Vadot					regulator-always-on;
1311f126890aSEmmanuel Vadot					regulator-boot-on;
1312f126890aSEmmanuel Vadot					ti,regulator-ext-sleep-control = <8>;
1313f126890aSEmmanuel Vadot				};
1314f126890aSEmmanuel Vadot
1315f126890aSEmmanuel Vadot				ldo8 {
1316f126890aSEmmanuel Vadot					regulator-name = "vdd_ddr_hs";
1317f126890aSEmmanuel Vadot					regulator-min-microvolt = <1000000>;
1318f126890aSEmmanuel Vadot					regulator-max-microvolt = <1000000>;
1319f126890aSEmmanuel Vadot					regulator-always-on;
1320f126890aSEmmanuel Vadot					ti,regulator-ext-sleep-control = <8>;
1321f126890aSEmmanuel Vadot				};
1322f126890aSEmmanuel Vadot			};
1323f126890aSEmmanuel Vadot		};
1324f126890aSEmmanuel Vadot
1325f126890aSEmmanuel Vadot		nct72: temperature-sensor@4c {
1326f126890aSEmmanuel Vadot			compatible = "onnn,nct1008";
1327f126890aSEmmanuel Vadot			reg = <0x4c>;
1328f126890aSEmmanuel Vadot
1329f126890aSEmmanuel Vadot			interrupt-parent = <&gpio>;
1330f126890aSEmmanuel Vadot			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_EDGE_FALLING>;
1331f126890aSEmmanuel Vadot
1332f126890aSEmmanuel Vadot			vcc-supply = <&vdd_3v3_sys>;
1333f126890aSEmmanuel Vadot			#thermal-sensor-cells = <1>;
1334f126890aSEmmanuel Vadot		};
1335f126890aSEmmanuel Vadot
1336f126890aSEmmanuel Vadot		vdd_core: core-regulator@60 {
1337f126890aSEmmanuel Vadot			compatible = "ti,tps62361";
1338f126890aSEmmanuel Vadot			reg = <0x60>;
1339f126890aSEmmanuel Vadot
1340f126890aSEmmanuel Vadot			regulator-name = "tps62361-vout";
1341f126890aSEmmanuel Vadot			regulator-min-microvolt = <500000>;
1342f126890aSEmmanuel Vadot			regulator-max-microvolt = <1770000>;
1343f126890aSEmmanuel Vadot			regulator-coupled-with = <&vdd_cpu>;
1344f126890aSEmmanuel Vadot			regulator-coupled-max-spread = <300000>;
1345f126890aSEmmanuel Vadot			regulator-max-step-microvolt = <100000>;
1346f126890aSEmmanuel Vadot			regulator-boot-on;
1347f126890aSEmmanuel Vadot			regulator-always-on;
1348f126890aSEmmanuel Vadot			ti,enable-vout-discharge;
1349f126890aSEmmanuel Vadot			ti,vsel0-state-high;
1350f126890aSEmmanuel Vadot			ti,vsel1-state-high;
1351f126890aSEmmanuel Vadot
1352f126890aSEmmanuel Vadot			nvidia,tegra-core-regulator;
1353f126890aSEmmanuel Vadot		};
1354f126890aSEmmanuel Vadot	};
1355f126890aSEmmanuel Vadot
1356f126890aSEmmanuel Vadot	pmc@7000e400 {
1357f126890aSEmmanuel Vadot		status = "okay";
1358f126890aSEmmanuel Vadot		nvidia,invert-interrupt;
1359f126890aSEmmanuel Vadot		/* FIXME: LP1 doesn't work at the moment */
1360f126890aSEmmanuel Vadot		nvidia,suspend-mode = <2>;
1361f126890aSEmmanuel Vadot		nvidia,cpu-pwr-good-time = <2000>;
1362f126890aSEmmanuel Vadot		nvidia,cpu-pwr-off-time = <200>;
1363f126890aSEmmanuel Vadot		nvidia,core-pwr-good-time = <3845 3845>;
1364f126890aSEmmanuel Vadot		nvidia,core-pwr-off-time = <0>;
1365f126890aSEmmanuel Vadot		nvidia,core-power-req-active-high;
1366f126890aSEmmanuel Vadot		nvidia,sys-clock-req-active-high;
1367f126890aSEmmanuel Vadot		core-supply = <&vdd_core>;
1368f126890aSEmmanuel Vadot
1369f126890aSEmmanuel Vadot		/* Set DEV_OFF + PWR_OFF_SET bit in DCDC control register of TPS65911 PMIC  */
1370f126890aSEmmanuel Vadot		i2c-thermtrip {
1371f126890aSEmmanuel Vadot			nvidia,i2c-controller-id = <4>;
1372f126890aSEmmanuel Vadot			nvidia,bus-addr = <0x2d>;
1373f126890aSEmmanuel Vadot			nvidia,reg-addr = <0x3f>;
1374f126890aSEmmanuel Vadot			nvidia,reg-data = <0x81>;
1375f126890aSEmmanuel Vadot		};
1376f126890aSEmmanuel Vadot	};
1377f126890aSEmmanuel Vadot
1378f126890aSEmmanuel Vadot	hda@70030000 {
1379f126890aSEmmanuel Vadot		status = "okay";
1380f126890aSEmmanuel Vadot	};
1381f126890aSEmmanuel Vadot
1382f126890aSEmmanuel Vadot	ahub@70080000 {
1383f126890aSEmmanuel Vadot		i2s@70080400 {		/* i2s1 */
1384f126890aSEmmanuel Vadot			status = "okay";
1385f126890aSEmmanuel Vadot		};
1386f126890aSEmmanuel Vadot
1387f126890aSEmmanuel Vadot		/* BT SCO */
1388f126890aSEmmanuel Vadot		i2s@70080600 {		/* i2s3 */
1389f126890aSEmmanuel Vadot			status = "okay";
1390f126890aSEmmanuel Vadot		};
1391f126890aSEmmanuel Vadot	};
1392f126890aSEmmanuel Vadot
1393f126890aSEmmanuel Vadot	mmc@78000000 {
1394f126890aSEmmanuel Vadot		status = "okay";
1395f126890aSEmmanuel Vadot
1396f126890aSEmmanuel Vadot		/* FIXME: Full 208Mhz clock rate doesn't work reliably */
1397f126890aSEmmanuel Vadot		max-frequency = <104000000>;
1398f126890aSEmmanuel Vadot
1399f126890aSEmmanuel Vadot		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1400f126890aSEmmanuel Vadot		bus-width = <4>;
1401f126890aSEmmanuel Vadot
1402f126890aSEmmanuel Vadot		vmmc-supply = <&vdd_usd>;	/* ldo2 */
1403f126890aSEmmanuel Vadot		vqmmc-supply = <&vddio_usd>;	/* ldo3 */
1404f126890aSEmmanuel Vadot	};
1405f126890aSEmmanuel Vadot
1406f126890aSEmmanuel Vadot	mmc@78000400 {
1407f126890aSEmmanuel Vadot		status = "okay";
1408f126890aSEmmanuel Vadot
1409f126890aSEmmanuel Vadot		#address-cells = <1>;
1410f126890aSEmmanuel Vadot		#size-cells = <0>;
1411f126890aSEmmanuel Vadot
1412f126890aSEmmanuel Vadot		assigned-clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
1413f126890aSEmmanuel Vadot		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
1414f126890aSEmmanuel Vadot		assigned-clock-rates = <50000000>;
1415f126890aSEmmanuel Vadot
1416f126890aSEmmanuel Vadot		max-frequency = <50000000>;
1417f126890aSEmmanuel Vadot		keep-power-in-suspend;
1418f126890aSEmmanuel Vadot		bus-width = <4>;
1419f126890aSEmmanuel Vadot		non-removable;
1420f126890aSEmmanuel Vadot
1421f126890aSEmmanuel Vadot		mmc-pwrseq = <&brcm_wifi_pwrseq>;
1422f126890aSEmmanuel Vadot		vmmc-supply = <&vdd_3v3_com>;
1423f126890aSEmmanuel Vadot		vqmmc-supply = <&vdd_1v8_vio>;
1424f126890aSEmmanuel Vadot
1425f126890aSEmmanuel Vadot		/* Azurewave AW-NH615 BCM4329B1 or AW-NH665 BCM4330B1 */
1426f126890aSEmmanuel Vadot		wifi@1 {
1427f126890aSEmmanuel Vadot			compatible = "brcm,bcm4329-fmac";
1428f126890aSEmmanuel Vadot			reg = <1>;
1429f126890aSEmmanuel Vadot
1430f126890aSEmmanuel Vadot			interrupt-parent = <&gpio>;
1431f126890aSEmmanuel Vadot			interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_LEVEL_HIGH>;
1432f126890aSEmmanuel Vadot			interrupt-names = "host-wake";
1433f126890aSEmmanuel Vadot		};
1434f126890aSEmmanuel Vadot	};
1435f126890aSEmmanuel Vadot
1436f126890aSEmmanuel Vadot	mmc@78000600 {
1437f126890aSEmmanuel Vadot		status = "okay";
1438f126890aSEmmanuel Vadot		bus-width = <8>;
1439f126890aSEmmanuel Vadot		vmmc-supply = <&vcore_emmc>;
1440f126890aSEmmanuel Vadot		vqmmc-supply = <&vdd_1v8_vio>;
1441f126890aSEmmanuel Vadot		mmc-ddr-3_3v;
1442f126890aSEmmanuel Vadot		non-removable;
1443f126890aSEmmanuel Vadot	};
1444f126890aSEmmanuel Vadot
1445f126890aSEmmanuel Vadot	/* USB via ASUS connector */
1446f126890aSEmmanuel Vadot	usb@7d000000 {
1447f126890aSEmmanuel Vadot		compatible = "nvidia,tegra30-udc";
1448f126890aSEmmanuel Vadot		status = "okay";
1449f126890aSEmmanuel Vadot		dr_mode = "peripheral";
1450f126890aSEmmanuel Vadot	};
1451f126890aSEmmanuel Vadot
1452f126890aSEmmanuel Vadot	usb-phy@7d000000 {
1453f126890aSEmmanuel Vadot		status = "okay";
1454f126890aSEmmanuel Vadot		dr_mode = "peripheral";
1455f126890aSEmmanuel Vadot		nvidia,hssync-start-delay = <0>;
1456f126890aSEmmanuel Vadot		nvidia,xcvr-lsfslew = <2>;
1457f126890aSEmmanuel Vadot		nvidia,xcvr-lsrslew = <2>;
1458f126890aSEmmanuel Vadot		vbus-supply = <&vdd_5v0_sys>;
1459f126890aSEmmanuel Vadot	};
1460f126890aSEmmanuel Vadot
1461f126890aSEmmanuel Vadot	/* Dock's USB port */
1462f126890aSEmmanuel Vadot	usb@7d008000 {
1463f126890aSEmmanuel Vadot		status = "okay";
1464f126890aSEmmanuel Vadot	};
1465f126890aSEmmanuel Vadot
1466f126890aSEmmanuel Vadot	usb-phy@7d008000 {
1467f126890aSEmmanuel Vadot		status = "okay";
1468f126890aSEmmanuel Vadot		vbus-supply = <&vdd_5v0_bat>;
1469f126890aSEmmanuel Vadot	};
1470f126890aSEmmanuel Vadot
1471f126890aSEmmanuel Vadot	mains: ac-adapter-detect {
1472f126890aSEmmanuel Vadot		compatible = "gpio-charger";
1473f126890aSEmmanuel Vadot		charger-type = "mains";
1474f126890aSEmmanuel Vadot		gpios = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1475f126890aSEmmanuel Vadot	};
1476f126890aSEmmanuel Vadot
1477f126890aSEmmanuel Vadot	backlight: backlight {
1478f126890aSEmmanuel Vadot		compatible = "pwm-backlight";
1479f126890aSEmmanuel Vadot
1480f126890aSEmmanuel Vadot		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1481f126890aSEmmanuel Vadot		power-supply = <&vdd_5v0_bl>;
1482f126890aSEmmanuel Vadot		pwms = <&pwm 0 4000000>;
1483f126890aSEmmanuel Vadot
1484f126890aSEmmanuel Vadot		brightness-levels = <1 255>;
1485f126890aSEmmanuel Vadot		num-interpolated-steps = <254>;
1486f126890aSEmmanuel Vadot		default-brightness-level = <40>;
1487f126890aSEmmanuel Vadot	};
1488f126890aSEmmanuel Vadot
1489f126890aSEmmanuel Vadot	/* PMIC has a built-in 32KHz oscillator which is used by PMC */
1490f126890aSEmmanuel Vadot	clk32k_in: clock-32k {
1491f126890aSEmmanuel Vadot		compatible = "fixed-clock";
1492f126890aSEmmanuel Vadot		#clock-cells = <0>;
1493f126890aSEmmanuel Vadot		clock-frequency = <32768>;
1494f126890aSEmmanuel Vadot		clock-output-names = "pmic-oscillator";
1495f126890aSEmmanuel Vadot	};
1496f126890aSEmmanuel Vadot
1497f126890aSEmmanuel Vadot	cpus {
1498f126890aSEmmanuel Vadot		cpu0: cpu@0 {
1499f126890aSEmmanuel Vadot			cpu-supply = <&vdd_cpu>;
1500f126890aSEmmanuel Vadot			operating-points-v2 = <&cpu0_opp_table>;
1501f126890aSEmmanuel Vadot			#cooling-cells = <2>;
1502f126890aSEmmanuel Vadot		};
1503f126890aSEmmanuel Vadot		cpu1: cpu@1 {
1504f126890aSEmmanuel Vadot			cpu-supply = <&vdd_cpu>;
1505f126890aSEmmanuel Vadot			operating-points-v2 = <&cpu0_opp_table>;
1506f126890aSEmmanuel Vadot			#cooling-cells = <2>;
1507f126890aSEmmanuel Vadot		};
1508f126890aSEmmanuel Vadot		cpu2: cpu@2 {
1509f126890aSEmmanuel Vadot			cpu-supply = <&vdd_cpu>;
1510f126890aSEmmanuel Vadot			operating-points-v2 = <&cpu0_opp_table>;
1511f126890aSEmmanuel Vadot			#cooling-cells = <2>;
1512f126890aSEmmanuel Vadot		};
1513f126890aSEmmanuel Vadot		cpu3: cpu@3 {
1514f126890aSEmmanuel Vadot			cpu-supply = <&vdd_cpu>;
1515f126890aSEmmanuel Vadot			operating-points-v2 = <&cpu0_opp_table>;
1516f126890aSEmmanuel Vadot			#cooling-cells = <2>;
1517f126890aSEmmanuel Vadot		};
1518f126890aSEmmanuel Vadot	};
1519f126890aSEmmanuel Vadot
1520f126890aSEmmanuel Vadot	extcon-keys {
1521f126890aSEmmanuel Vadot		compatible = "gpio-keys";
1522f126890aSEmmanuel Vadot
1523f126890aSEmmanuel Vadot		switch-dock-hall-sensor {
1524f126890aSEmmanuel Vadot			label = "Lid sensor";
1525f126890aSEmmanuel Vadot			gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>;
1526f126890aSEmmanuel Vadot			linux,input-type = <EV_SW>;
1527f126890aSEmmanuel Vadot			linux,code = <SW_LID>;
1528f126890aSEmmanuel Vadot			debounce-interval = <500>;
1529f126890aSEmmanuel Vadot			wakeup-event-action = <EV_ACT_ASSERTED>;
1530f126890aSEmmanuel Vadot			wakeup-source;
1531f126890aSEmmanuel Vadot		};
1532f126890aSEmmanuel Vadot
1533f126890aSEmmanuel Vadot		switch-lineout-detect {
1534f126890aSEmmanuel Vadot			label = "Audio dock line-out detect";
1535f126890aSEmmanuel Vadot			gpios = <&gpio TEGRA_GPIO(X, 3) GPIO_ACTIVE_LOW>;
1536f126890aSEmmanuel Vadot			linux,input-type = <EV_SW>;
1537f126890aSEmmanuel Vadot			linux,code = <SW_LINEOUT_INSERT>;
1538f126890aSEmmanuel Vadot			debounce-interval = <10>;
1539f126890aSEmmanuel Vadot			wakeup-event-action = <EV_ACT_ASSERTED>;
1540f126890aSEmmanuel Vadot			wakeup-source;
1541f126890aSEmmanuel Vadot		};
1542f126890aSEmmanuel Vadot	};
1543f126890aSEmmanuel Vadot
1544f126890aSEmmanuel Vadot	gpio-keys {
1545f126890aSEmmanuel Vadot		compatible = "gpio-keys";
1546f126890aSEmmanuel Vadot
1547f126890aSEmmanuel Vadot		key-power {
1548f126890aSEmmanuel Vadot			label = "Power";
1549f126890aSEmmanuel Vadot			gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>;
1550f126890aSEmmanuel Vadot			linux,code = <KEY_POWER>;
1551f126890aSEmmanuel Vadot			debounce-interval = <10>;
1552f126890aSEmmanuel Vadot			wakeup-event-action = <EV_ACT_ASSERTED>;
1553f126890aSEmmanuel Vadot			wakeup-source;
1554f126890aSEmmanuel Vadot		};
1555f126890aSEmmanuel Vadot
1556f126890aSEmmanuel Vadot		key-volume-down {
1557f126890aSEmmanuel Vadot			label = "Volume Down";
1558f126890aSEmmanuel Vadot			gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>;
1559f126890aSEmmanuel Vadot			linux,code = <KEY_VOLUMEDOWN>;
1560f126890aSEmmanuel Vadot			debounce-interval = <10>;
1561f126890aSEmmanuel Vadot			wakeup-event-action = <EV_ACT_ASSERTED>;
1562f126890aSEmmanuel Vadot			wakeup-source;
1563f126890aSEmmanuel Vadot		};
1564f126890aSEmmanuel Vadot
1565f126890aSEmmanuel Vadot		key-volume-up {
1566f126890aSEmmanuel Vadot			label = "Volume Up";
1567f126890aSEmmanuel Vadot			gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
1568f126890aSEmmanuel Vadot			linux,code = <KEY_VOLUMEUP>;
1569f126890aSEmmanuel Vadot			debounce-interval = <10>;
1570f126890aSEmmanuel Vadot			wakeup-event-action = <EV_ACT_ASSERTED>;
1571f126890aSEmmanuel Vadot			wakeup-source;
1572f126890aSEmmanuel Vadot		};
1573f126890aSEmmanuel Vadot	};
1574f126890aSEmmanuel Vadot
1575f126890aSEmmanuel Vadot	vdd_5v0_bat: regulator-bat {
1576f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1577f126890aSEmmanuel Vadot		regulator-name = "vdd_ac_bat";
1578f126890aSEmmanuel Vadot		regulator-min-microvolt = <5000000>;
1579f126890aSEmmanuel Vadot		regulator-max-microvolt = <5000000>;
1580f126890aSEmmanuel Vadot		regulator-always-on;
1581f126890aSEmmanuel Vadot		regulator-boot-on;
1582f126890aSEmmanuel Vadot	};
1583f126890aSEmmanuel Vadot
1584f126890aSEmmanuel Vadot	vdd_5v0_cp: regulator-sby {
1585f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1586f126890aSEmmanuel Vadot		regulator-name = "vdd_5v0_sby";
1587f126890aSEmmanuel Vadot		regulator-min-microvolt = <5000000>;
1588f126890aSEmmanuel Vadot		regulator-max-microvolt = <5000000>;
1589f126890aSEmmanuel Vadot		regulator-always-on;
1590f126890aSEmmanuel Vadot		regulator-boot-on;
1591f126890aSEmmanuel Vadot		gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
1592f126890aSEmmanuel Vadot		enable-active-high;
1593f126890aSEmmanuel Vadot		vin-supply = <&vdd_5v0_bat>;
1594f126890aSEmmanuel Vadot	};
1595f126890aSEmmanuel Vadot
1596f126890aSEmmanuel Vadot	vdd_5v0_sys: regulator-5v {
1597f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1598f126890aSEmmanuel Vadot		regulator-name = "vdd_5v0_sys";
1599f126890aSEmmanuel Vadot		regulator-min-microvolt = <5000000>;
1600f126890aSEmmanuel Vadot		regulator-max-microvolt = <5000000>;
1601f126890aSEmmanuel Vadot		regulator-always-on;
1602f126890aSEmmanuel Vadot		regulator-boot-on;
1603f126890aSEmmanuel Vadot		gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
1604f126890aSEmmanuel Vadot		enable-active-high;
1605f126890aSEmmanuel Vadot		vin-supply = <&vdd_5v0_bat>;
1606f126890aSEmmanuel Vadot	};
1607f126890aSEmmanuel Vadot
1608f126890aSEmmanuel Vadot	vdd_1v5_ddr: regulator-ddr {
1609f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1610f126890aSEmmanuel Vadot		regulator-name = "vdd_ddr";
1611f126890aSEmmanuel Vadot		regulator-min-microvolt = <1500000>;
1612f126890aSEmmanuel Vadot		regulator-max-microvolt = <1500000>;
1613f126890aSEmmanuel Vadot		regulator-always-on;
1614f126890aSEmmanuel Vadot		regulator-boot-on;
1615f126890aSEmmanuel Vadot		gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
1616f126890aSEmmanuel Vadot		enable-active-high;
1617f126890aSEmmanuel Vadot		vin-supply = <&vdd_5v0_bat>;
1618f126890aSEmmanuel Vadot	};
1619f126890aSEmmanuel Vadot
1620f126890aSEmmanuel Vadot	vdd_3v3_sys: regulator-3v {
1621f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1622f126890aSEmmanuel Vadot		regulator-name = "vdd_3v3_sys";
1623f126890aSEmmanuel Vadot		regulator-min-microvolt = <3300000>;
1624f126890aSEmmanuel Vadot		regulator-max-microvolt = <3300000>;
1625f126890aSEmmanuel Vadot		regulator-always-on;
1626f126890aSEmmanuel Vadot		regulator-boot-on;
1627f126890aSEmmanuel Vadot		gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
1628f126890aSEmmanuel Vadot		enable-active-high;
1629f126890aSEmmanuel Vadot		vin-supply = <&vdd_5v0_bat>;
1630f126890aSEmmanuel Vadot	};
1631f126890aSEmmanuel Vadot
1632f126890aSEmmanuel Vadot	vdd_pnl: regulator-panel {
1633f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1634f126890aSEmmanuel Vadot		regulator-name = "vdd_panel";
1635f126890aSEmmanuel Vadot		regulator-min-microvolt = <3300000>;
1636f126890aSEmmanuel Vadot		regulator-max-microvolt = <3300000>;
1637f126890aSEmmanuel Vadot		regulator-enable-ramp-delay = <20000>;
1638f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>;
1639f126890aSEmmanuel Vadot		enable-active-high;
1640f126890aSEmmanuel Vadot		vin-supply = <&vdd_3v3_sys>;
1641f126890aSEmmanuel Vadot	};
1642f126890aSEmmanuel Vadot
1643f126890aSEmmanuel Vadot	vdd_3v3_com: regulator-com {
1644f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1645f126890aSEmmanuel Vadot		regulator-name = "vdd_3v3_com";
1646f126890aSEmmanuel Vadot		regulator-min-microvolt = <3300000>;
1647f126890aSEmmanuel Vadot		regulator-max-microvolt = <3300000>;
1648f126890aSEmmanuel Vadot		regulator-always-on;
1649f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
1650f126890aSEmmanuel Vadot		enable-active-high;
1651f126890aSEmmanuel Vadot		vin-supply = <&vdd_3v3_sys>;
1652f126890aSEmmanuel Vadot	};
1653f126890aSEmmanuel Vadot
1654f126890aSEmmanuel Vadot	vdd_5v0_bl: regulator-bl {
1655f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1656f126890aSEmmanuel Vadot		regulator-name = "vdd_5v0_bl";
1657f126890aSEmmanuel Vadot		regulator-min-microvolt = <5000000>;
1658f126890aSEmmanuel Vadot		regulator-max-microvolt = <5000000>;
1659f126890aSEmmanuel Vadot		regulator-boot-on;
1660f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
1661f126890aSEmmanuel Vadot		enable-active-high;
1662f126890aSEmmanuel Vadot		vin-supply = <&vdd_5v0_bat>;
1663f126890aSEmmanuel Vadot	};
1664f126890aSEmmanuel Vadot
1665f126890aSEmmanuel Vadot	hdmi_5v0_sys: regulator-hdmi {
1666f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1667f126890aSEmmanuel Vadot		regulator-name = "hdmi_5v0_sys";
1668f126890aSEmmanuel Vadot		regulator-min-microvolt = <5000000>;
1669f126890aSEmmanuel Vadot		regulator-max-microvolt = <5000000>;
1670f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1671f126890aSEmmanuel Vadot		enable-active-high;
1672f126890aSEmmanuel Vadot		vin-supply = <&vdd_5v0_sys>;
1673f126890aSEmmanuel Vadot	};
1674f126890aSEmmanuel Vadot
1675f126890aSEmmanuel Vadot	sound {
1676f126890aSEmmanuel Vadot		nvidia,i2s-controller = <&tegra_i2s1>;
1677f126890aSEmmanuel Vadot
1678f126890aSEmmanuel Vadot		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1679f126890aSEmmanuel Vadot		nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_LOW>;
1680f126890aSEmmanuel Vadot		nvidia,coupled-mic-hp-det;
1681f126890aSEmmanuel Vadot
1682f126890aSEmmanuel Vadot		clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
1683f126890aSEmmanuel Vadot			 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1684f126890aSEmmanuel Vadot			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1685f126890aSEmmanuel Vadot		clock-names = "pll_a", "pll_a_out0", "mclk";
1686f126890aSEmmanuel Vadot
1687f126890aSEmmanuel Vadot		assigned-clocks = <&tegra_car TEGRA30_CLK_EXTERN1>,
1688f126890aSEmmanuel Vadot				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1689f126890aSEmmanuel Vadot
1690f126890aSEmmanuel Vadot		assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1691f126890aSEmmanuel Vadot					 <&tegra_car TEGRA30_CLK_EXTERN1>;
1692f126890aSEmmanuel Vadot	};
1693f126890aSEmmanuel Vadot
1694f126890aSEmmanuel Vadot	thermal-zones {
1695f126890aSEmmanuel Vadot		/*
1696f126890aSEmmanuel Vadot		 * NCT72 has two sensors:
1697f126890aSEmmanuel Vadot		 *
1698f126890aSEmmanuel Vadot		 *	0: internal that monitors ambient/skin temperature
1699f126890aSEmmanuel Vadot		 *	1: external that is connected to the CPU's diode
1700f126890aSEmmanuel Vadot		 *
1701f126890aSEmmanuel Vadot		 * Ideally we should use userspace thermal governor,
1702f126890aSEmmanuel Vadot		 * but it's a much more complex solution.  The "skin"
1703f126890aSEmmanuel Vadot		 * zone exists as a simpler solution which prevents
1704f126890aSEmmanuel Vadot		 * Transformers from getting too hot from a user's
1705f126890aSEmmanuel Vadot		 * tactile perspective. The CPU zone is intended to
1706f126890aSEmmanuel Vadot		 * protect silicon from damage.
1707f126890aSEmmanuel Vadot		 */
1708f126890aSEmmanuel Vadot
1709f126890aSEmmanuel Vadot		skin-thermal {
1710f126890aSEmmanuel Vadot			polling-delay-passive = <1000>; /* milliseconds */
1711f126890aSEmmanuel Vadot			polling-delay = <5000>; /* milliseconds */
1712f126890aSEmmanuel Vadot
1713f126890aSEmmanuel Vadot			thermal-sensors = <&nct72 0>;
1714f126890aSEmmanuel Vadot
1715f126890aSEmmanuel Vadot			trips {
1716f126890aSEmmanuel Vadot				trip0: skin-alert {
1717f126890aSEmmanuel Vadot					/* throttle at 57C until temperature drops to 56.8C */
1718f126890aSEmmanuel Vadot					temperature = <57000>;
1719f126890aSEmmanuel Vadot					hysteresis = <200>;
1720f126890aSEmmanuel Vadot					type = "passive";
1721f126890aSEmmanuel Vadot				};
1722f126890aSEmmanuel Vadot
1723f126890aSEmmanuel Vadot				trip1: skin-crit {
1724f126890aSEmmanuel Vadot					/* shut down at 65C */
1725f126890aSEmmanuel Vadot					temperature = <65000>;
1726f126890aSEmmanuel Vadot					hysteresis = <2000>;
1727f126890aSEmmanuel Vadot					type = "critical";
1728f126890aSEmmanuel Vadot				};
1729f126890aSEmmanuel Vadot			};
1730f126890aSEmmanuel Vadot
1731f126890aSEmmanuel Vadot			cooling-maps {
1732f126890aSEmmanuel Vadot				map0 {
1733f126890aSEmmanuel Vadot					trip = <&trip0>;
1734f126890aSEmmanuel Vadot					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1735f126890aSEmmanuel Vadot							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1736f126890aSEmmanuel Vadot							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1737f126890aSEmmanuel Vadot							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1738f126890aSEmmanuel Vadot							 <&actmon THERMAL_NO_LIMIT
1739f126890aSEmmanuel Vadot								  THERMAL_NO_LIMIT>;
1740f126890aSEmmanuel Vadot				};
1741f126890aSEmmanuel Vadot			};
1742f126890aSEmmanuel Vadot		};
1743f126890aSEmmanuel Vadot
1744f126890aSEmmanuel Vadot		cpu-thermal {
1745f126890aSEmmanuel Vadot			polling-delay-passive = <1000>; /* milliseconds */
1746f126890aSEmmanuel Vadot			polling-delay = <5000>; /* milliseconds */
1747f126890aSEmmanuel Vadot
1748f126890aSEmmanuel Vadot			thermal-sensors = <&nct72 1>;
1749f126890aSEmmanuel Vadot
1750f126890aSEmmanuel Vadot			trips {
1751f126890aSEmmanuel Vadot				trip2: cpu-alert {
1752f126890aSEmmanuel Vadot					/* throttle at 75C until temperature drops to 74.8C */
1753f126890aSEmmanuel Vadot					temperature = <75000>;
1754f126890aSEmmanuel Vadot					hysteresis = <200>;
1755f126890aSEmmanuel Vadot					type = "passive";
1756f126890aSEmmanuel Vadot				};
1757f126890aSEmmanuel Vadot
1758f126890aSEmmanuel Vadot				trip3: cpu-crit {
1759f126890aSEmmanuel Vadot					/* shut down at 90C */
1760f126890aSEmmanuel Vadot					temperature = <90000>;
1761f126890aSEmmanuel Vadot					hysteresis = <2000>;
1762f126890aSEmmanuel Vadot					type = "critical";
1763f126890aSEmmanuel Vadot				};
1764f126890aSEmmanuel Vadot			};
1765f126890aSEmmanuel Vadot
1766f126890aSEmmanuel Vadot			cooling-maps {
1767f126890aSEmmanuel Vadot				map1 {
1768f126890aSEmmanuel Vadot					trip = <&trip2>;
1769f126890aSEmmanuel Vadot					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1770f126890aSEmmanuel Vadot							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1771f126890aSEmmanuel Vadot							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1772f126890aSEmmanuel Vadot							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1773f126890aSEmmanuel Vadot							 <&actmon THERMAL_NO_LIMIT
1774f126890aSEmmanuel Vadot								  THERMAL_NO_LIMIT>;
1775f126890aSEmmanuel Vadot				};
1776f126890aSEmmanuel Vadot			};
1777f126890aSEmmanuel Vadot		};
1778f126890aSEmmanuel Vadot	};
1779f126890aSEmmanuel Vadot
1780f126890aSEmmanuel Vadot	brcm_wifi_pwrseq: wifi-pwrseq {
1781f126890aSEmmanuel Vadot		compatible = "mmc-pwrseq-simple";
1782f126890aSEmmanuel Vadot
1783f126890aSEmmanuel Vadot		clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>;
1784f126890aSEmmanuel Vadot		clock-names = "ext_clock";
1785f126890aSEmmanuel Vadot
1786f126890aSEmmanuel Vadot		reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>;
1787f126890aSEmmanuel Vadot		post-power-on-delay-ms = <300>;
1788f126890aSEmmanuel Vadot		power-off-delay-us = <300>;
1789f126890aSEmmanuel Vadot	};
1790f126890aSEmmanuel Vadot};
1791