xref: /freebsd-src/sys/contrib/device-tree/src/arm/nvidia/tegra114-roth.dts (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145)
1f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0
2f126890aSEmmanuel Vadot/dts-v1/;
3f126890aSEmmanuel Vadot
4f126890aSEmmanuel Vadot#include <dt-bindings/input/input.h>
5f126890aSEmmanuel Vadot#include "tegra114.dtsi"
6f126890aSEmmanuel Vadot
7f126890aSEmmanuel Vadot/ {
8f126890aSEmmanuel Vadot	model = "NVIDIA SHIELD";
9f126890aSEmmanuel Vadot	compatible = "nvidia,roth", "nvidia,tegra114";
10f126890aSEmmanuel Vadot
11f126890aSEmmanuel Vadot	chosen {
12f126890aSEmmanuel Vadot		/* SHIELD's bootloader's arguments need to be overridden */
13f126890aSEmmanuel Vadot		bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1";
14f126890aSEmmanuel Vadot		/* SHIELD's bootloader will place initrd at this address */
15f126890aSEmmanuel Vadot		linux,initrd-start = <0x82000000>;
16f126890aSEmmanuel Vadot		linux,initrd-end = <0x82800000>;
17f126890aSEmmanuel Vadot	};
18f126890aSEmmanuel Vadot
19f126890aSEmmanuel Vadot	aliases {
20f126890aSEmmanuel Vadot		serial0 = &uartd;
21f126890aSEmmanuel Vadot	};
22f126890aSEmmanuel Vadot
23f126890aSEmmanuel Vadot	firmware {
24f126890aSEmmanuel Vadot		trusted-foundations {
25f126890aSEmmanuel Vadot			compatible = "tlm,trusted-foundations";
26f126890aSEmmanuel Vadot			tlm,version-major = <2>;
27f126890aSEmmanuel Vadot			tlm,version-minor = <8>;
28f126890aSEmmanuel Vadot		};
29f126890aSEmmanuel Vadot	};
30f126890aSEmmanuel Vadot
31f126890aSEmmanuel Vadot	memory@80000000 {
32f126890aSEmmanuel Vadot		/* memory >= 0x79600000 is reserved for firmware usage */
33f126890aSEmmanuel Vadot		reg = <0x80000000 0x79600000>;
34f126890aSEmmanuel Vadot	};
35f126890aSEmmanuel Vadot
36f126890aSEmmanuel Vadot	host1x@50000000 {
37f126890aSEmmanuel Vadot		dsi@54300000 {
38f126890aSEmmanuel Vadot			status = "okay";
39f126890aSEmmanuel Vadot
40f126890aSEmmanuel Vadot			avdd-dsi-csi-supply = <&vdd_1v2_ap>;
41f126890aSEmmanuel Vadot
42f126890aSEmmanuel Vadot			panel@0 {
43f126890aSEmmanuel Vadot				compatible = "lg,lh500wx1-sd03";
44f126890aSEmmanuel Vadot				reg = <0>;
45f126890aSEmmanuel Vadot
46f126890aSEmmanuel Vadot				power-supply = <&vdd_lcd>;
47f126890aSEmmanuel Vadot				backlight = <&backlight>;
48f126890aSEmmanuel Vadot			};
49f126890aSEmmanuel Vadot		};
50f126890aSEmmanuel Vadot	};
51f126890aSEmmanuel Vadot
52f126890aSEmmanuel Vadot	pinmux@70000868 {
53f126890aSEmmanuel Vadot		pinctrl-names = "default";
54f126890aSEmmanuel Vadot		pinctrl-0 = <&state_default>;
55f126890aSEmmanuel Vadot
56f126890aSEmmanuel Vadot		state_default: pinmux {
57f126890aSEmmanuel Vadot			clk1_out_pw4 {
58f126890aSEmmanuel Vadot				nvidia,pins = "clk1_out_pw4";
59f126890aSEmmanuel Vadot				nvidia,function = "extperiph1";
60f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
61f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
62f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
63f126890aSEmmanuel Vadot			};
64f126890aSEmmanuel Vadot			dap1_din_pn1 {
65f126890aSEmmanuel Vadot				nvidia,pins = "dap1_din_pn1";
66f126890aSEmmanuel Vadot				nvidia,function = "i2s0";
67f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
69f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
70f126890aSEmmanuel Vadot			};
71f126890aSEmmanuel Vadot			dap1_dout_pn2 {
72f126890aSEmmanuel Vadot				nvidia,pins = "dap1_dout_pn2",
73f126890aSEmmanuel Vadot						"dap1_fs_pn0",
74f126890aSEmmanuel Vadot						"dap1_sclk_pn3";
75f126890aSEmmanuel Vadot				nvidia,function = "i2s0";
76f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
77f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
78f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
79f126890aSEmmanuel Vadot			};
80f126890aSEmmanuel Vadot			dap2_din_pa4 {
81f126890aSEmmanuel Vadot				nvidia,pins = "dap2_din_pa4";
82f126890aSEmmanuel Vadot				nvidia,function = "i2s1";
83f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
84f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
85f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86f126890aSEmmanuel Vadot			};
87f126890aSEmmanuel Vadot			dap2_dout_pa5 {
88f126890aSEmmanuel Vadot				nvidia,pins = "dap2_dout_pa5",
89f126890aSEmmanuel Vadot						"dap2_fs_pa2",
90f126890aSEmmanuel Vadot						"dap2_sclk_pa3";
91f126890aSEmmanuel Vadot				nvidia,function = "i2s1";
92f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
94f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
95f126890aSEmmanuel Vadot			};
96f126890aSEmmanuel Vadot			dap4_din_pp5 {
97f126890aSEmmanuel Vadot				nvidia,pins = "dap4_din_pp5",
98f126890aSEmmanuel Vadot						"dap4_dout_pp6",
99f126890aSEmmanuel Vadot						"dap4_fs_pp4",
100f126890aSEmmanuel Vadot						"dap4_sclk_pp7";
101f126890aSEmmanuel Vadot				nvidia,function = "i2s3";
102f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
104f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
105f126890aSEmmanuel Vadot			};
106f126890aSEmmanuel Vadot			dvfs_pwm_px0 {
107f126890aSEmmanuel Vadot				nvidia,pins = "dvfs_pwm_px0",
108f126890aSEmmanuel Vadot						"dvfs_clk_px2";
109f126890aSEmmanuel Vadot				nvidia,function = "cldvfs";
110f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
112f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
113f126890aSEmmanuel Vadot			};
114f126890aSEmmanuel Vadot			ulpi_clk_py0 {
115f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_clk_py0",
116f126890aSEmmanuel Vadot						"ulpi_data0_po1",
117f126890aSEmmanuel Vadot						"ulpi_data1_po2",
118f126890aSEmmanuel Vadot						"ulpi_data2_po3",
119f126890aSEmmanuel Vadot						"ulpi_data3_po4",
120f126890aSEmmanuel Vadot						"ulpi_data4_po5",
121f126890aSEmmanuel Vadot						"ulpi_data5_po6",
122f126890aSEmmanuel Vadot						"ulpi_data6_po7",
123f126890aSEmmanuel Vadot						"ulpi_data7_po0";
124f126890aSEmmanuel Vadot				nvidia,function = "ulpi";
125f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
126f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
127f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
128f126890aSEmmanuel Vadot			};
129f126890aSEmmanuel Vadot			ulpi_dir_py1 {
130f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_dir_py1",
131f126890aSEmmanuel Vadot						"ulpi_nxt_py2";
132f126890aSEmmanuel Vadot				nvidia,function = "ulpi";
133f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
134f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
135f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
136f126890aSEmmanuel Vadot			};
137f126890aSEmmanuel Vadot			ulpi_stp_py3 {
138f126890aSEmmanuel Vadot				nvidia,pins = "ulpi_stp_py3";
139f126890aSEmmanuel Vadot				nvidia,function = "ulpi";
140f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
141f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
142f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
143f126890aSEmmanuel Vadot			};
144f126890aSEmmanuel Vadot			cam_i2c_scl_pbb1 {
145f126890aSEmmanuel Vadot				nvidia,pins = "cam_i2c_scl_pbb1",
146f126890aSEmmanuel Vadot						"cam_i2c_sda_pbb2";
147f126890aSEmmanuel Vadot				nvidia,function = "i2c3";
148f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
150f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
151f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
152f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
153f126890aSEmmanuel Vadot			};
154f126890aSEmmanuel Vadot			cam_mclk_pcc0 {
155f126890aSEmmanuel Vadot				nvidia,pins = "cam_mclk_pcc0",
156f126890aSEmmanuel Vadot						"pbb0";
157f126890aSEmmanuel Vadot				nvidia,function = "vi_alt3";
158f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
159f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
160f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
161f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
162f126890aSEmmanuel Vadot			};
163f126890aSEmmanuel Vadot			pbb4 {
164f126890aSEmmanuel Vadot				nvidia,pins = "pbb4";
165f126890aSEmmanuel Vadot				nvidia,function = "vgp4";
166f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
167f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
168f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
169f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
170f126890aSEmmanuel Vadot			};
171f126890aSEmmanuel Vadot			gen2_i2c_scl_pt5 {
172f126890aSEmmanuel Vadot				nvidia,pins = "gen2_i2c_scl_pt5",
173f126890aSEmmanuel Vadot						"gen2_i2c_sda_pt6";
174f126890aSEmmanuel Vadot				nvidia,function = "i2c2";
175f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
176f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
177f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
178f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
179f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
180f126890aSEmmanuel Vadot			};
181f126890aSEmmanuel Vadot			gmi_a16_pj7 {
182f126890aSEmmanuel Vadot				nvidia,pins = "gmi_a16_pj7",
183f126890aSEmmanuel Vadot						"gmi_a19_pk7";
184f126890aSEmmanuel Vadot				nvidia,function = "uartd";
185f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
186f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
187f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
188f126890aSEmmanuel Vadot			};
189f126890aSEmmanuel Vadot			gmi_a17_pb0 {
190f126890aSEmmanuel Vadot				nvidia,pins = "gmi_a17_pb0",
191f126890aSEmmanuel Vadot						"gmi_a18_pb1";
192f126890aSEmmanuel Vadot				nvidia,function = "uartd";
193f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
194f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
195f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
196f126890aSEmmanuel Vadot			};
197f126890aSEmmanuel Vadot			gmi_ad5_pg5 {
198f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad5_pg5",
199f126890aSEmmanuel Vadot						"gmi_wr_n_pi0";
200f126890aSEmmanuel Vadot				nvidia,function = "spi4";
201f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
203f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
204f126890aSEmmanuel Vadot			};
205f126890aSEmmanuel Vadot			gmi_ad6_pg6 {
206f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad6_pg6",
207f126890aSEmmanuel Vadot						"gmi_ad7_pg7";
208f126890aSEmmanuel Vadot				nvidia,function = "spi4";
209f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
210f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
211f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
212f126890aSEmmanuel Vadot			};
213f126890aSEmmanuel Vadot			gmi_ad12_ph4 {
214f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad12_ph4";
215f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
216f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
217f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
218f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
219f126890aSEmmanuel Vadot			};
220f126890aSEmmanuel Vadot			gmi_cs6_n_pi13 {
221f126890aSEmmanuel Vadot				nvidia,pins = "gmi_cs6_n_pi3";
222f126890aSEmmanuel Vadot				nvidia,function = "nand";
223f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
224f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
225f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
226f126890aSEmmanuel Vadot			};
227f126890aSEmmanuel Vadot			gmi_ad9_ph1 {
228f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad9_ph1";
229f126890aSEmmanuel Vadot				nvidia,function = "pwm1";
230f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
231f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
232f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
233f126890aSEmmanuel Vadot			};
234f126890aSEmmanuel Vadot			gmi_cs1_n_pj2 {
235f126890aSEmmanuel Vadot				nvidia,pins = "gmi_cs1_n_pj2",
236f126890aSEmmanuel Vadot						"gmi_oe_n_pi1";
237f126890aSEmmanuel Vadot				nvidia,function = "soc";
238f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
239f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
240f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
241f126890aSEmmanuel Vadot			};
242f126890aSEmmanuel Vadot			gmi_rst_n_pi4 {
243f126890aSEmmanuel Vadot				nvidia,pins = "gmi_rst_n_pi4";
244f126890aSEmmanuel Vadot				nvidia,function = "gmi";
245f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
246f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
247f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248f126890aSEmmanuel Vadot			};
249f126890aSEmmanuel Vadot			gmi_iordy_pi5 {
250f126890aSEmmanuel Vadot				nvidia,pins = "gmi_iordy_pi5";
251f126890aSEmmanuel Vadot				nvidia,function = "gmi";
252f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
254f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
255f126890aSEmmanuel Vadot			};
256f126890aSEmmanuel Vadot			clk2_out_pw5 {
257f126890aSEmmanuel Vadot				nvidia,pins = "clk2_out_pw5";
258f126890aSEmmanuel Vadot				nvidia,function = "extperiph2";
259f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
260f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
261f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
262f126890aSEmmanuel Vadot			};
263f126890aSEmmanuel Vadot			sdmmc1_clk_pz0 {
264f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc1_clk_pz0";
265f126890aSEmmanuel Vadot				nvidia,function = "sdmmc1";
266f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
267f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
268f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
269f126890aSEmmanuel Vadot			};
270f126890aSEmmanuel Vadot			sdmmc1_cmd_pz1 {
271f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc1_cmd_pz1",
272f126890aSEmmanuel Vadot						"sdmmc1_dat0_py7",
273f126890aSEmmanuel Vadot						"sdmmc1_dat1_py6",
274f126890aSEmmanuel Vadot						"sdmmc1_dat2_py5",
275f126890aSEmmanuel Vadot						"sdmmc1_dat3_py4";
276f126890aSEmmanuel Vadot				nvidia,function = "sdmmc1";
277f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
278f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
279f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
280f126890aSEmmanuel Vadot			};
281f126890aSEmmanuel Vadot			sdmmc3_clk_pa6 {
282f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc3_clk_pa6";
283f126890aSEmmanuel Vadot				nvidia,function = "sdmmc3";
284f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
285f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
286f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
287f126890aSEmmanuel Vadot			};
288f126890aSEmmanuel Vadot			sdmmc3_cmd_pa7 {
289f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc3_cmd_pa7",
290f126890aSEmmanuel Vadot						"sdmmc3_dat0_pb7",
291f126890aSEmmanuel Vadot						"sdmmc3_dat1_pb6",
292f126890aSEmmanuel Vadot						"sdmmc3_dat2_pb5",
293f126890aSEmmanuel Vadot						"sdmmc3_dat3_pb4",
294f126890aSEmmanuel Vadot						"sdmmc3_cd_n_pv2",
295f126890aSEmmanuel Vadot						"sdmmc3_clk_lb_out_pee4",
296f126890aSEmmanuel Vadot						"sdmmc3_clk_lb_in_pee5";
297f126890aSEmmanuel Vadot				nvidia,function = "sdmmc3";
298f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
299f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
300f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
301f126890aSEmmanuel Vadot			};
302f126890aSEmmanuel Vadot			kb_col4_pq4 {
303f126890aSEmmanuel Vadot				nvidia,pins = "kb_col4_pq4";
304f126890aSEmmanuel Vadot				nvidia,function = "sdmmc3";
305f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
306f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
307f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
308f126890aSEmmanuel Vadot			};
309f126890aSEmmanuel Vadot			sdmmc4_clk_pcc4 {
310f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc4_clk_pcc4";
311f126890aSEmmanuel Vadot				nvidia,function = "sdmmc4";
312f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
313f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
314f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
315f126890aSEmmanuel Vadot			};
316f126890aSEmmanuel Vadot			sdmmc4_cmd_pt7 {
317f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc4_cmd_pt7",
318f126890aSEmmanuel Vadot						"sdmmc4_dat0_paa0",
319f126890aSEmmanuel Vadot						"sdmmc4_dat1_paa1",
320f126890aSEmmanuel Vadot						"sdmmc4_dat2_paa2",
321f126890aSEmmanuel Vadot						"sdmmc4_dat3_paa3",
322f126890aSEmmanuel Vadot						"sdmmc4_dat4_paa4",
323f126890aSEmmanuel Vadot						"sdmmc4_dat5_paa5",
324f126890aSEmmanuel Vadot						"sdmmc4_dat6_paa6",
325f126890aSEmmanuel Vadot						"sdmmc4_dat7_paa7";
326f126890aSEmmanuel Vadot				nvidia,function = "sdmmc4";
327f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
328f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
329f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
330f126890aSEmmanuel Vadot			};
331f126890aSEmmanuel Vadot			clk_32k_out_pa0 {
332f126890aSEmmanuel Vadot				nvidia,pins = "clk_32k_out_pa0";
333f126890aSEmmanuel Vadot				nvidia,function = "blink";
334f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
335f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
336f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
337f126890aSEmmanuel Vadot			};
338f126890aSEmmanuel Vadot			kb_col0_pq0 {
339f126890aSEmmanuel Vadot				nvidia,pins = "kb_col0_pq0",
340f126890aSEmmanuel Vadot						"kb_col1_pq1",
341f126890aSEmmanuel Vadot						"kb_col2_pq2",
342f126890aSEmmanuel Vadot						"kb_row0_pr0",
343f126890aSEmmanuel Vadot						"kb_row1_pr1",
344f126890aSEmmanuel Vadot						"kb_row2_pr2",
345f126890aSEmmanuel Vadot						"kb_row8_ps0";
346f126890aSEmmanuel Vadot				nvidia,function = "kbc";
347f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
348f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
349f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
350f126890aSEmmanuel Vadot			};
351f126890aSEmmanuel Vadot			kb_row7_pr7 {
352f126890aSEmmanuel Vadot				nvidia,pins = "kb_row7_pr7";
353f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
354f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
355f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
356f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
357f126890aSEmmanuel Vadot			};
358f126890aSEmmanuel Vadot			kb_row10_ps2 {
359f126890aSEmmanuel Vadot				nvidia,pins = "kb_row10_ps2";
360f126890aSEmmanuel Vadot				nvidia,function = "uarta";
361f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
363f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
364f126890aSEmmanuel Vadot			};
365f126890aSEmmanuel Vadot			kb_row9_ps1 {
366f126890aSEmmanuel Vadot				nvidia,pins = "kb_row9_ps1";
367f126890aSEmmanuel Vadot				nvidia,function = "uarta";
368f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
369f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
370f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
371f126890aSEmmanuel Vadot			};
372f126890aSEmmanuel Vadot			pwr_i2c_scl_pz6 {
373f126890aSEmmanuel Vadot				nvidia,pins = "pwr_i2c_scl_pz6",
374f126890aSEmmanuel Vadot						"pwr_i2c_sda_pz7";
375f126890aSEmmanuel Vadot				nvidia,function = "i2cpwr";
376f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
378f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
379f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
380f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
381f126890aSEmmanuel Vadot			};
382f126890aSEmmanuel Vadot			sys_clk_req_pz5 {
383f126890aSEmmanuel Vadot				nvidia,pins = "sys_clk_req_pz5";
384f126890aSEmmanuel Vadot				nvidia,function = "sysclk";
385f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
386f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
387f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
388f126890aSEmmanuel Vadot			};
389f126890aSEmmanuel Vadot			core_pwr_req {
390f126890aSEmmanuel Vadot				nvidia,pins = "core_pwr_req";
391f126890aSEmmanuel Vadot				nvidia,function = "pwron";
392f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
394f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
395f126890aSEmmanuel Vadot			};
396f126890aSEmmanuel Vadot			cpu_pwr_req {
397f126890aSEmmanuel Vadot				nvidia,pins = "cpu_pwr_req";
398f126890aSEmmanuel Vadot				nvidia,function = "cpu";
399f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
401f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
402f126890aSEmmanuel Vadot			};
403f126890aSEmmanuel Vadot			pwr_int_n {
404f126890aSEmmanuel Vadot				nvidia,pins = "pwr_int_n";
405f126890aSEmmanuel Vadot				nvidia,function = "pmi";
406f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
407f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
408f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
409f126890aSEmmanuel Vadot			};
410f126890aSEmmanuel Vadot			reset_out_n {
411f126890aSEmmanuel Vadot				nvidia,pins = "reset_out_n";
412f126890aSEmmanuel Vadot				nvidia,function = "reset_out_n";
413f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
415f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
416f126890aSEmmanuel Vadot			};
417f126890aSEmmanuel Vadot			clk3_out_pee0 {
418f126890aSEmmanuel Vadot				nvidia,pins = "clk3_out_pee0";
419f126890aSEmmanuel Vadot				nvidia,function = "extperiph3";
420f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
422f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
423f126890aSEmmanuel Vadot			};
424f126890aSEmmanuel Vadot			gen1_i2c_scl_pc4 {
425f126890aSEmmanuel Vadot				nvidia,pins = "gen1_i2c_scl_pc4",
426f126890aSEmmanuel Vadot						"gen1_i2c_sda_pc5";
427f126890aSEmmanuel Vadot				nvidia,function = "i2c1";
428f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
429f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
430f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
431f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
432f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
433f126890aSEmmanuel Vadot			};
434f126890aSEmmanuel Vadot			uart2_cts_n_pj5 {
435f126890aSEmmanuel Vadot				nvidia,pins = "uart2_cts_n_pj5";
436f126890aSEmmanuel Vadot				nvidia,function = "uartb";
437f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
438f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
439f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
440f126890aSEmmanuel Vadot			};
441f126890aSEmmanuel Vadot			uart2_rts_n_pj6 {
442f126890aSEmmanuel Vadot				nvidia,pins = "uart2_rts_n_pj6";
443f126890aSEmmanuel Vadot				nvidia,function = "uartb";
444f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
445f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
446f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
447f126890aSEmmanuel Vadot			};
448f126890aSEmmanuel Vadot			uart2_rxd_pc3 {
449f126890aSEmmanuel Vadot				nvidia,pins = "uart2_rxd_pc3";
450f126890aSEmmanuel Vadot				nvidia,function = "irda";
451f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
452f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
453f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
454f126890aSEmmanuel Vadot			};
455f126890aSEmmanuel Vadot			uart2_txd_pc2 {
456f126890aSEmmanuel Vadot				nvidia,pins = "uart2_txd_pc2";
457f126890aSEmmanuel Vadot				nvidia,function = "irda";
458f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
459f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
460f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
461f126890aSEmmanuel Vadot			};
462f126890aSEmmanuel Vadot			uart3_cts_n_pa1 {
463f126890aSEmmanuel Vadot				nvidia,pins = "uart3_cts_n_pa1",
464f126890aSEmmanuel Vadot						"uart3_rxd_pw7";
465f126890aSEmmanuel Vadot				nvidia,function = "uartc";
466f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
467f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
468f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
469f126890aSEmmanuel Vadot			};
470f126890aSEmmanuel Vadot			uart3_rts_n_pc0 {
471f126890aSEmmanuel Vadot				nvidia,pins = "uart3_rts_n_pc0",
472f126890aSEmmanuel Vadot						"uart3_txd_pw6";
473f126890aSEmmanuel Vadot				nvidia,function = "uartc";
474f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
475f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
476f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
477f126890aSEmmanuel Vadot			};
478f126890aSEmmanuel Vadot			owr {
479f126890aSEmmanuel Vadot				nvidia,pins = "owr";
480f126890aSEmmanuel Vadot				nvidia,function = "owr";
481f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
482f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
483f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
484f126890aSEmmanuel Vadot			};
485f126890aSEmmanuel Vadot			hdmi_cec_pee3 {
486f126890aSEmmanuel Vadot				nvidia,pins = "hdmi_cec_pee3";
487f126890aSEmmanuel Vadot				nvidia,function = "cec";
488f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
489f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
490f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
491f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
492f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
493f126890aSEmmanuel Vadot			};
494f126890aSEmmanuel Vadot			ddc_scl_pv4 {
495f126890aSEmmanuel Vadot				nvidia,pins = "ddc_scl_pv4",
496f126890aSEmmanuel Vadot						"ddc_sda_pv5";
497f126890aSEmmanuel Vadot				nvidia,function = "i2c4";
498f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
499f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
500f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
501f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
502f126890aSEmmanuel Vadot				nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
503f126890aSEmmanuel Vadot			};
504f126890aSEmmanuel Vadot			spdif_in_pk6 {
505f126890aSEmmanuel Vadot				nvidia,pins = "spdif_in_pk6";
506f126890aSEmmanuel Vadot				nvidia,function = "usb";
507f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
508f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
509f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
510f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
511f126890aSEmmanuel Vadot			};
512f126890aSEmmanuel Vadot			usb_vbus_en0_pn4 {
513f126890aSEmmanuel Vadot				nvidia,pins = "usb_vbus_en0_pn4";
514f126890aSEmmanuel Vadot				nvidia,function = "usb";
515f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
516f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
517f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
518f126890aSEmmanuel Vadot				nvidia,lock = <TEGRA_PIN_DISABLE>;
519f126890aSEmmanuel Vadot				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
520f126890aSEmmanuel Vadot			};
521f126890aSEmmanuel Vadot			gpio_x6_aud_px6 {
522f126890aSEmmanuel Vadot				nvidia,pins = "gpio_x6_aud_px6";
523f126890aSEmmanuel Vadot				nvidia,function = "spi6";
524f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
525f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
526f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
527f126890aSEmmanuel Vadot			};
528f126890aSEmmanuel Vadot			gpio_x1_aud_px1 {
529f126890aSEmmanuel Vadot				nvidia,pins = "gpio_x1_aud_px1";
530f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
531f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
532f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
533f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
534f126890aSEmmanuel Vadot			};
535f126890aSEmmanuel Vadot			gpio_x7_aud_px7 {
536f126890aSEmmanuel Vadot				nvidia,pins = "gpio_x7_aud_px7";
537f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
538f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
539f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
540f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
541f126890aSEmmanuel Vadot			};
542f126890aSEmmanuel Vadot			gmi_adv_n_pk0 {
543f126890aSEmmanuel Vadot				nvidia,pins = "gmi_adv_n_pk0";
544f126890aSEmmanuel Vadot				nvidia,function = "gmi";
545f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
546f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_ENABLE>;
547f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
548f126890aSEmmanuel Vadot			};
549f126890aSEmmanuel Vadot			gmi_cs0_n_pj0 {
550f126890aSEmmanuel Vadot				nvidia,pins = "gmi_cs0_n_pj0";
551f126890aSEmmanuel Vadot				nvidia,function = "gmi";
552f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
553f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
554f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
555f126890aSEmmanuel Vadot			};
556f126890aSEmmanuel Vadot			pu3 {
557f126890aSEmmanuel Vadot				nvidia,pins = "pu3";
558f126890aSEmmanuel Vadot				nvidia,function = "pwm0";
559f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
560f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
561f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
562f126890aSEmmanuel Vadot			};
563f126890aSEmmanuel Vadot			gpio_x4_aud_px4 {
564f126890aSEmmanuel Vadot				nvidia,pins = "gpio_x4_aud_px4",
565f126890aSEmmanuel Vadot						"gpio_x5_aud_px5";
566f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
567f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
568f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
569f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
570f126890aSEmmanuel Vadot			};
571f126890aSEmmanuel Vadot			gpio_x3_aud_px3 {
572f126890aSEmmanuel Vadot				nvidia,pins = "gpio_x3_aud_px3";
573f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
574f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
575f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
576f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
577f126890aSEmmanuel Vadot			};
578f126890aSEmmanuel Vadot			gpio_w2_aud_pw2 {
579f126890aSEmmanuel Vadot				nvidia,pins = "gpio_w2_aud_pw2";
580f126890aSEmmanuel Vadot				nvidia,function = "rsvd2";
581f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
582f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
583f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
584f126890aSEmmanuel Vadot			};
585f126890aSEmmanuel Vadot			gpio_w3_aud_pw3 {
586f126890aSEmmanuel Vadot				nvidia,pins = "gpio_w3_aud_pw3";
587f126890aSEmmanuel Vadot				nvidia,function = "spi6";
588f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
589f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
590f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
591f126890aSEmmanuel Vadot			};
592f126890aSEmmanuel Vadot			dap3_fs_pp0 {
593f126890aSEmmanuel Vadot				nvidia,pins = "dap3_fs_pp0",
594f126890aSEmmanuel Vadot						"dap3_din_pp1",
595f126890aSEmmanuel Vadot						"dap3_dout_pp2",
596f126890aSEmmanuel Vadot						"dap3_sclk_pp3";
597f126890aSEmmanuel Vadot				nvidia,function = "i2s2";
598f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
599f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
600f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
601f126890aSEmmanuel Vadot			};
602f126890aSEmmanuel Vadot			pv0 {
603f126890aSEmmanuel Vadot				nvidia,pins = "pv0";
604f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
605f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
606f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
607f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
608f126890aSEmmanuel Vadot			};
609f126890aSEmmanuel Vadot			pv1 {
610f126890aSEmmanuel Vadot				nvidia,pins = "pv1";
611f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
612f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
613f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
614f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
615f126890aSEmmanuel Vadot			};
616f126890aSEmmanuel Vadot			pbb3 {
617f126890aSEmmanuel Vadot				nvidia,pins = "pbb3",
618f126890aSEmmanuel Vadot						"pbb5",
619f126890aSEmmanuel Vadot						"pbb6",
620f126890aSEmmanuel Vadot						"pbb7";
621f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
622f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
623f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
624f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
625f126890aSEmmanuel Vadot			};
626f126890aSEmmanuel Vadot			pcc1 {
627f126890aSEmmanuel Vadot				nvidia,pins = "pcc1",
628f126890aSEmmanuel Vadot						"pcc2";
629f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
630f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
631f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
632f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
633f126890aSEmmanuel Vadot			};
634f126890aSEmmanuel Vadot			gmi_ad0_pg0 {
635f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad0_pg0",
636f126890aSEmmanuel Vadot						"gmi_ad1_pg1";
637f126890aSEmmanuel Vadot				nvidia,function = "gmi";
638f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
639f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
640f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
641f126890aSEmmanuel Vadot			};
642f126890aSEmmanuel Vadot			gmi_ad10_ph2 {
643f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad10_ph2",
644f126890aSEmmanuel Vadot						"gmi_ad12_ph4",
645f126890aSEmmanuel Vadot						"gmi_ad15_ph7",
646f126890aSEmmanuel Vadot						"gmi_cs3_n_pk4";
647f126890aSEmmanuel Vadot				nvidia,function = "gmi";
648f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
649f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
650f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
651f126890aSEmmanuel Vadot			};
652f126890aSEmmanuel Vadot			gmi_ad11_ph3 {
653f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad11_ph3",
654f126890aSEmmanuel Vadot						"gmi_ad13_ph5",
655f126890aSEmmanuel Vadot						"gmi_ad8_ph0",
656f126890aSEmmanuel Vadot						"gmi_clk_pk1",
657f126890aSEmmanuel Vadot						"gmi_cs2_n_pk3";
658f126890aSEmmanuel Vadot				nvidia,function = "gmi";
659f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
660f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
661f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
662f126890aSEmmanuel Vadot			};
663f126890aSEmmanuel Vadot			gmi_ad14_ph6 {
664f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad14_ph6",
665f126890aSEmmanuel Vadot						"gmi_cs0_n_pj0",
666f126890aSEmmanuel Vadot						"gmi_cs4_n_pk2",
667f126890aSEmmanuel Vadot						"gmi_cs7_n_pi6",
668f126890aSEmmanuel Vadot						"gmi_dqs_p_pj3",
669f126890aSEmmanuel Vadot						"gmi_wp_n_pc7";
670f126890aSEmmanuel Vadot				nvidia,function = "gmi";
671f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
672f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
673f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
674f126890aSEmmanuel Vadot			};
675f126890aSEmmanuel Vadot			gmi_ad2_pg2 {
676f126890aSEmmanuel Vadot				nvidia,pins = "gmi_ad2_pg2",
677f126890aSEmmanuel Vadot						"gmi_ad3_pg3";
678f126890aSEmmanuel Vadot				nvidia,function = "gmi";
679f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
680f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
681f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
682f126890aSEmmanuel Vadot			};
683f126890aSEmmanuel Vadot			sdmmc1_wp_n_pv3 {
684f126890aSEmmanuel Vadot				nvidia,pins = "sdmmc1_wp_n_pv3";
685f126890aSEmmanuel Vadot				nvidia,function = "spi4";
686f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
687f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
688f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
689f126890aSEmmanuel Vadot			};
690f126890aSEmmanuel Vadot			clk2_req_pcc5 {
691f126890aSEmmanuel Vadot				nvidia,pins = "clk2_req_pcc5";
692f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
693f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
694f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
695f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
696f126890aSEmmanuel Vadot			};
697f126890aSEmmanuel Vadot			kb_col3_pq3 {
698f126890aSEmmanuel Vadot				nvidia,pins = "kb_col3_pq3";
699f126890aSEmmanuel Vadot				nvidia,function = "pwm2";
700f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
701f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
702f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
703f126890aSEmmanuel Vadot			};
704f126890aSEmmanuel Vadot			kb_col5_pq5 {
705f126890aSEmmanuel Vadot				nvidia,pins = "kb_col5_pq5";
706f126890aSEmmanuel Vadot				nvidia,function = "kbc";
707f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
708f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
709f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
710f126890aSEmmanuel Vadot			};
711f126890aSEmmanuel Vadot			kb_col6_pq6 {
712f126890aSEmmanuel Vadot				nvidia,pins = "kb_col6_pq6",
713f126890aSEmmanuel Vadot						"kb_col7_pq7";
714f126890aSEmmanuel Vadot				nvidia,function = "kbc";
715f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
716f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
717f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
718f126890aSEmmanuel Vadot			};
719f126890aSEmmanuel Vadot			kb_row3_pr3 {
720f126890aSEmmanuel Vadot				nvidia,pins = "kb_row3_pr3",
721f126890aSEmmanuel Vadot						"kb_row4_pr4",
722f126890aSEmmanuel Vadot						"kb_row6_pr6";
723f126890aSEmmanuel Vadot				nvidia,function = "kbc";
724f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
725f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
726f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
727f126890aSEmmanuel Vadot			};
728f126890aSEmmanuel Vadot			clk3_req_pee1 {
729f126890aSEmmanuel Vadot				nvidia,pins = "clk3_req_pee1";
730f126890aSEmmanuel Vadot				nvidia,function = "rsvd4";
731f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
732f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
733f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
734f126890aSEmmanuel Vadot			};
735f126890aSEmmanuel Vadot			pu2 {
736f126890aSEmmanuel Vadot				nvidia,pins = "pu2";
737f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
738f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_UP>;
739f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
740f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
741f126890aSEmmanuel Vadot			};
742f126890aSEmmanuel Vadot			hdmi_int_pn7 {
743f126890aSEmmanuel Vadot				nvidia,pins = "hdmi_int_pn7";
744f126890aSEmmanuel Vadot				nvidia,function = "rsvd1";
745f126890aSEmmanuel Vadot				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
746f126890aSEmmanuel Vadot				nvidia,tristate = <TEGRA_PIN_DISABLE>;
747f126890aSEmmanuel Vadot				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
748f126890aSEmmanuel Vadot			};
749f126890aSEmmanuel Vadot
750f126890aSEmmanuel Vadot			drive_sdio1 {
751f126890aSEmmanuel Vadot				nvidia,pins = "drive_sdio1";
752f126890aSEmmanuel Vadot				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
753f126890aSEmmanuel Vadot				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
754f126890aSEmmanuel Vadot				nvidia,pull-down-strength = <36>;
755f126890aSEmmanuel Vadot				nvidia,pull-up-strength = <20>;
756f126890aSEmmanuel Vadot				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
757f126890aSEmmanuel Vadot				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
758f126890aSEmmanuel Vadot			};
759f126890aSEmmanuel Vadot			drive_sdio3 {
760f126890aSEmmanuel Vadot				nvidia,pins = "drive_sdio3";
761f126890aSEmmanuel Vadot				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
762f126890aSEmmanuel Vadot				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
763f126890aSEmmanuel Vadot				nvidia,pull-down-strength = <36>;
764f126890aSEmmanuel Vadot				nvidia,pull-up-strength = <20>;
765f126890aSEmmanuel Vadot				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
766f126890aSEmmanuel Vadot				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
767f126890aSEmmanuel Vadot			};
768f126890aSEmmanuel Vadot			drive_gma {
769f126890aSEmmanuel Vadot				nvidia,pins = "drive_gma";
770f126890aSEmmanuel Vadot				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
771f126890aSEmmanuel Vadot				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
772f126890aSEmmanuel Vadot				nvidia,pull-down-strength = <2>;
773f126890aSEmmanuel Vadot				nvidia,pull-up-strength = <2>;
774f126890aSEmmanuel Vadot				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
775f126890aSEmmanuel Vadot				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
776f126890aSEmmanuel Vadot			};
777f126890aSEmmanuel Vadot		};
778f126890aSEmmanuel Vadot	};
779f126890aSEmmanuel Vadot
780f126890aSEmmanuel Vadot	/* Usable on reworked devices only */
781f126890aSEmmanuel Vadot	serial@70006300 {
782*aa1a8ff2SEmmanuel Vadot		/delete-property/ dmas;
783*aa1a8ff2SEmmanuel Vadot		/delete-property/ dma-names;
784f126890aSEmmanuel Vadot		status = "okay";
785f126890aSEmmanuel Vadot	};
786f126890aSEmmanuel Vadot
787f126890aSEmmanuel Vadot	pwm@7000a000 {
788f126890aSEmmanuel Vadot		status = "okay";
789f126890aSEmmanuel Vadot	};
790f126890aSEmmanuel Vadot
791f126890aSEmmanuel Vadot	i2c@7000d000 {
792f126890aSEmmanuel Vadot		status = "okay";
793f126890aSEmmanuel Vadot		clock-frequency = <400000>;
794f126890aSEmmanuel Vadot
795f126890aSEmmanuel Vadot		regulator@43 {
796f126890aSEmmanuel Vadot			compatible = "ti,tps51632";
797f126890aSEmmanuel Vadot			reg = <0x43>;
798f126890aSEmmanuel Vadot			regulator-name = "vdd-cpu";
799f126890aSEmmanuel Vadot			regulator-min-microvolt = <500000>;
800f126890aSEmmanuel Vadot			regulator-max-microvolt = <1520000>;
801f126890aSEmmanuel Vadot			regulator-always-on;
802f126890aSEmmanuel Vadot			regulator-boot-on;
803f126890aSEmmanuel Vadot		};
804f126890aSEmmanuel Vadot
805f126890aSEmmanuel Vadot		palmas: pmic@58 {
806f126890aSEmmanuel Vadot			compatible = "ti,tps65913", "ti,palmas";
807f126890aSEmmanuel Vadot			reg = <0x58>;
808f126890aSEmmanuel Vadot			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
809f126890aSEmmanuel Vadot
810f126890aSEmmanuel Vadot			#interrupt-cells = <2>;
811f126890aSEmmanuel Vadot			interrupt-controller;
812f126890aSEmmanuel Vadot
813f126890aSEmmanuel Vadot			ti,system-power-controller;
814f126890aSEmmanuel Vadot
815f126890aSEmmanuel Vadot			palmas_gpio: gpio {
816f126890aSEmmanuel Vadot				compatible = "ti,palmas-gpio";
817f126890aSEmmanuel Vadot				gpio-controller;
818f126890aSEmmanuel Vadot				#gpio-cells = <2>;
819f126890aSEmmanuel Vadot			};
820f126890aSEmmanuel Vadot
821f126890aSEmmanuel Vadot			pmic {
822f126890aSEmmanuel Vadot				compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
823f126890aSEmmanuel Vadot
824f126890aSEmmanuel Vadot				regulators {
825f126890aSEmmanuel Vadot					smps12 {
826f126890aSEmmanuel Vadot						regulator-name = "vdd-ddr";
827f126890aSEmmanuel Vadot						regulator-min-microvolt = <1200000>;
828f126890aSEmmanuel Vadot						regulator-max-microvolt = <1500000>;
829f126890aSEmmanuel Vadot						regulator-always-on;
830f126890aSEmmanuel Vadot						regulator-boot-on;
831f126890aSEmmanuel Vadot					};
832f126890aSEmmanuel Vadot
833f126890aSEmmanuel Vadot					vdd_1v8: smps3 {
834f126890aSEmmanuel Vadot						regulator-name = "vdd-1v8";
835f126890aSEmmanuel Vadot						regulator-min-microvolt = <1800000>;
836f126890aSEmmanuel Vadot						regulator-max-microvolt = <1800000>;
837f126890aSEmmanuel Vadot						regulator-boot-on;
838f126890aSEmmanuel Vadot					};
839f126890aSEmmanuel Vadot
840f126890aSEmmanuel Vadot					smps457 {
841f126890aSEmmanuel Vadot						regulator-name = "vdd-soc";
842f126890aSEmmanuel Vadot						regulator-min-microvolt = <900000>;
843f126890aSEmmanuel Vadot						regulator-max-microvolt = <1400000>;
844f126890aSEmmanuel Vadot						regulator-always-on;
845f126890aSEmmanuel Vadot						regulator-boot-on;
846f126890aSEmmanuel Vadot					};
847f126890aSEmmanuel Vadot
848f126890aSEmmanuel Vadot					smps8 {
849f126890aSEmmanuel Vadot						regulator-name = "avdd-pll-1v05";
850f126890aSEmmanuel Vadot						regulator-min-microvolt = <1050000>;
851f126890aSEmmanuel Vadot						regulator-max-microvolt = <1050000>;
852f126890aSEmmanuel Vadot						regulator-always-on;
853f126890aSEmmanuel Vadot						regulator-boot-on;
854f126890aSEmmanuel Vadot					};
855f126890aSEmmanuel Vadot
856f126890aSEmmanuel Vadot					smps9 {
857f126890aSEmmanuel Vadot						regulator-name = "vdd-2v85-emmc";
858f126890aSEmmanuel Vadot						regulator-min-microvolt = <2800000>;
859f126890aSEmmanuel Vadot						regulator-max-microvolt = <2800000>;
860f126890aSEmmanuel Vadot						regulator-always-on;
861f126890aSEmmanuel Vadot					};
862f126890aSEmmanuel Vadot
863f126890aSEmmanuel Vadot					smps10_out1 {
864f126890aSEmmanuel Vadot						regulator-name = "vdd-fan";
865f126890aSEmmanuel Vadot						regulator-min-microvolt = <5000000>;
866f126890aSEmmanuel Vadot						regulator-max-microvolt = <5000000>;
867f126890aSEmmanuel Vadot						regulator-always-on;
868f126890aSEmmanuel Vadot						regulator-boot-on;
869f126890aSEmmanuel Vadot					};
870f126890aSEmmanuel Vadot
871f126890aSEmmanuel Vadot					smps10_out2 {
872f126890aSEmmanuel Vadot						regulator-name = "vdd-5v0-sys";
873f126890aSEmmanuel Vadot						regulator-min-microvolt = <5000000>;
874f126890aSEmmanuel Vadot						regulator-max-microvolt = <5000000>;
875f126890aSEmmanuel Vadot						regulator-always-on;
876f126890aSEmmanuel Vadot						regulator-boot-on;
877f126890aSEmmanuel Vadot					};
878f126890aSEmmanuel Vadot
879f126890aSEmmanuel Vadot					ldo2 {
880f126890aSEmmanuel Vadot						regulator-name = "vdd-2v8-display";
881f126890aSEmmanuel Vadot						regulator-min-microvolt = <2800000>;
882f126890aSEmmanuel Vadot						regulator-max-microvolt = <2800000>;
883f126890aSEmmanuel Vadot						regulator-always-on;
884f126890aSEmmanuel Vadot						regulator-boot-on;
885f126890aSEmmanuel Vadot					};
886f126890aSEmmanuel Vadot
887f126890aSEmmanuel Vadot					vdd_1v2_ap: ldo3 {
888f126890aSEmmanuel Vadot						regulator-name = "avdd-1v2";
889f126890aSEmmanuel Vadot						regulator-min-microvolt = <1200000>;
890f126890aSEmmanuel Vadot						regulator-max-microvolt = <1200000>;
891f126890aSEmmanuel Vadot						regulator-always-on;
892f126890aSEmmanuel Vadot						regulator-boot-on;
893f126890aSEmmanuel Vadot					};
894f126890aSEmmanuel Vadot
895f126890aSEmmanuel Vadot					ldo4 {
896f126890aSEmmanuel Vadot						regulator-name = "vpp-fuse";
897f126890aSEmmanuel Vadot						regulator-min-microvolt = <1800000>;
898f126890aSEmmanuel Vadot						regulator-max-microvolt = <1800000>;
899f126890aSEmmanuel Vadot					};
900f126890aSEmmanuel Vadot
901f126890aSEmmanuel Vadot					ldo5 {
902f126890aSEmmanuel Vadot						regulator-name = "avdd-hdmi-pll";
903f126890aSEmmanuel Vadot						regulator-min-microvolt = <1200000>;
904f126890aSEmmanuel Vadot						regulator-max-microvolt = <1200000>;
905f126890aSEmmanuel Vadot					};
906f126890aSEmmanuel Vadot
907f126890aSEmmanuel Vadot					ldo6 {
908f126890aSEmmanuel Vadot						regulator-name = "vdd-sensor-2v8";
909f126890aSEmmanuel Vadot						regulator-min-microvolt = <2850000>;
910f126890aSEmmanuel Vadot						regulator-max-microvolt = <2850000>;
911f126890aSEmmanuel Vadot					};
912f126890aSEmmanuel Vadot
913f126890aSEmmanuel Vadot					ldo8 {
914f126890aSEmmanuel Vadot						regulator-name = "vdd-rtc";
915f126890aSEmmanuel Vadot						regulator-min-microvolt = <1100000>;
916f126890aSEmmanuel Vadot						regulator-max-microvolt = <1100000>;
917f126890aSEmmanuel Vadot						regulator-always-on;
918f126890aSEmmanuel Vadot						regulator-boot-on;
919f126890aSEmmanuel Vadot						ti,enable-ldo8-tracking;
920f126890aSEmmanuel Vadot					};
921f126890aSEmmanuel Vadot
922f126890aSEmmanuel Vadot					vddio_sdmmc3: ldo9 {
923f126890aSEmmanuel Vadot						regulator-name = "vddio-sdmmc3";
924f126890aSEmmanuel Vadot						regulator-min-microvolt = <1800000>;
925f126890aSEmmanuel Vadot						regulator-max-microvolt = <3300000>;
926f126890aSEmmanuel Vadot					};
927f126890aSEmmanuel Vadot
928f126890aSEmmanuel Vadot					ldousb {
929f126890aSEmmanuel Vadot						regulator-name = "avdd-usb-hdmi";
930f126890aSEmmanuel Vadot						regulator-min-microvolt = <3300000>;
931f126890aSEmmanuel Vadot						regulator-max-microvolt = <3300000>;
932f126890aSEmmanuel Vadot						regulator-always-on;
933f126890aSEmmanuel Vadot						regulator-boot-on;
934f126890aSEmmanuel Vadot					};
935f126890aSEmmanuel Vadot
936f126890aSEmmanuel Vadot					vdd_3v3_sys: regen1 {
937f126890aSEmmanuel Vadot						regulator-name = "rail-3v3";
938f126890aSEmmanuel Vadot						regulator-max-microvolt = <3300000>;
939f126890aSEmmanuel Vadot						regulator-always-on;
940f126890aSEmmanuel Vadot						regulator-boot-on;
941f126890aSEmmanuel Vadot					};
942f126890aSEmmanuel Vadot
943f126890aSEmmanuel Vadot					regen2 {
944f126890aSEmmanuel Vadot						regulator-name = "rail-5v0";
945f126890aSEmmanuel Vadot						regulator-max-microvolt = <5000000>;
946f126890aSEmmanuel Vadot						regulator-always-on;
947f126890aSEmmanuel Vadot						regulator-boot-on;
948f126890aSEmmanuel Vadot					};
949f126890aSEmmanuel Vadot
950f126890aSEmmanuel Vadot				};
951f126890aSEmmanuel Vadot			};
952f126890aSEmmanuel Vadot
953f126890aSEmmanuel Vadot			rtc {
954f126890aSEmmanuel Vadot				compatible = "ti,palmas-rtc";
955f126890aSEmmanuel Vadot				interrupt-parent = <&palmas>;
956f126890aSEmmanuel Vadot				interrupts = <8 0>;
957f126890aSEmmanuel Vadot			};
958f126890aSEmmanuel Vadot
959f126890aSEmmanuel Vadot		};
960f126890aSEmmanuel Vadot	};
961f126890aSEmmanuel Vadot
962f126890aSEmmanuel Vadot	pmc@7000e400 {
963f126890aSEmmanuel Vadot		nvidia,invert-interrupt;
964f126890aSEmmanuel Vadot	};
965f126890aSEmmanuel Vadot
966f126890aSEmmanuel Vadot	/* SD card */
967f126890aSEmmanuel Vadot	mmc@78000400 {
968f126890aSEmmanuel Vadot		status = "okay";
969f126890aSEmmanuel Vadot		bus-width = <4>;
970f126890aSEmmanuel Vadot		vqmmc-supply = <&vddio_sdmmc3>;
971f126890aSEmmanuel Vadot		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
972f126890aSEmmanuel Vadot		power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
973f126890aSEmmanuel Vadot	};
974f126890aSEmmanuel Vadot
975f126890aSEmmanuel Vadot	/* eMMC */
976f126890aSEmmanuel Vadot	mmc@78000600 {
977f126890aSEmmanuel Vadot		status = "okay";
978f126890aSEmmanuel Vadot		bus-width = <8>;
979f126890aSEmmanuel Vadot		non-removable;
980f126890aSEmmanuel Vadot	};
981f126890aSEmmanuel Vadot
982f126890aSEmmanuel Vadot	/* External USB port (must be powered) */
983f126890aSEmmanuel Vadot	usb@7d000000 {
984f126890aSEmmanuel Vadot		status = "okay";
985f126890aSEmmanuel Vadot	};
986f126890aSEmmanuel Vadot
987f126890aSEmmanuel Vadot	usb-phy@7d000000 {
988f126890aSEmmanuel Vadot		status = "okay";
989f126890aSEmmanuel Vadot		nvidia,xcvr-setup = <7>;
990f126890aSEmmanuel Vadot		nvidia,xcvr-lsfslew = <2>;
991f126890aSEmmanuel Vadot		nvidia,xcvr-lsrslew = <2>;
992f126890aSEmmanuel Vadot		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
993f126890aSEmmanuel Vadot		/* Should be changed to "otg" once we have vbus_supply */
994f126890aSEmmanuel Vadot		/* As of now, USB devices need to be powered externally */
995f126890aSEmmanuel Vadot		dr_mode = "host";
996f126890aSEmmanuel Vadot	};
997f126890aSEmmanuel Vadot
998f126890aSEmmanuel Vadot	/* SHIELD controller */
999f126890aSEmmanuel Vadot	usb@7d008000 {
1000f126890aSEmmanuel Vadot		status = "okay";
1001f126890aSEmmanuel Vadot	};
1002f126890aSEmmanuel Vadot
1003f126890aSEmmanuel Vadot	usb-phy@7d008000 {
1004f126890aSEmmanuel Vadot		status = "okay";
1005f126890aSEmmanuel Vadot		nvidia,xcvr-setup = <7>;
1006f126890aSEmmanuel Vadot		nvidia,xcvr-lsfslew = <2>;
1007f126890aSEmmanuel Vadot		nvidia,xcvr-lsrslew = <2>;
1008f126890aSEmmanuel Vadot	};
1009f126890aSEmmanuel Vadot
1010f126890aSEmmanuel Vadot	backlight: backlight {
1011f126890aSEmmanuel Vadot		compatible = "pwm-backlight";
1012f126890aSEmmanuel Vadot		pwms = <&pwm 1 40000>;
1013f126890aSEmmanuel Vadot
1014f126890aSEmmanuel Vadot		brightness-levels = <0 4 8 16 32 64 128 255>;
1015f126890aSEmmanuel Vadot		default-brightness-level = <6>;
1016f126890aSEmmanuel Vadot
1017f126890aSEmmanuel Vadot		power-supply = <&lcd_bl_en>;
1018f126890aSEmmanuel Vadot		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1019f126890aSEmmanuel Vadot	};
1020f126890aSEmmanuel Vadot
1021f126890aSEmmanuel Vadot	clk32k_in: clock-32k {
1022f126890aSEmmanuel Vadot		compatible = "fixed-clock";
1023f126890aSEmmanuel Vadot		clock-frequency = <32768>;
1024f126890aSEmmanuel Vadot		#clock-cells = <0>;
1025f126890aSEmmanuel Vadot	};
1026f126890aSEmmanuel Vadot
1027f126890aSEmmanuel Vadot	gpio-keys {
1028f126890aSEmmanuel Vadot		compatible = "gpio-keys";
1029f126890aSEmmanuel Vadot
1030f126890aSEmmanuel Vadot		key-back {
1031f126890aSEmmanuel Vadot			label = "Back";
1032f126890aSEmmanuel Vadot			gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
1033f126890aSEmmanuel Vadot			linux,code = <KEY_BACK>;
1034f126890aSEmmanuel Vadot		};
1035f126890aSEmmanuel Vadot
1036f126890aSEmmanuel Vadot		key-home {
1037f126890aSEmmanuel Vadot			label = "Home";
1038f126890aSEmmanuel Vadot			gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
1039f126890aSEmmanuel Vadot			linux,code = <KEY_HOME>;
1040f126890aSEmmanuel Vadot		};
1041f126890aSEmmanuel Vadot
1042f126890aSEmmanuel Vadot		key-power {
1043f126890aSEmmanuel Vadot			label = "Power";
1044f126890aSEmmanuel Vadot			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1045f126890aSEmmanuel Vadot			linux,code = <KEY_POWER>;
1046f126890aSEmmanuel Vadot			wakeup-source;
1047f126890aSEmmanuel Vadot		};
1048f126890aSEmmanuel Vadot	};
1049f126890aSEmmanuel Vadot
1050f126890aSEmmanuel Vadot	lcd_bl_en: regulator-lcden {
1051f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1052f126890aSEmmanuel Vadot		regulator-name = "lcd_bl_en";
1053f126890aSEmmanuel Vadot		regulator-min-microvolt = <5000000>;
1054f126890aSEmmanuel Vadot		regulator-max-microvolt = <5000000>;
1055f126890aSEmmanuel Vadot		regulator-boot-on;
1056f126890aSEmmanuel Vadot	};
1057f126890aSEmmanuel Vadot
1058f126890aSEmmanuel Vadot	vdd_lcd: regulator-lcd {
1059f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1060f126890aSEmmanuel Vadot		regulator-name = "vdd_lcd_1v8";
1061f126890aSEmmanuel Vadot		regulator-min-microvolt = <1800000>;
1062f126890aSEmmanuel Vadot		regulator-max-microvolt = <1800000>;
1063f126890aSEmmanuel Vadot		vin-supply = <&vdd_1v8>;
1064f126890aSEmmanuel Vadot		enable-active-high;
1065f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
1066f126890aSEmmanuel Vadot		regulator-boot-on;
1067f126890aSEmmanuel Vadot	};
1068f126890aSEmmanuel Vadot
1069f126890aSEmmanuel Vadot	regulator-1v8ts {
1070f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1071f126890aSEmmanuel Vadot		regulator-name = "vdd_1v8_ts";
1072f126890aSEmmanuel Vadot		regulator-min-microvolt = <1800000>;
1073f126890aSEmmanuel Vadot		regulator-max-microvolt = <1800000>;
1074f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>;
1075f126890aSEmmanuel Vadot		regulator-boot-on;
1076f126890aSEmmanuel Vadot	};
1077f126890aSEmmanuel Vadot
1078f126890aSEmmanuel Vadot	regulator-3v3ts {
1079f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1080f126890aSEmmanuel Vadot		regulator-name = "vdd_3v3_ts";
1081f126890aSEmmanuel Vadot		regulator-min-microvolt = <3300000>;
1082f126890aSEmmanuel Vadot		regulator-max-microvolt = <3300000>;
1083f126890aSEmmanuel Vadot		enable-active-high;
1084f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
1085f126890aSEmmanuel Vadot		regulator-boot-on;
1086f126890aSEmmanuel Vadot	};
1087f126890aSEmmanuel Vadot
1088f126890aSEmmanuel Vadot	regulator-1v8com {
1089f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1090f126890aSEmmanuel Vadot		regulator-name = "vdd_1v8_com";
1091f126890aSEmmanuel Vadot		regulator-min-microvolt = <1800000>;
1092f126890aSEmmanuel Vadot		regulator-max-microvolt = <1800000>;
1093f126890aSEmmanuel Vadot		vin-supply = <&vdd_1v8>;
1094f126890aSEmmanuel Vadot		enable-active-high;
1095f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
1096f126890aSEmmanuel Vadot		regulator-boot-on;
1097f126890aSEmmanuel Vadot	};
1098f126890aSEmmanuel Vadot
1099f126890aSEmmanuel Vadot	regulator-3v3com {
1100f126890aSEmmanuel Vadot		compatible = "regulator-fixed";
1101f126890aSEmmanuel Vadot		regulator-name = "vdd_3v3_com";
1102f126890aSEmmanuel Vadot		regulator-min-microvolt = <3300000>;
1103f126890aSEmmanuel Vadot		regulator-max-microvolt = <3300000>;
1104f126890aSEmmanuel Vadot		vin-supply = <&vdd_3v3_sys>;
1105f126890aSEmmanuel Vadot		enable-active-high;
1106f126890aSEmmanuel Vadot		gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
1107f126890aSEmmanuel Vadot		regulator-always-on;
1108f126890aSEmmanuel Vadot		regulator-boot-on;
1109f126890aSEmmanuel Vadot	};
1110f126890aSEmmanuel Vadot};
1111