1f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2f126890aSEmmanuel Vadot 3f126890aSEmmanuel Vadot/dts-v1/; 4f126890aSEmmanuel Vadot 5f126890aSEmmanuel Vadot#include <dt-bindings/input/gpio-keys.h> 6f126890aSEmmanuel Vadot#include <dt-bindings/input/input.h> 7f126890aSEmmanuel Vadot 8f126890aSEmmanuel Vadot#include "tegra114.dtsi" 9f126890aSEmmanuel Vadot 10f126890aSEmmanuel Vadot/ { 11f126890aSEmmanuel Vadot model = "Asus Transformer Pad TF701T"; 12f126890aSEmmanuel Vadot compatible = "asus,tf701t", "nvidia,tegra114"; 13f126890aSEmmanuel Vadot chassis-type = "convertible"; 14f126890aSEmmanuel Vadot 15f126890aSEmmanuel Vadot aliases { 16f126890aSEmmanuel Vadot mmc0 = "/mmc@78000600"; /* eMMC */ 17f126890aSEmmanuel Vadot mmc1 = "/mmc@78000400"; /* uSD slot */ 18f126890aSEmmanuel Vadot mmc2 = "/mmc@78000000"; /* WiFi */ 19f126890aSEmmanuel Vadot 20f126890aSEmmanuel Vadot rtc0 = &palmas; 21f126890aSEmmanuel Vadot rtc1 = "/rtc@7000e000"; 22f126890aSEmmanuel Vadot 23f126890aSEmmanuel Vadot serial0 = &uartd; /* Console */ 24f126890aSEmmanuel Vadot serial1 = &uartc; /* Bluetooth */ 25f126890aSEmmanuel Vadot serial2 = &uartb; /* GPS */ 26f126890aSEmmanuel Vadot }; 27f126890aSEmmanuel Vadot 28f126890aSEmmanuel Vadot firmware { 29f126890aSEmmanuel Vadot trusted-foundations { 30f126890aSEmmanuel Vadot compatible = "tlm,trusted-foundations"; 31f126890aSEmmanuel Vadot tlm,version-major = <2>; 32f126890aSEmmanuel Vadot tlm,version-minor = <8>; 33f126890aSEmmanuel Vadot }; 34f126890aSEmmanuel Vadot }; 35f126890aSEmmanuel Vadot 36f126890aSEmmanuel Vadot memory@80000000 { 37f126890aSEmmanuel Vadot reg = <0x80000000 0x80000000>; 38f126890aSEmmanuel Vadot }; 39f126890aSEmmanuel Vadot 40f126890aSEmmanuel Vadot reserved-memory { 41f126890aSEmmanuel Vadot #address-cells = <1>; 42f126890aSEmmanuel Vadot #size-cells = <1>; 43f126890aSEmmanuel Vadot ranges; 44f126890aSEmmanuel Vadot 45f126890aSEmmanuel Vadot linux,cma@80000000 { 46f126890aSEmmanuel Vadot compatible = "shared-dma-pool"; 47f126890aSEmmanuel Vadot alloc-ranges = <0x80000000 0x30000000>; 48f126890aSEmmanuel Vadot size = <0x10000000>; 49f126890aSEmmanuel Vadot linux,cma-default; 50f126890aSEmmanuel Vadot reusable; 51f126890aSEmmanuel Vadot }; 52f126890aSEmmanuel Vadot 53f126890aSEmmanuel Vadot trustzone@bfe00000 { 54f126890aSEmmanuel Vadot reg = <0xbfe00000 0x200000>; 55f126890aSEmmanuel Vadot no-map; 56f126890aSEmmanuel Vadot }; 57f126890aSEmmanuel Vadot }; 58f126890aSEmmanuel Vadot 59f126890aSEmmanuel Vadot host1x@50000000 { 60*b2d2a78aSEmmanuel Vadot hdmi@54280000 { 61*b2d2a78aSEmmanuel Vadot status = "okay"; 62*b2d2a78aSEmmanuel Vadot 63*b2d2a78aSEmmanuel Vadot hdmi-supply = <&hdmi_5v0_sys>; 64*b2d2a78aSEmmanuel Vadot pll-supply = <&avdd_hdmi_pll>; 65*b2d2a78aSEmmanuel Vadot vdd-supply = <&avdd_hdmi>; 66*b2d2a78aSEmmanuel Vadot 67*b2d2a78aSEmmanuel Vadot port { 68*b2d2a78aSEmmanuel Vadot hdmi_out: endpoint { 69*b2d2a78aSEmmanuel Vadot remote-endpoint = <&connector_in>; 70*b2d2a78aSEmmanuel Vadot }; 71*b2d2a78aSEmmanuel Vadot }; 72*b2d2a78aSEmmanuel Vadot }; 73*b2d2a78aSEmmanuel Vadot 74f126890aSEmmanuel Vadot dsi@54300000 { 75f126890aSEmmanuel Vadot status = "okay"; 76f126890aSEmmanuel Vadot 77*b2d2a78aSEmmanuel Vadot avdd-dsi-csi-supply = <&avdd_dsi_csi>; 78f126890aSEmmanuel Vadot 79f126890aSEmmanuel Vadot nvidia,ganged-mode = <&dsib>; 80f126890aSEmmanuel Vadot 81f126890aSEmmanuel Vadot panel_primary: panel@0 { 82f126890aSEmmanuel Vadot compatible = "sharp,lq101r1sx01"; 83f126890aSEmmanuel Vadot reg = <0>; 84f126890aSEmmanuel Vadot 85f126890aSEmmanuel Vadot link2 = <&panel_secondary>; 86f126890aSEmmanuel Vadot 87*b2d2a78aSEmmanuel Vadot power-supply = <&dvdd_1v8_lcd>; 88f126890aSEmmanuel Vadot backlight = <&backlight>; 89f126890aSEmmanuel Vadot }; 90f126890aSEmmanuel Vadot }; 91f126890aSEmmanuel Vadot 92f126890aSEmmanuel Vadot dsi@54400000 { 93f126890aSEmmanuel Vadot status = "okay"; 94f126890aSEmmanuel Vadot 95*b2d2a78aSEmmanuel Vadot avdd-dsi-csi-supply = <&avdd_dsi_csi>; 96f126890aSEmmanuel Vadot 97f126890aSEmmanuel Vadot panel_secondary: panel@0 { 98f126890aSEmmanuel Vadot compatible = "sharp,lq101r1sx01"; 99f126890aSEmmanuel Vadot reg = <0>; 100f126890aSEmmanuel Vadot }; 101f126890aSEmmanuel Vadot }; 102f126890aSEmmanuel Vadot }; 103f126890aSEmmanuel Vadot 104*b2d2a78aSEmmanuel Vadot vde@6001a000 { 105*b2d2a78aSEmmanuel Vadot assigned-clocks = <&tegra_car TEGRA114_CLK_VDE>; 106*b2d2a78aSEmmanuel Vadot assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_P>; 107*b2d2a78aSEmmanuel Vadot assigned-clock-rates = <408000000>; 108*b2d2a78aSEmmanuel Vadot }; 109*b2d2a78aSEmmanuel Vadot 110f126890aSEmmanuel Vadot pinmux@70000868 { 111*b2d2a78aSEmmanuel Vadot pinctrl-names = "default"; 112*b2d2a78aSEmmanuel Vadot pinctrl-0 = <&state_default>; 113*b2d2a78aSEmmanuel Vadot 114*b2d2a78aSEmmanuel Vadot state_default: pinmux { 115*b2d2a78aSEmmanuel Vadot /* WLAN SDIO pinmux */ 116*b2d2a78aSEmmanuel Vadot sdmmc1-clk { 117*b2d2a78aSEmmanuel Vadot nvidia,pins = "sdmmc1_clk_pz0"; 118*b2d2a78aSEmmanuel Vadot nvidia,function = "sdmmc1"; 119*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 120*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 121*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 122*b2d2a78aSEmmanuel Vadot }; 123*b2d2a78aSEmmanuel Vadot 124*b2d2a78aSEmmanuel Vadot sdmmc1-cmd { 125*b2d2a78aSEmmanuel Vadot nvidia,pins = "sdmmc1_cmd_pz1", 126*b2d2a78aSEmmanuel Vadot "sdmmc1_dat0_py7", 127*b2d2a78aSEmmanuel Vadot "sdmmc1_dat1_py6", 128*b2d2a78aSEmmanuel Vadot "sdmmc1_dat2_py5", 129*b2d2a78aSEmmanuel Vadot "sdmmc1_dat3_py4"; 130*b2d2a78aSEmmanuel Vadot nvidia,function = "sdmmc1"; 131f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 132f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 133f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 134f126890aSEmmanuel Vadot }; 135f126890aSEmmanuel Vadot 136*b2d2a78aSEmmanuel Vadot wlan-power { 137*b2d2a78aSEmmanuel Vadot nvidia,pins = "clk2_req_pcc5"; 138*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 139f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 140f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 141f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 142f126890aSEmmanuel Vadot }; 143*b2d2a78aSEmmanuel Vadot 144*b2d2a78aSEmmanuel Vadot wlan-reset { 145*b2d2a78aSEmmanuel Vadot nvidia,pins = "gpio_x7_aud_px7"; 146*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 147*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 148*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 149*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 150f126890aSEmmanuel Vadot }; 151f126890aSEmmanuel Vadot 152*b2d2a78aSEmmanuel Vadot wlan-host-wake { 153*b2d2a78aSEmmanuel Vadot nvidia,pins = "pu5"; 154*b2d2a78aSEmmanuel Vadot nvidia,function = "pwm2"; 155*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 156*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 157*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 158*b2d2a78aSEmmanuel Vadot }; 159*b2d2a78aSEmmanuel Vadot 160*b2d2a78aSEmmanuel Vadot wlan-3v3-com { 161*b2d2a78aSEmmanuel Vadot nvidia,pins = "pu1"; 162*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 163*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 164*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 165*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 166*b2d2a78aSEmmanuel Vadot }; 167*b2d2a78aSEmmanuel Vadot 168*b2d2a78aSEmmanuel Vadot /* UART-A pinmux */ 169*b2d2a78aSEmmanuel Vadot uarta-cts { 170*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_row10_ps2"; 171*b2d2a78aSEmmanuel Vadot nvidia,function = "uarta"; 172*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 173*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 174*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 175*b2d2a78aSEmmanuel Vadot }; 176*b2d2a78aSEmmanuel Vadot 177*b2d2a78aSEmmanuel Vadot uarta-rts { 178*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_row9_ps1"; 179*b2d2a78aSEmmanuel Vadot nvidia,function = "uarta"; 180*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 181*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 182*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 183*b2d2a78aSEmmanuel Vadot }; 184*b2d2a78aSEmmanuel Vadot 185*b2d2a78aSEmmanuel Vadot /* GNSS UART-B pinmux */ 186*b2d2a78aSEmmanuel Vadot uartb-cts { 187*b2d2a78aSEmmanuel Vadot nvidia,pins = "uart2_cts_n_pj5"; 188*b2d2a78aSEmmanuel Vadot nvidia,function = "uartb"; 189*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 190*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 191*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 192*b2d2a78aSEmmanuel Vadot }; 193*b2d2a78aSEmmanuel Vadot 194*b2d2a78aSEmmanuel Vadot uartb-rts { 195*b2d2a78aSEmmanuel Vadot nvidia,pins = "uart2_rts_n_pj6"; 196*b2d2a78aSEmmanuel Vadot nvidia,function = "uartb"; 197*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 198*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 199*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 200*b2d2a78aSEmmanuel Vadot }; 201*b2d2a78aSEmmanuel Vadot 202*b2d2a78aSEmmanuel Vadot uartb-rxd { 203*b2d2a78aSEmmanuel Vadot nvidia,pins = "uart2_rxd_pc3"; 204*b2d2a78aSEmmanuel Vadot nvidia,function = "irda"; 205*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 206*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 207*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 208*b2d2a78aSEmmanuel Vadot }; 209*b2d2a78aSEmmanuel Vadot 210*b2d2a78aSEmmanuel Vadot uartb-txd { 211*b2d2a78aSEmmanuel Vadot nvidia,pins = "uart2_txd_pc2"; 212*b2d2a78aSEmmanuel Vadot nvidia,function = "irda"; 213*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 214*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 215*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 216*b2d2a78aSEmmanuel Vadot }; 217*b2d2a78aSEmmanuel Vadot 218*b2d2a78aSEmmanuel Vadot /* Bluetooth UART-C pinmux */ 219*b2d2a78aSEmmanuel Vadot uartc-cts-rxd { 220*b2d2a78aSEmmanuel Vadot nvidia,pins = "uart3_cts_n_pa1", 221*b2d2a78aSEmmanuel Vadot "uart3_rxd_pw7"; 222*b2d2a78aSEmmanuel Vadot nvidia,function = "uartc"; 223*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 224*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 225*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 226*b2d2a78aSEmmanuel Vadot }; 227*b2d2a78aSEmmanuel Vadot 228*b2d2a78aSEmmanuel Vadot uartc-rts-txd { 229*b2d2a78aSEmmanuel Vadot nvidia,pins = "uart3_rts_n_pc0", 230*b2d2a78aSEmmanuel Vadot "uart3_txd_pw6"; 231*b2d2a78aSEmmanuel Vadot nvidia,function = "uartc"; 232*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 233*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 234*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 235*b2d2a78aSEmmanuel Vadot }; 236*b2d2a78aSEmmanuel Vadot 237*b2d2a78aSEmmanuel Vadot bt-shutdown { 238*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_col6_pq6", 239*b2d2a78aSEmmanuel Vadot "kb_col7_pq7"; 240*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 241*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 242*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 243*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 244*b2d2a78aSEmmanuel Vadot }; 245*b2d2a78aSEmmanuel Vadot 246*b2d2a78aSEmmanuel Vadot bt-dev-wake { 247*b2d2a78aSEmmanuel Vadot nvidia,pins = "clk3_req_pee1"; 248*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 249*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 250*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 251*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 252*b2d2a78aSEmmanuel Vadot }; 253*b2d2a78aSEmmanuel Vadot 254*b2d2a78aSEmmanuel Vadot bt-host-wake { 255*b2d2a78aSEmmanuel Vadot nvidia,pins = "pu6"; 256*b2d2a78aSEmmanuel Vadot nvidia,function = "pwm3"; 257*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 258*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 259*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 260*b2d2a78aSEmmanuel Vadot }; 261*b2d2a78aSEmmanuel Vadot 262*b2d2a78aSEmmanuel Vadot bt-pcm-dap4-out { 263*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap4_fs_pp4", 264*b2d2a78aSEmmanuel Vadot "dap4_dout_pp6", 265*b2d2a78aSEmmanuel Vadot "dap4_sclk_pp7"; 266*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s3"; 267*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 268*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 269*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 270*b2d2a78aSEmmanuel Vadot }; 271*b2d2a78aSEmmanuel Vadot 272*b2d2a78aSEmmanuel Vadot bt-pcm-dap4-in { 273*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap4_din_pp5"; 274*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s3"; 275*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 276*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 277*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 278*b2d2a78aSEmmanuel Vadot }; 279*b2d2a78aSEmmanuel Vadot 280*b2d2a78aSEmmanuel Vadot /* UART-D pinmux */ 281*b2d2a78aSEmmanuel Vadot uartd-cts { 282*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_a17_pb0"; 283*b2d2a78aSEmmanuel Vadot nvidia,function = "uartd"; 284*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 285*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 286*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 287*b2d2a78aSEmmanuel Vadot }; 288*b2d2a78aSEmmanuel Vadot 289*b2d2a78aSEmmanuel Vadot uartd-rts { 290*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_a16_pj7", 291*b2d2a78aSEmmanuel Vadot "gmi_a19_pk7"; 292*b2d2a78aSEmmanuel Vadot nvidia,function = "uartd"; 293*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 294*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 295*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 296*b2d2a78aSEmmanuel Vadot }; 297*b2d2a78aSEmmanuel Vadot 298*b2d2a78aSEmmanuel Vadot /* MicroSD pinmux */ 299*b2d2a78aSEmmanuel Vadot sdmmc3-clk { 300*b2d2a78aSEmmanuel Vadot nvidia,pins = "sdmmc3_clk_pa6"; 301*b2d2a78aSEmmanuel Vadot nvidia,function = "sdmmc3"; 302*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 303*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 304*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 305*b2d2a78aSEmmanuel Vadot }; 306*b2d2a78aSEmmanuel Vadot 307*b2d2a78aSEmmanuel Vadot sdmmc3-data { 308*b2d2a78aSEmmanuel Vadot nvidia,pins = "sdmmc3_cmd_pa7", 309*b2d2a78aSEmmanuel Vadot "sdmmc3_dat0_pb7", 310*b2d2a78aSEmmanuel Vadot "sdmmc3_dat1_pb6", 311*b2d2a78aSEmmanuel Vadot "sdmmc3_dat2_pb5", 312*b2d2a78aSEmmanuel Vadot "sdmmc3_dat3_pb4", 313*b2d2a78aSEmmanuel Vadot "kb_col4_pq4", 314*b2d2a78aSEmmanuel Vadot "sdmmc3_cd_n_pv2", 315*b2d2a78aSEmmanuel Vadot "sdmmc3_clk_lb_out_pee4", 316*b2d2a78aSEmmanuel Vadot "sdmmc3_clk_lb_in_pee5"; 317*b2d2a78aSEmmanuel Vadot nvidia,function = "sdmmc3"; 318*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 319*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 320*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 321*b2d2a78aSEmmanuel Vadot }; 322*b2d2a78aSEmmanuel Vadot 323*b2d2a78aSEmmanuel Vadot microsd-pwr { 324*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_clk_pk1"; 325f126890aSEmmanuel Vadot nvidia,function = "gmi"; 326f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 327f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 328f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 329f126890aSEmmanuel Vadot }; 330*b2d2a78aSEmmanuel Vadot 331*b2d2a78aSEmmanuel Vadot /* EMMC pinmux */ 332*b2d2a78aSEmmanuel Vadot sdmmc4-clk-cmd { 333*b2d2a78aSEmmanuel Vadot nvidia,pins = "sdmmc4_clk_pcc4"; 334*b2d2a78aSEmmanuel Vadot nvidia,function = "sdmmc4"; 335*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 336*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 337*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 338f126890aSEmmanuel Vadot }; 339f126890aSEmmanuel Vadot 340*b2d2a78aSEmmanuel Vadot sdmmc4-data { 341*b2d2a78aSEmmanuel Vadot nvidia,pins = "sdmmc4_cmd_pt7", 342*b2d2a78aSEmmanuel Vadot "sdmmc4_dat0_paa0", 343*b2d2a78aSEmmanuel Vadot "sdmmc4_dat1_paa1", 344*b2d2a78aSEmmanuel Vadot "sdmmc4_dat2_paa2", 345*b2d2a78aSEmmanuel Vadot "sdmmc4_dat3_paa3", 346*b2d2a78aSEmmanuel Vadot "sdmmc4_dat4_paa4", 347*b2d2a78aSEmmanuel Vadot "sdmmc4_dat5_paa5", 348*b2d2a78aSEmmanuel Vadot "sdmmc4_dat6_paa6", 349*b2d2a78aSEmmanuel Vadot "sdmmc4_dat7_paa7"; 350*b2d2a78aSEmmanuel Vadot nvidia,function = "sdmmc4"; 351f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 352f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 353f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 354f126890aSEmmanuel Vadot }; 355f126890aSEmmanuel Vadot 356*b2d2a78aSEmmanuel Vadot /* I2C pinmux */ 357*b2d2a78aSEmmanuel Vadot gen1-i2c { 358*b2d2a78aSEmmanuel Vadot nvidia,pins = "gen1_i2c_scl_pc4", 359*b2d2a78aSEmmanuel Vadot "gen1_i2c_sda_pc5"; 360*b2d2a78aSEmmanuel Vadot nvidia,function = "i2c1"; 361*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 362*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 363*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 364*b2d2a78aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 365*b2d2a78aSEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 366*b2d2a78aSEmmanuel Vadot }; 367*b2d2a78aSEmmanuel Vadot 368*b2d2a78aSEmmanuel Vadot gen2-i2c { 369*b2d2a78aSEmmanuel Vadot nvidia,pins = "gen2_i2c_scl_pt5", 370*b2d2a78aSEmmanuel Vadot "gen2_i2c_sda_pt6"; 371*b2d2a78aSEmmanuel Vadot nvidia,function = "i2c2"; 372*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 373*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 374*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 375*b2d2a78aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 376*b2d2a78aSEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 377*b2d2a78aSEmmanuel Vadot }; 378*b2d2a78aSEmmanuel Vadot 379*b2d2a78aSEmmanuel Vadot cam-i2c { 380*b2d2a78aSEmmanuel Vadot nvidia,pins = "cam_i2c_scl_pbb1", 381*b2d2a78aSEmmanuel Vadot "cam_i2c_sda_pbb2"; 382*b2d2a78aSEmmanuel Vadot nvidia,function = "i2c3"; 383*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 385*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 386*b2d2a78aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 387*b2d2a78aSEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 388*b2d2a78aSEmmanuel Vadot }; 389*b2d2a78aSEmmanuel Vadot 390*b2d2a78aSEmmanuel Vadot ddc-i2c { 391*b2d2a78aSEmmanuel Vadot nvidia,pins = "ddc_scl_pv4", 392*b2d2a78aSEmmanuel Vadot "ddc_sda_pv5"; 393*b2d2a78aSEmmanuel Vadot nvidia,function = "i2c4"; 394*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 395*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 396*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 397*b2d2a78aSEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 398*b2d2a78aSEmmanuel Vadot }; 399*b2d2a78aSEmmanuel Vadot 400*b2d2a78aSEmmanuel Vadot pwr-i2c { 401*b2d2a78aSEmmanuel Vadot nvidia,pins = "pwr_i2c_scl_pz6", 402*b2d2a78aSEmmanuel Vadot "pwr_i2c_sda_pz7"; 403*b2d2a78aSEmmanuel Vadot nvidia,function = "i2cpwr"; 404*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 405*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 406*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 407*b2d2a78aSEmmanuel Vadot nvidia,open-drain = <TEGRA_PIN_ENABLE>; 408*b2d2a78aSEmmanuel Vadot nvidia,lock = <TEGRA_PIN_DISABLE>; 409*b2d2a78aSEmmanuel Vadot }; 410*b2d2a78aSEmmanuel Vadot 411*b2d2a78aSEmmanuel Vadot /* SPI pinmux */ 412*b2d2a78aSEmmanuel Vadot spi1-out { 413*b2d2a78aSEmmanuel Vadot nvidia,pins = "ulpi_clk_py0", 414*b2d2a78aSEmmanuel Vadot "ulpi_nxt_py2", 415*b2d2a78aSEmmanuel Vadot "ulpi_stp_py3"; 416*b2d2a78aSEmmanuel Vadot nvidia,function = "spi1"; 417f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 418f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 419f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 420f126890aSEmmanuel Vadot }; 421*b2d2a78aSEmmanuel Vadot 422*b2d2a78aSEmmanuel Vadot spi1-in { 423*b2d2a78aSEmmanuel Vadot nvidia,pins = "ulpi_dir_py1"; 424*b2d2a78aSEmmanuel Vadot nvidia,function = "spi1"; 425*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 426*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 427*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 428f126890aSEmmanuel Vadot }; 429f126890aSEmmanuel Vadot 430*b2d2a78aSEmmanuel Vadot spi2 { 431*b2d2a78aSEmmanuel Vadot nvidia,pins = "ulpi_data4_po5", 432*b2d2a78aSEmmanuel Vadot "ulpi_data7_po0"; 433*b2d2a78aSEmmanuel Vadot nvidia,function = "spi2"; 434*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 435*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 436*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 437*b2d2a78aSEmmanuel Vadot }; 438*b2d2a78aSEmmanuel Vadot 439*b2d2a78aSEmmanuel Vadot spi4-out { 440*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad6_pg6", 441*b2d2a78aSEmmanuel Vadot "gmi_wr_n_pi0"; 442*b2d2a78aSEmmanuel Vadot nvidia,function = "spi4"; 443*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 444*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 445*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 446*b2d2a78aSEmmanuel Vadot }; 447*b2d2a78aSEmmanuel Vadot 448*b2d2a78aSEmmanuel Vadot spi4-in { 449*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad5_pg5", 450*b2d2a78aSEmmanuel Vadot "gmi_ad7_pg7"; 451*b2d2a78aSEmmanuel Vadot nvidia,function = "spi4"; 452*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 453*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 454*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 455*b2d2a78aSEmmanuel Vadot }; 456*b2d2a78aSEmmanuel Vadot 457*b2d2a78aSEmmanuel Vadot /* GPIO keys pinmux */ 458*b2d2a78aSEmmanuel Vadot hall-switch { 459f126890aSEmmanuel Vadot nvidia,pins = "ulpi_data4_po5"; 460f126890aSEmmanuel Vadot nvidia,function = "spi2"; 461f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 462f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 463f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 464f126890aSEmmanuel Vadot }; 465*b2d2a78aSEmmanuel Vadot 466*b2d2a78aSEmmanuel Vadot lineout-switch { 467*b2d2a78aSEmmanuel Vadot nvidia,pins = "gpio_x5_aud_px5"; 468*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 469*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 470*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 471*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 472f126890aSEmmanuel Vadot }; 473f126890aSEmmanuel Vadot 474*b2d2a78aSEmmanuel Vadot power-key { 475f126890aSEmmanuel Vadot nvidia,pins = "kb_col0_pq0"; 476f126890aSEmmanuel Vadot nvidia,function = "kbc"; 477f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 478f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 479f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 480f126890aSEmmanuel Vadot }; 481f126890aSEmmanuel Vadot 482*b2d2a78aSEmmanuel Vadot volume-keys { 483f126890aSEmmanuel Vadot nvidia,pins = "kb_row1_pr1", 484f126890aSEmmanuel Vadot "kb_row2_pr2"; 485f126890aSEmmanuel Vadot nvidia,function = "rsvd2"; 486f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 487f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 488f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 489f126890aSEmmanuel Vadot }; 490f126890aSEmmanuel Vadot 491*b2d2a78aSEmmanuel Vadot /* Sensors pinmux */ 492*b2d2a78aSEmmanuel Vadot nct-irq { 493*b2d2a78aSEmmanuel Vadot nvidia,pins = "ulpi_data3_po4"; 494*b2d2a78aSEmmanuel Vadot nvidia,function = "ulpi"; 495f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 496f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 497f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 498f126890aSEmmanuel Vadot }; 499f126890aSEmmanuel Vadot 500*b2d2a78aSEmmanuel Vadot mpu-irq { 501f126890aSEmmanuel Vadot nvidia,pins = "kb_row3_pr3"; 502f126890aSEmmanuel Vadot nvidia,function = "rsvd3"; 503f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 504f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 505f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 506f126890aSEmmanuel Vadot }; 507*b2d2a78aSEmmanuel Vadot 508*b2d2a78aSEmmanuel Vadot /* HDMI pinmux */ 509*b2d2a78aSEmmanuel Vadot hdmi-hpd { 510*b2d2a78aSEmmanuel Vadot nvidia,pins = "hdmi_int_pn7"; 511*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 512*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 513*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 514*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 515f126890aSEmmanuel Vadot }; 516f126890aSEmmanuel Vadot 517*b2d2a78aSEmmanuel Vadot hdmi-en { 518*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap3_dout_pp2"; 519*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s2"; 520*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 521*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 522*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 523*b2d2a78aSEmmanuel Vadot }; 524*b2d2a78aSEmmanuel Vadot 525*b2d2a78aSEmmanuel Vadot hdmi-cec { 526*b2d2a78aSEmmanuel Vadot nvidia,pins = "hdmi_cec_pee3"; 527*b2d2a78aSEmmanuel Vadot nvidia,function = "cec"; 528*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 529*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 530*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 531*b2d2a78aSEmmanuel Vadot }; 532*b2d2a78aSEmmanuel Vadot 533*b2d2a78aSEmmanuel Vadot /* LED pinmux */ 534*b2d2a78aSEmmanuel Vadot backlight-pwm { 535f126890aSEmmanuel Vadot nvidia,pins = "gmi_ad9_ph1"; 536f126890aSEmmanuel Vadot nvidia,function = "pwm1"; 537f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 538f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 539f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 540f126890aSEmmanuel Vadot }; 541*b2d2a78aSEmmanuel Vadot 542*b2d2a78aSEmmanuel Vadot backlight-en { 543*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad10_ph2"; 544*b2d2a78aSEmmanuel Vadot nvidia,function = "gmi"; 545*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 546*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 547*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 548f126890aSEmmanuel Vadot }; 549f126890aSEmmanuel Vadot 550*b2d2a78aSEmmanuel Vadot /* Touchscreen pinmux */ 551*b2d2a78aSEmmanuel Vadot touch-irq { 552*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_cs4_n_pk2"; 553*b2d2a78aSEmmanuel Vadot nvidia,function = "gmi"; 554*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 555*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 556*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 557*b2d2a78aSEmmanuel Vadot }; 558*b2d2a78aSEmmanuel Vadot 559*b2d2a78aSEmmanuel Vadot touch-rst { 560*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_cs3_n_pk4"; 561*b2d2a78aSEmmanuel Vadot nvidia,function = "gmi"; 562*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 563*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 564*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 565*b2d2a78aSEmmanuel Vadot }; 566*b2d2a78aSEmmanuel Vadot 567*b2d2a78aSEmmanuel Vadot touch-pwr { 568*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad8_ph0"; 569*b2d2a78aSEmmanuel Vadot nvidia,function = "gmi"; 570*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 571*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 572*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 573*b2d2a78aSEmmanuel Vadot }; 574*b2d2a78aSEmmanuel Vadot 575*b2d2a78aSEmmanuel Vadot touch-vio { 576*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad12_ph4"; 577*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd4"; 578*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 579*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 580*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 581*b2d2a78aSEmmanuel Vadot }; 582*b2d2a78aSEmmanuel Vadot 583*b2d2a78aSEmmanuel Vadot /* AUDIO pinmux */ 584*b2d2a78aSEmmanuel Vadot audio-ldo1 { 585*b2d2a78aSEmmanuel Vadot nvidia,pins = "sdmmc1_wp_n_pv3"; 586*b2d2a78aSEmmanuel Vadot nvidia,function = "sdmmc1"; 587*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 588*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 589*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 590*b2d2a78aSEmmanuel Vadot }; 591*b2d2a78aSEmmanuel Vadot 592*b2d2a78aSEmmanuel Vadot hp-detect { 593*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_row7_pr7"; 594*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 595*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 596*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 597*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 598*b2d2a78aSEmmanuel Vadot }; 599*b2d2a78aSEmmanuel Vadot 600*b2d2a78aSEmmanuel Vadot dap-i2s0-in { 601*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap1_din_pn1"; 602*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s0"; 603*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 604*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 605*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 606*b2d2a78aSEmmanuel Vadot }; 607*b2d2a78aSEmmanuel Vadot 608*b2d2a78aSEmmanuel Vadot dap-i2s0-out { 609*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap1_dout_pn2", 610*b2d2a78aSEmmanuel Vadot "dap1_fs_pn0", 611*b2d2a78aSEmmanuel Vadot "dap1_sclk_pn3"; 612*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s0"; 613*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 614*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 615*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 616*b2d2a78aSEmmanuel Vadot }; 617*b2d2a78aSEmmanuel Vadot 618*b2d2a78aSEmmanuel Vadot dap-i2s1-in { 619*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap2_din_pa4"; 620*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s1"; 621*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 622*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 623*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 624*b2d2a78aSEmmanuel Vadot }; 625*b2d2a78aSEmmanuel Vadot 626*b2d2a78aSEmmanuel Vadot dap-i2s1-out { 627*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap2_dout_pa5", 628*b2d2a78aSEmmanuel Vadot "dap2_fs_pa2", 629*b2d2a78aSEmmanuel Vadot "dap2_sclk_pa3"; 630*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s1"; 631*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 632*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 633*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 634*b2d2a78aSEmmanuel Vadot }; 635*b2d2a78aSEmmanuel Vadot 636*b2d2a78aSEmmanuel Vadot dap-i2s2-in { 637*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap3_fs_pp0", 638*b2d2a78aSEmmanuel Vadot "dap3_sclk_pp3"; 639*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s2"; 640*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 641*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 642*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 643*b2d2a78aSEmmanuel Vadot }; 644*b2d2a78aSEmmanuel Vadot 645*b2d2a78aSEmmanuel Vadot dap-i2s2-out { 646*b2d2a78aSEmmanuel Vadot nvidia,pins = "dap3_din_pp1"; 647*b2d2a78aSEmmanuel Vadot nvidia,function = "i2s2"; 648*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 649*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 650*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 651*b2d2a78aSEmmanuel Vadot }; 652*b2d2a78aSEmmanuel Vadot 653*b2d2a78aSEmmanuel Vadot spdif-in { 654*b2d2a78aSEmmanuel Vadot nvidia,pins = "spdif_in_pk6"; 655*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd3"; 656*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 657*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 658*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 659*b2d2a78aSEmmanuel Vadot }; 660*b2d2a78aSEmmanuel Vadot 661*b2d2a78aSEmmanuel Vadot spdif-out { 662*b2d2a78aSEmmanuel Vadot nvidia,pins = "spdif_out_pk5"; 663*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 664*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 665*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 666*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 667*b2d2a78aSEmmanuel Vadot }; 668*b2d2a78aSEmmanuel Vadot 669*b2d2a78aSEmmanuel Vadot /* AsusEC pinmux */ 670*b2d2a78aSEmmanuel Vadot ec-irq { 671*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_col5_pq5"; 672*b2d2a78aSEmmanuel Vadot nvidia,function = "kbc"; 673*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 674*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 675*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 676*b2d2a78aSEmmanuel Vadot }; 677*b2d2a78aSEmmanuel Vadot 678*b2d2a78aSEmmanuel Vadot ec-req { 679*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_col2_pq2"; 680*b2d2a78aSEmmanuel Vadot nvidia,function = "kbc"; 681*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 682*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 683*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 684*b2d2a78aSEmmanuel Vadot }; 685*b2d2a78aSEmmanuel Vadot 686*b2d2a78aSEmmanuel Vadot hotplug-i2c { 687*b2d2a78aSEmmanuel Vadot nvidia,pins = "ulpi_data7_po0"; 688*b2d2a78aSEmmanuel Vadot nvidia,function = "spi2"; 689*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 690*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 691*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 692*b2d2a78aSEmmanuel Vadot }; 693*b2d2a78aSEmmanuel Vadot 694*b2d2a78aSEmmanuel Vadot ps2-irq { 695*b2d2a78aSEmmanuel Vadot nvidia,pins = "gpio_w2_aud_pw2"; 696*b2d2a78aSEmmanuel Vadot nvidia,function = "spi6"; 697*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 698*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 699*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 700*b2d2a78aSEmmanuel Vadot }; 701*b2d2a78aSEmmanuel Vadot 702*b2d2a78aSEmmanuel Vadot kbd-irq { 703*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_cs0_n_pj0"; 704*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 705*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 706*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 707*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 708*b2d2a78aSEmmanuel Vadot }; 709*b2d2a78aSEmmanuel Vadot 710*b2d2a78aSEmmanuel Vadot dvfs-pin { 711*b2d2a78aSEmmanuel Vadot nvidia,pins = "dvfs_pwm_px0", 712*b2d2a78aSEmmanuel Vadot "dvfs_clk_px2"; 713*b2d2a78aSEmmanuel Vadot nvidia,function = "cldvfs"; 714*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 715*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 716*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 717*b2d2a78aSEmmanuel Vadot }; 718*b2d2a78aSEmmanuel Vadot 719*b2d2a78aSEmmanuel Vadot /* Core pinmux */ 720*b2d2a78aSEmmanuel Vadot clk-32k-out { 721*b2d2a78aSEmmanuel Vadot nvidia,pins = "clk_32k_out_pa0"; 722*b2d2a78aSEmmanuel Vadot nvidia,function = "soc"; 723*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 724*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 725*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 726*b2d2a78aSEmmanuel Vadot }; 727*b2d2a78aSEmmanuel Vadot 728*b2d2a78aSEmmanuel Vadot sys-clk-req { 729*b2d2a78aSEmmanuel Vadot nvidia,pins = "sys_clk_req_pz5"; 730*b2d2a78aSEmmanuel Vadot nvidia,function = "sysclk"; 731*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 732*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 733*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 734*b2d2a78aSEmmanuel Vadot }; 735*b2d2a78aSEmmanuel Vadot 736*b2d2a78aSEmmanuel Vadot core-pwr-req { 737*b2d2a78aSEmmanuel Vadot nvidia,pins = "core_pwr_req"; 738*b2d2a78aSEmmanuel Vadot nvidia,function = "pwron"; 739*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 740*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 741*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 742*b2d2a78aSEmmanuel Vadot }; 743*b2d2a78aSEmmanuel Vadot 744*b2d2a78aSEmmanuel Vadot cpu-pwr-req { 745*b2d2a78aSEmmanuel Vadot nvidia,pins = "cpu_pwr_req"; 746*b2d2a78aSEmmanuel Vadot nvidia,function = "cpu"; 747*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 748*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 749*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 750*b2d2a78aSEmmanuel Vadot }; 751*b2d2a78aSEmmanuel Vadot 752*b2d2a78aSEmmanuel Vadot pwr-int-n { 753*b2d2a78aSEmmanuel Vadot nvidia,pins = "pwr_int_n"; 754*b2d2a78aSEmmanuel Vadot nvidia,function = "pmi"; 755*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 756*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 757*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 758*b2d2a78aSEmmanuel Vadot }; 759*b2d2a78aSEmmanuel Vadot 760*b2d2a78aSEmmanuel Vadot clk-32k-in { 761*b2d2a78aSEmmanuel Vadot nvidia,pins = "clk_32k_in"; 762*b2d2a78aSEmmanuel Vadot nvidia,function = "clk"; 763*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 764*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 765*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 766*b2d2a78aSEmmanuel Vadot }; 767*b2d2a78aSEmmanuel Vadot 768*b2d2a78aSEmmanuel Vadot owr { 769*b2d2a78aSEmmanuel Vadot nvidia,pins = "owr"; 770*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 771*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 772*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 773*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 774*b2d2a78aSEmmanuel Vadot }; 775*b2d2a78aSEmmanuel Vadot 776*b2d2a78aSEmmanuel Vadot reset-out-n { 777*b2d2a78aSEmmanuel Vadot nvidia,pins = "reset_out_n"; 778*b2d2a78aSEmmanuel Vadot nvidia,function = "reset_out_n"; 779*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 780*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 781*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 782*b2d2a78aSEmmanuel Vadot }; 783*b2d2a78aSEmmanuel Vadot 784*b2d2a78aSEmmanuel Vadot /* ULPI pinmux */ 785*b2d2a78aSEmmanuel Vadot ulpi-data0-6 { 786*b2d2a78aSEmmanuel Vadot nvidia,pins = "ulpi_data0_po1", 787*b2d2a78aSEmmanuel Vadot "ulpi_data6_po7"; 788*b2d2a78aSEmmanuel Vadot nvidia,function = "ulpi"; 789*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 790*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 791*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 792*b2d2a78aSEmmanuel Vadot }; 793*b2d2a78aSEmmanuel Vadot 794*b2d2a78aSEmmanuel Vadot ulpi-data1-5 { 795*b2d2a78aSEmmanuel Vadot nvidia,pins = "ulpi_data1_po2", 796*b2d2a78aSEmmanuel Vadot "ulpi_data5_po6"; 797*b2d2a78aSEmmanuel Vadot nvidia,function = "ulpi"; 798*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 799*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 800*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 801*b2d2a78aSEmmanuel Vadot }; 802*b2d2a78aSEmmanuel Vadot 803*b2d2a78aSEmmanuel Vadot ulpi-data2-3 { 804*b2d2a78aSEmmanuel Vadot nvidia,pins = "ulpi_data2_po3", 805*b2d2a78aSEmmanuel Vadot "ulpi_data3_po4"; 806*b2d2a78aSEmmanuel Vadot nvidia,function = "ulpi"; 807*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 808*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 809*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 810*b2d2a78aSEmmanuel Vadot }; 811*b2d2a78aSEmmanuel Vadot 812*b2d2a78aSEmmanuel Vadot /* PORT V */ 813*b2d2a78aSEmmanuel Vadot pv0-gpio { 814*b2d2a78aSEmmanuel Vadot nvidia,pins = "pv0"; 815*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 816*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 817*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 818*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 819*b2d2a78aSEmmanuel Vadot }; 820*b2d2a78aSEmmanuel Vadot 821*b2d2a78aSEmmanuel Vadot pv1-gpio { 822*b2d2a78aSEmmanuel Vadot nvidia,pins = "pv1"; 823*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 824*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 825*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 826*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 827*b2d2a78aSEmmanuel Vadot }; 828*b2d2a78aSEmmanuel Vadot 829*b2d2a78aSEmmanuel Vadot /* PORT U */ 830*b2d2a78aSEmmanuel Vadot pu0-gpio { 831*b2d2a78aSEmmanuel Vadot nvidia,pins = "pu0"; 832*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd3"; 833*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 834*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 835*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 836*b2d2a78aSEmmanuel Vadot }; 837*b2d2a78aSEmmanuel Vadot 838*b2d2a78aSEmmanuel Vadot pu2-gpio { 839*b2d2a78aSEmmanuel Vadot nvidia,pins = "pu2"; 840*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 841*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 842*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 843*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 844*b2d2a78aSEmmanuel Vadot }; 845*b2d2a78aSEmmanuel Vadot 846*b2d2a78aSEmmanuel Vadot /* PWM pinmux */ 847*b2d2a78aSEmmanuel Vadot pwm0 { 848*b2d2a78aSEmmanuel Vadot nvidia,pins = "pu3"; 849*b2d2a78aSEmmanuel Vadot nvidia,function = "pwm0"; 850*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 851*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 852*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 853*b2d2a78aSEmmanuel Vadot }; 854*b2d2a78aSEmmanuel Vadot 855*b2d2a78aSEmmanuel Vadot pwm1 { 856*b2d2a78aSEmmanuel Vadot nvidia,pins = "pu4"; 857f126890aSEmmanuel Vadot nvidia,function = "pwm1"; 858f126890aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 859f126890aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 860f126890aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 861f126890aSEmmanuel Vadot }; 862*b2d2a78aSEmmanuel Vadot 863*b2d2a78aSEmmanuel Vadot /* EXTPERIPH pinmux */ 864*b2d2a78aSEmmanuel Vadot clk1-out { 865*b2d2a78aSEmmanuel Vadot nvidia,pins = "clk1_out_pw4"; 866*b2d2a78aSEmmanuel Vadot nvidia,function = "extperiph1"; 867*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 868*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 869*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 870f126890aSEmmanuel Vadot }; 871f126890aSEmmanuel Vadot 872*b2d2a78aSEmmanuel Vadot clk2-out { 873*b2d2a78aSEmmanuel Vadot nvidia,pins = "clk2_out_pw5"; 874*b2d2a78aSEmmanuel Vadot nvidia,function = "extperiph2"; 875*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 876*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 877*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 878*b2d2a78aSEmmanuel Vadot }; 879*b2d2a78aSEmmanuel Vadot 880*b2d2a78aSEmmanuel Vadot clk3-out { 881*b2d2a78aSEmmanuel Vadot nvidia,pins = "clk3_out_pee0"; 882*b2d2a78aSEmmanuel Vadot nvidia,function = "extperiph3"; 883*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 884*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 885*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 886*b2d2a78aSEmmanuel Vadot }; 887*b2d2a78aSEmmanuel Vadot 888*b2d2a78aSEmmanuel Vadot clk1-req { 889*b2d2a78aSEmmanuel Vadot nvidia,pins = "clk1_req_pee2"; 890*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd3"; 891*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 892*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 893*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 894*b2d2a78aSEmmanuel Vadot }; 895*b2d2a78aSEmmanuel Vadot 896*b2d2a78aSEmmanuel Vadot /* GMI pinmux */ 897*b2d2a78aSEmmanuel Vadot gmi-wp-n { 898*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_wp_n_pc7"; 899*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 900*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 901*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 902*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 903*b2d2a78aSEmmanuel Vadot }; 904*b2d2a78aSEmmanuel Vadot 905*b2d2a78aSEmmanuel Vadot gmi-adv { 906*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_adv_n_pk0"; 907*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 908*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 909*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 910*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 911*b2d2a78aSEmmanuel Vadot }; 912*b2d2a78aSEmmanuel Vadot 913*b2d2a78aSEmmanuel Vadot gmi-ad0-ad1 { 914*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad0_pg0", 915*b2d2a78aSEmmanuel Vadot "gmi_ad1_pg1"; 916*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 917*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 918*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 919*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 920*b2d2a78aSEmmanuel Vadot }; 921*b2d2a78aSEmmanuel Vadot 922*b2d2a78aSEmmanuel Vadot gmi-ad2-ad3 { 923*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad2_pg2", 924*b2d2a78aSEmmanuel Vadot "gmi_ad3_pg3"; 925*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 926*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 927*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 928*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 929*b2d2a78aSEmmanuel Vadot }; 930*b2d2a78aSEmmanuel Vadot 931*b2d2a78aSEmmanuel Vadot gmi-iordy { 932*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_iordy_pi5"; 933*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 934*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 935*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 936*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 937*b2d2a78aSEmmanuel Vadot }; 938*b2d2a78aSEmmanuel Vadot 939*b2d2a78aSEmmanuel Vadot gmi-a18 { 940*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_a18_pb1"; 941*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 942*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 943*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 944*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 945*b2d2a78aSEmmanuel Vadot }; 946*b2d2a78aSEmmanuel Vadot 947*b2d2a78aSEmmanuel Vadot gmi-wait { 948*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_wait_pi7"; 949*b2d2a78aSEmmanuel Vadot nvidia,function = "nand"; 950*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 951*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 952*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 953*b2d2a78aSEmmanuel Vadot }; 954*b2d2a78aSEmmanuel Vadot 955*b2d2a78aSEmmanuel Vadot gmi-cs6-n { 956*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_cs6_n_pi3"; 957*b2d2a78aSEmmanuel Vadot nvidia,function = "nand"; 958*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 959*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 960*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 961*b2d2a78aSEmmanuel Vadot }; 962*b2d2a78aSEmmanuel Vadot 963*b2d2a78aSEmmanuel Vadot gmi-cs7-n { 964*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_cs7_n_pi6"; 965*b2d2a78aSEmmanuel Vadot nvidia,function = "nand"; 966*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 967*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 968*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 969*b2d2a78aSEmmanuel Vadot }; 970*b2d2a78aSEmmanuel Vadot 971*b2d2a78aSEmmanuel Vadot gmi-dqs-p { 972*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_dqs_p_pj3"; 973*b2d2a78aSEmmanuel Vadot nvidia,function = "nand"; 974*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 975*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 976*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 977*b2d2a78aSEmmanuel Vadot }; 978*b2d2a78aSEmmanuel Vadot 979*b2d2a78aSEmmanuel Vadot gmi-cs2-ad { 980*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_cs2_n_pk3", 981*b2d2a78aSEmmanuel Vadot "gmi_ad14_ph6", 982*b2d2a78aSEmmanuel Vadot "gmi_ad15_ph7"; 983*b2d2a78aSEmmanuel Vadot nvidia,function = "gmi"; 984*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 985*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 986*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 987*b2d2a78aSEmmanuel Vadot }; 988*b2d2a78aSEmmanuel Vadot 989*b2d2a78aSEmmanuel Vadot gmi-cs4-clk { 990*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_cs4_n_pk2", 991*b2d2a78aSEmmanuel Vadot "gmi_clk_lb"; 992*b2d2a78aSEmmanuel Vadot nvidia,function = "gmi"; 993*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 994*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 995*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 996*b2d2a78aSEmmanuel Vadot }; 997*b2d2a78aSEmmanuel Vadot 998*b2d2a78aSEmmanuel Vadot gmi-ad11 { 999*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad11_ph3"; 1000*b2d2a78aSEmmanuel Vadot nvidia,function = "gmi"; 1001*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1002*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1003*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1004*b2d2a78aSEmmanuel Vadot }; 1005*b2d2a78aSEmmanuel Vadot 1006*b2d2a78aSEmmanuel Vadot gmi-cs1-oe { 1007*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_cs1_n_pj2", 1008*b2d2a78aSEmmanuel Vadot "gmi_oe_n_pi1"; 1009*b2d2a78aSEmmanuel Vadot nvidia,function = "soc"; 1010*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 1011*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1012*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1013*b2d2a78aSEmmanuel Vadot }; 1014*b2d2a78aSEmmanuel Vadot 1015*b2d2a78aSEmmanuel Vadot gmi-ad4 { 1016*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad4_pg4"; 1017*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd4"; 1018*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1019*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1020*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1021*b2d2a78aSEmmanuel Vadot }; 1022*b2d2a78aSEmmanuel Vadot 1023*b2d2a78aSEmmanuel Vadot gmi-ad13 { 1024*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_ad13_ph5"; 1025*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd4"; 1026*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1027*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 1028*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1029*b2d2a78aSEmmanuel Vadot }; 1030*b2d2a78aSEmmanuel Vadot 1031*b2d2a78aSEmmanuel Vadot gmi-rst-n { 1032*b2d2a78aSEmmanuel Vadot nvidia,pins = "gmi_rst_n_pi4"; 1033*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd4"; 1034*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1035*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1036*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1037*b2d2a78aSEmmanuel Vadot }; 1038*b2d2a78aSEmmanuel Vadot 1039*b2d2a78aSEmmanuel Vadot /* PORT CC */ 1040*b2d2a78aSEmmanuel Vadot pcc-gpio { 1041*b2d2a78aSEmmanuel Vadot nvidia,pins = "pcc1", "pcc2"; 1042*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 1043*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1044*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1045*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1046*b2d2a78aSEmmanuel Vadot }; 1047*b2d2a78aSEmmanuel Vadot 1048*b2d2a78aSEmmanuel Vadot /* PORT BB */ 1049*b2d2a78aSEmmanuel Vadot pbb3-gpio { 1050*b2d2a78aSEmmanuel Vadot nvidia,pins = "pbb3"; 1051*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd4"; 1052*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1053*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1054*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1055*b2d2a78aSEmmanuel Vadot }; 1056*b2d2a78aSEmmanuel Vadot 1057*b2d2a78aSEmmanuel Vadot pbb4-5-6-gpio { 1058*b2d2a78aSEmmanuel Vadot nvidia,pins = "pbb4", "pbb5", "pbb6"; 1059*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd4"; 1060*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1061*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1062*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1063*b2d2a78aSEmmanuel Vadot }; 1064*b2d2a78aSEmmanuel Vadot 1065*b2d2a78aSEmmanuel Vadot pbb7-gpio { 1066*b2d2a78aSEmmanuel Vadot nvidia,pins = "pbb7"; 1067*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 1068*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1069*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1070*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1071*b2d2a78aSEmmanuel Vadot }; 1072*b2d2a78aSEmmanuel Vadot 1073*b2d2a78aSEmmanuel Vadot /* KBC pinmux */ 1074*b2d2a78aSEmmanuel Vadot kb-r0-c1 { 1075*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_row0_pr0", 1076*b2d2a78aSEmmanuel Vadot "kb_col1_pq1"; 1077*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 1078*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 1079*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1080*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1081*b2d2a78aSEmmanuel Vadot }; 1082*b2d2a78aSEmmanuel Vadot 1083*b2d2a78aSEmmanuel Vadot kb-row4 { 1084*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_row4_pr4"; 1085*b2d2a78aSEmmanuel Vadot nvidia,function = "kbc"; 1086*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1087*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 1088*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1089*b2d2a78aSEmmanuel Vadot }; 1090*b2d2a78aSEmmanuel Vadot 1091*b2d2a78aSEmmanuel Vadot kb-row5 { 1092*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_row5_pr5"; 1093*b2d2a78aSEmmanuel Vadot nvidia,function = "kbc"; 1094*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 1095*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 1096*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1097*b2d2a78aSEmmanuel Vadot }; 1098*b2d2a78aSEmmanuel Vadot 1099*b2d2a78aSEmmanuel Vadot kb-row6 { 1100*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_row6_pr6"; 1101*b2d2a78aSEmmanuel Vadot nvidia,function = "kbc"; 1102*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1103*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1104*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1105*b2d2a78aSEmmanuel Vadot }; 1106*b2d2a78aSEmmanuel Vadot 1107*b2d2a78aSEmmanuel Vadot kb-r8-c3 { 1108*b2d2a78aSEmmanuel Vadot nvidia,pins = "kb_row8_ps0", 1109*b2d2a78aSEmmanuel Vadot "kb_col3_pq3"; 1110*b2d2a78aSEmmanuel Vadot nvidia,function = "kbc"; 1111*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 1112*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1113*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1114*b2d2a78aSEmmanuel Vadot }; 1115*b2d2a78aSEmmanuel Vadot 1116*b2d2a78aSEmmanuel Vadot /* VI pinmux */ 1117*b2d2a78aSEmmanuel Vadot cam-mclk { 1118*b2d2a78aSEmmanuel Vadot nvidia,pins = "cam_mclk_pcc0", 1119*b2d2a78aSEmmanuel Vadot "pbb0"; 1120*b2d2a78aSEmmanuel Vadot nvidia,function = "vi_alt3"; 1121*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1122*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1123*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1124*b2d2a78aSEmmanuel Vadot }; 1125*b2d2a78aSEmmanuel Vadot 1126*b2d2a78aSEmmanuel Vadot /* AUD pinmux */ 1127*b2d2a78aSEmmanuel Vadot gpio-x4-aud { 1128*b2d2a78aSEmmanuel Vadot nvidia,pins = "gpio_x4_aud_px4"; 1129*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd1"; 1130*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1131*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1132*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1133*b2d2a78aSEmmanuel Vadot }; 1134*b2d2a78aSEmmanuel Vadot 1135*b2d2a78aSEmmanuel Vadot gpio-x1-aud { 1136*b2d2a78aSEmmanuel Vadot nvidia,pins = "gpio_x1_aud_px1"; 1137*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 1138*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 1139*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1140*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1141*b2d2a78aSEmmanuel Vadot }; 1142*b2d2a78aSEmmanuel Vadot 1143*b2d2a78aSEmmanuel Vadot gpio-x3-aud { 1144*b2d2a78aSEmmanuel Vadot nvidia,pins = "gpio_x3_aud_px3"; 1145*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd3"; 1146*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 1147*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1148*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1149*b2d2a78aSEmmanuel Vadot }; 1150*b2d2a78aSEmmanuel Vadot 1151*b2d2a78aSEmmanuel Vadot gpio-x6-aud { 1152*b2d2a78aSEmmanuel Vadot nvidia,pins = "gpio_x6_aud_px6"; 1153*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd4"; 1154*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_UP>; 1155*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_DISABLE>; 1156*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1157*b2d2a78aSEmmanuel Vadot }; 1158*b2d2a78aSEmmanuel Vadot 1159*b2d2a78aSEmmanuel Vadot usb-vbus { 1160*b2d2a78aSEmmanuel Vadot nvidia,pins = "usb_vbus_en0_pn4", 1161*b2d2a78aSEmmanuel Vadot "usb_vbus_en1_pn5"; 1162*b2d2a78aSEmmanuel Vadot nvidia,function = "rsvd2"; 1163*b2d2a78aSEmmanuel Vadot nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1164*b2d2a78aSEmmanuel Vadot nvidia,tristate = <TEGRA_PIN_ENABLE>; 1165*b2d2a78aSEmmanuel Vadot nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1166*b2d2a78aSEmmanuel Vadot }; 1167*b2d2a78aSEmmanuel Vadot 1168*b2d2a78aSEmmanuel Vadot /* GPIO power/drive control */ 1169*b2d2a78aSEmmanuel Vadot drive-sdio1 { 1170*b2d2a78aSEmmanuel Vadot nvidia,pins = "drive_sdio1"; 1171*b2d2a78aSEmmanuel Vadot nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 1172*b2d2a78aSEmmanuel Vadot nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1173*b2d2a78aSEmmanuel Vadot nvidia,pull-down-strength = <36>; 1174*b2d2a78aSEmmanuel Vadot nvidia,pull-up-strength = <20>; 1175*b2d2a78aSEmmanuel Vadot nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; 1176*b2d2a78aSEmmanuel Vadot nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; 1177*b2d2a78aSEmmanuel Vadot }; 1178*b2d2a78aSEmmanuel Vadot 1179*b2d2a78aSEmmanuel Vadot drive-sdio3 { 1180f126890aSEmmanuel Vadot nvidia,pins = "drive_sdio3"; 1181f126890aSEmmanuel Vadot nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 1182f126890aSEmmanuel Vadot nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1183f126890aSEmmanuel Vadot nvidia,pull-down-strength = <22>; 1184f126890aSEmmanuel Vadot nvidia,pull-up-strength = <36>; 1185f126890aSEmmanuel Vadot nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1186f126890aSEmmanuel Vadot nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1187f126890aSEmmanuel Vadot }; 1188f126890aSEmmanuel Vadot 1189*b2d2a78aSEmmanuel Vadot drive-gma { 1190*b2d2a78aSEmmanuel Vadot nvidia,pins = "drive_gma"; 1191*b2d2a78aSEmmanuel Vadot nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 1192*b2d2a78aSEmmanuel Vadot nvidia,schmitt = <TEGRA_PIN_DISABLE>; 1193*b2d2a78aSEmmanuel Vadot nvidia,pull-down-strength = <2>; 1194*b2d2a78aSEmmanuel Vadot nvidia,pull-up-strength = <2>; 1195*b2d2a78aSEmmanuel Vadot nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1196*b2d2a78aSEmmanuel Vadot nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 1197f126890aSEmmanuel Vadot }; 1198f126890aSEmmanuel Vadot }; 1199f126890aSEmmanuel Vadot }; 1200f126890aSEmmanuel Vadot 1201f126890aSEmmanuel Vadot serial@70006040 { 1202f126890aSEmmanuel Vadot /* GPS */ 1203f126890aSEmmanuel Vadot }; 1204f126890aSEmmanuel Vadot 1205f126890aSEmmanuel Vadot serial@70006200 { 1206*b2d2a78aSEmmanuel Vadot compatible = "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart"; 1207*b2d2a78aSEmmanuel Vadot reset-names = "serial"; 1208*b2d2a78aSEmmanuel Vadot /delete-property/ reg-shift; 1209*b2d2a78aSEmmanuel Vadot status = "okay"; 1210*b2d2a78aSEmmanuel Vadot 1211*b2d2a78aSEmmanuel Vadot nvidia,adjust-baud-rates = <0 9600 100>, 1212*b2d2a78aSEmmanuel Vadot <9600 115200 200>, 1213*b2d2a78aSEmmanuel Vadot <1000000 4000000 136>; 1214*b2d2a78aSEmmanuel Vadot 1215*b2d2a78aSEmmanuel Vadot bluetooth { 1216*b2d2a78aSEmmanuel Vadot compatible = "brcm,bcm4334-bt"; 1217*b2d2a78aSEmmanuel Vadot max-speed = <4000000>; 1218*b2d2a78aSEmmanuel Vadot 1219*b2d2a78aSEmmanuel Vadot clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 1220*b2d2a78aSEmmanuel Vadot clock-names = "txco"; 1221*b2d2a78aSEmmanuel Vadot 1222*b2d2a78aSEmmanuel Vadot interrupt-parent = <&gpio>; 1223*b2d2a78aSEmmanuel Vadot interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 1224*b2d2a78aSEmmanuel Vadot interrupt-names = "host-wakeup"; 1225*b2d2a78aSEmmanuel Vadot 1226*b2d2a78aSEmmanuel Vadot device-wakeup-gpios = <&gpio TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>; 1227*b2d2a78aSEmmanuel Vadot shutdown-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; 1228*b2d2a78aSEmmanuel Vadot reset-gpios = <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>; 1229*b2d2a78aSEmmanuel Vadot 1230*b2d2a78aSEmmanuel Vadot vbat-supply = <&vdd_3v3_com>; 1231*b2d2a78aSEmmanuel Vadot vddio-supply = <&vdd_1v8_vio>; 1232*b2d2a78aSEmmanuel Vadot }; 1233f126890aSEmmanuel Vadot }; 1234f126890aSEmmanuel Vadot 1235f126890aSEmmanuel Vadot serial@70006300 { 1236aa1a8ff2SEmmanuel Vadot /delete-property/ dmas; 1237aa1a8ff2SEmmanuel Vadot /delete-property/ dma-names; 1238f126890aSEmmanuel Vadot status = "okay"; 1239f126890aSEmmanuel Vadot }; 1240f126890aSEmmanuel Vadot 1241f126890aSEmmanuel Vadot pwm@7000a000 { 1242f126890aSEmmanuel Vadot status = "okay"; 1243f126890aSEmmanuel Vadot }; 1244f126890aSEmmanuel Vadot 1245f126890aSEmmanuel Vadot i2c@7000c000 { 1246f126890aSEmmanuel Vadot status = "okay"; 1247f126890aSEmmanuel Vadot clock-frequency = <100000>; 1248f126890aSEmmanuel Vadot 1249f126890aSEmmanuel Vadot magnetometer@c { 1250f126890aSEmmanuel Vadot compatible = "asahi-kasei,ak09911"; 1251f126890aSEmmanuel Vadot reg = <0xc>; 1252f126890aSEmmanuel Vadot 1253*b2d2a78aSEmmanuel Vadot /* no DRDY (polling) */ 1254*b2d2a78aSEmmanuel Vadot 1255*b2d2a78aSEmmanuel Vadot vdd-supply = <&vdd_2v85_sen>; 1256*b2d2a78aSEmmanuel Vadot vid-supply = <&vdd_1v8_vio>; 1257*b2d2a78aSEmmanuel Vadot 1258*b2d2a78aSEmmanuel Vadot mount-matrix = "0", "1", "0", 1259*b2d2a78aSEmmanuel Vadot "1", "0", "0", 1260*b2d2a78aSEmmanuel Vadot "0", "0","-1"; 1261f126890aSEmmanuel Vadot }; 1262f126890aSEmmanuel Vadot 1263f126890aSEmmanuel Vadot rt5639: audio-codec@1c { 1264f126890aSEmmanuel Vadot compatible = "realtek,rt5639"; 1265f126890aSEmmanuel Vadot reg = <0x1c>; 1266f126890aSEmmanuel Vadot 1267*b2d2a78aSEmmanuel Vadot realtek,ldo1-en-gpios = 1268*b2d2a78aSEmmanuel Vadot <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; 1269f126890aSEmmanuel Vadot 1270*b2d2a78aSEmmanuel Vadot clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1271*b2d2a78aSEmmanuel Vadot clock-names = "mclk"; 1272f126890aSEmmanuel Vadot }; 1273f126890aSEmmanuel Vadot 1274f126890aSEmmanuel Vadot temp_sensor: temperature-sensor@4c { 1275f126890aSEmmanuel Vadot compatible = "onnn,nct1008"; 1276f126890aSEmmanuel Vadot reg = <0x4c>; 1277f126890aSEmmanuel Vadot 1278*b2d2a78aSEmmanuel Vadot interrupt-parent = <&gpio>; 1279*b2d2a78aSEmmanuel Vadot interrupts = <TEGRA_GPIO(O, 4) IRQ_TYPE_EDGE_FALLING>; 1280*b2d2a78aSEmmanuel Vadot 1281*b2d2a78aSEmmanuel Vadot vcc-supply = <&vdd_1v8_vio>; 1282f126890aSEmmanuel Vadot #thermal-sensor-cells = <1>; 1283f126890aSEmmanuel Vadot }; 1284f126890aSEmmanuel Vadot 1285f126890aSEmmanuel Vadot motion-tracker@68 { 1286f126890aSEmmanuel Vadot compatible = "invensense,mpu6500"; 1287f126890aSEmmanuel Vadot reg = <0x68>; 1288f126890aSEmmanuel Vadot 1289f126890aSEmmanuel Vadot interrupt-parent = <&gpio>; 1290f126890aSEmmanuel Vadot interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>; 1291f126890aSEmmanuel Vadot 1292*b2d2a78aSEmmanuel Vadot vdd-supply = <&vdd_2v85_sen>; 1293*b2d2a78aSEmmanuel Vadot vddio-supply = <&vdd_1v8_vio>; 1294*b2d2a78aSEmmanuel Vadot 1295f126890aSEmmanuel Vadot mount-matrix = "0", "-1", "0", 1296f126890aSEmmanuel Vadot "1", "0", "0", 1297f126890aSEmmanuel Vadot "0", "0", "1"; 1298f126890aSEmmanuel Vadot }; 1299f126890aSEmmanuel Vadot }; 1300f126890aSEmmanuel Vadot 1301f126890aSEmmanuel Vadot i2c@7000c400 { 1302f126890aSEmmanuel Vadot status = "okay"; 1303f126890aSEmmanuel Vadot clock-frequency = <100000>; 1304f126890aSEmmanuel Vadot 1305f126890aSEmmanuel Vadot power-sensor@44 { 1306f126890aSEmmanuel Vadot compatible = "ti,ina230"; 1307f126890aSEmmanuel Vadot reg = <0x44>; 1308*b2d2a78aSEmmanuel Vadot 1309*b2d2a78aSEmmanuel Vadot shunt-resistor = <5000>; 1310f126890aSEmmanuel Vadot }; 1311f126890aSEmmanuel Vadot }; 1312f126890aSEmmanuel Vadot 1313f126890aSEmmanuel Vadot i2c@7000c500 { 1314f126890aSEmmanuel Vadot status = "okay"; 1315f126890aSEmmanuel Vadot clock-frequency = <400000>; 1316f126890aSEmmanuel Vadot 1317f126890aSEmmanuel Vadot light-sensor@1c { 1318f126890aSEmmanuel Vadot compatible = "dynaimage,al3320a"; 1319f126890aSEmmanuel Vadot reg = <0x1c>; 1320f126890aSEmmanuel Vadot 1321*b2d2a78aSEmmanuel Vadot vdd-supply = <&vdd_1v8_vio>; 1322f126890aSEmmanuel Vadot }; 1323f126890aSEmmanuel Vadot }; 1324f126890aSEmmanuel Vadot 1325*b2d2a78aSEmmanuel Vadot hdmi_ddc: i2c@7000c700 { 1326*b2d2a78aSEmmanuel Vadot status = "okay"; 1327*b2d2a78aSEmmanuel Vadot clock-frequency = <10000>; 1328f126890aSEmmanuel Vadot }; 1329f126890aSEmmanuel Vadot 1330f126890aSEmmanuel Vadot i2c@7000d000 { 1331f126890aSEmmanuel Vadot status = "okay"; 1332f126890aSEmmanuel Vadot clock-frequency = <400000>; 1333f126890aSEmmanuel Vadot 1334f126890aSEmmanuel Vadot palmas: pmic@58 { 1335f126890aSEmmanuel Vadot compatible = "ti,tps65913", "ti,palmas"; 1336f126890aSEmmanuel Vadot reg = <0x58>; 1337f126890aSEmmanuel Vadot interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1338f126890aSEmmanuel Vadot 1339f126890aSEmmanuel Vadot #interrupt-cells = <2>; 1340f126890aSEmmanuel Vadot interrupt-controller; 1341f126890aSEmmanuel Vadot 1342f126890aSEmmanuel Vadot ti,system-power-controller; 1343f126890aSEmmanuel Vadot 1344*b2d2a78aSEmmanuel Vadot palmas_gpadc: adc { 1345*b2d2a78aSEmmanuel Vadot compatible = "ti,palmas-gpadc"; 1346*b2d2a78aSEmmanuel Vadot interrupts = <18 IRQ_TYPE_NONE>, 1347*b2d2a78aSEmmanuel Vadot <16 IRQ_TYPE_NONE>, 1348*b2d2a78aSEmmanuel Vadot <17 IRQ_TYPE_NONE>; 1349*b2d2a78aSEmmanuel Vadot 1350*b2d2a78aSEmmanuel Vadot ti,channel0-current-microamp = <5>; 1351*b2d2a78aSEmmanuel Vadot ti,channel3-current-microamp = <400>; 1352*b2d2a78aSEmmanuel Vadot ti,enable-extended-delay; 1353*b2d2a78aSEmmanuel Vadot 1354*b2d2a78aSEmmanuel Vadot #io-channel-cells = <1>; 1355*b2d2a78aSEmmanuel Vadot }; 1356*b2d2a78aSEmmanuel Vadot 1357*b2d2a78aSEmmanuel Vadot palmas_extcon: extcon { 1358*b2d2a78aSEmmanuel Vadot compatible = "ti,palmas-usb-vid"; 1359*b2d2a78aSEmmanuel Vadot ti,enable-vbus-detection; 1360*b2d2a78aSEmmanuel Vadot ti,enable-id-detection; 1361*b2d2a78aSEmmanuel Vadot }; 1362*b2d2a78aSEmmanuel Vadot 1363f126890aSEmmanuel Vadot palmas_gpio: gpio { 1364f126890aSEmmanuel Vadot compatible = "ti,palmas-gpio"; 1365f126890aSEmmanuel Vadot gpio-controller; 1366f126890aSEmmanuel Vadot #gpio-cells = <2>; 1367f126890aSEmmanuel Vadot }; 1368f126890aSEmmanuel Vadot 1369*b2d2a78aSEmmanuel Vadot palmas_clk32kg@0 { 1370*b2d2a78aSEmmanuel Vadot compatible = "ti,palmas-clk32kg"; 1371*b2d2a78aSEmmanuel Vadot #clock-cells = <0>; 1372*b2d2a78aSEmmanuel Vadot }; 1373*b2d2a78aSEmmanuel Vadot 1374f126890aSEmmanuel Vadot pinmux { 1375f126890aSEmmanuel Vadot compatible = "ti,tps65913-pinctrl"; 1376f126890aSEmmanuel Vadot ti,palmas-enable-dvfs1; 1377f126890aSEmmanuel Vadot 1378f126890aSEmmanuel Vadot pinctrl-names = "default"; 1379f126890aSEmmanuel Vadot pinctrl-0 = <&palmas_default>; 1380f126890aSEmmanuel Vadot 1381f126890aSEmmanuel Vadot palmas_default: pinmux { 1382f126890aSEmmanuel Vadot pin_gpio0 { 1383f126890aSEmmanuel Vadot pins = "gpio0"; 1384f126890aSEmmanuel Vadot function = "gpio"; 1385f126890aSEmmanuel Vadot }; 1386f126890aSEmmanuel Vadot 1387f126890aSEmmanuel Vadot pin_gpio1 { 1388f126890aSEmmanuel Vadot pins = "gpio1"; 1389f126890aSEmmanuel Vadot function = "gpio"; 1390f126890aSEmmanuel Vadot }; 1391f126890aSEmmanuel Vadot 1392f126890aSEmmanuel Vadot pin_gpio2 { 1393f126890aSEmmanuel Vadot pins = "gpio2"; 1394f126890aSEmmanuel Vadot function = "gpio"; 1395f126890aSEmmanuel Vadot }; 1396f126890aSEmmanuel Vadot 1397f126890aSEmmanuel Vadot pin_gpio3 { 1398f126890aSEmmanuel Vadot pins = "gpio3"; 1399f126890aSEmmanuel Vadot function = "gpio"; 1400f126890aSEmmanuel Vadot }; 1401f126890aSEmmanuel Vadot 1402f126890aSEmmanuel Vadot pin_gpio4 { 1403f126890aSEmmanuel Vadot pins = "gpio4"; 1404f126890aSEmmanuel Vadot function = "gpio"; 1405f126890aSEmmanuel Vadot }; 1406f126890aSEmmanuel Vadot 1407f126890aSEmmanuel Vadot pin_gpio5 { 1408f126890aSEmmanuel Vadot pins = "gpio5"; 1409f126890aSEmmanuel Vadot function = "gpio"; 1410f126890aSEmmanuel Vadot }; 1411f126890aSEmmanuel Vadot 1412f126890aSEmmanuel Vadot pin_gpio6 { 1413f126890aSEmmanuel Vadot pins = "gpio6"; 1414f126890aSEmmanuel Vadot function = "gpio"; 1415f126890aSEmmanuel Vadot }; 1416f126890aSEmmanuel Vadot 1417f126890aSEmmanuel Vadot pin_gpio7 { 1418f126890aSEmmanuel Vadot pins = "gpio7"; 1419f126890aSEmmanuel Vadot function = "gpio"; 1420f126890aSEmmanuel Vadot }; 1421f126890aSEmmanuel Vadot 1422f126890aSEmmanuel Vadot pin_powergood { 1423f126890aSEmmanuel Vadot pins = "powergood"; 1424f126890aSEmmanuel Vadot function = "powergood"; 1425f126890aSEmmanuel Vadot }; 1426f126890aSEmmanuel Vadot 1427f126890aSEmmanuel Vadot pin_vac { 1428f126890aSEmmanuel Vadot pins = "vac"; 1429f126890aSEmmanuel Vadot function = "vac"; 1430f126890aSEmmanuel Vadot }; 1431f126890aSEmmanuel Vadot }; 1432f126890aSEmmanuel Vadot }; 1433f126890aSEmmanuel Vadot 1434f126890aSEmmanuel Vadot pmic { 1435f126890aSEmmanuel Vadot compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; 1436f126890aSEmmanuel Vadot 1437*b2d2a78aSEmmanuel Vadot ldo1-in-supply = <&vddio_ddr>; 1438*b2d2a78aSEmmanuel Vadot ldo2-in-supply = <&vddio_ddr>; 1439*b2d2a78aSEmmanuel Vadot ldo4-in-supply = <&vdd_1v8_vio>; 1440*b2d2a78aSEmmanuel Vadot ldo5-in-supply = <&vcore_emmc>; 1441*b2d2a78aSEmmanuel Vadot ldo6-in-supply = <&vcore_emmc>; 1442*b2d2a78aSEmmanuel Vadot ldo7-in-supply = <&vcore_emmc>; 1443*b2d2a78aSEmmanuel Vadot ldo9-in-supply = <&vcore_emmc>; 1444*b2d2a78aSEmmanuel Vadot ldoln-in-supply = <&vdd_smps10_out2>; 1445f126890aSEmmanuel Vadot 1446f126890aSEmmanuel Vadot regulators { 1447*b2d2a78aSEmmanuel Vadot vdd_cpu: smps123 { 1448*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_cpu"; 1449f126890aSEmmanuel Vadot regulator-min-microvolt = <900000>; 1450f126890aSEmmanuel Vadot regulator-max-microvolt = <1350000>; 1451f126890aSEmmanuel Vadot regulator-always-on; 1452f126890aSEmmanuel Vadot regulator-boot-on; 1453f126890aSEmmanuel Vadot ti,roof-floor = <1>; 1454f126890aSEmmanuel Vadot ti,mode-sleep = <3>; 1455f126890aSEmmanuel Vadot }; 1456f126890aSEmmanuel Vadot 1457*b2d2a78aSEmmanuel Vadot vdd_core: smps45 { 1458*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_core"; 1459f126890aSEmmanuel Vadot regulator-min-microvolt = <900000>; 1460f126890aSEmmanuel Vadot regulator-max-microvolt = <1400000>; 1461f126890aSEmmanuel Vadot regulator-always-on; 1462f126890aSEmmanuel Vadot regulator-boot-on; 1463f126890aSEmmanuel Vadot ti,roof-floor = <3>; 1464f126890aSEmmanuel Vadot }; 1465f126890aSEmmanuel Vadot 1466*b2d2a78aSEmmanuel Vadot /* smps6 disabled */ 1467f126890aSEmmanuel Vadot 1468*b2d2a78aSEmmanuel Vadot vddio_ddr: smps7 { 1469*b2d2a78aSEmmanuel Vadot regulator-name = "vddio_ddr"; 1470f126890aSEmmanuel Vadot regulator-min-microvolt = <1350000>; 1471f126890aSEmmanuel Vadot regulator-max-microvolt = <1350000>; 1472f126890aSEmmanuel Vadot regulator-always-on; 1473f126890aSEmmanuel Vadot regulator-boot-on; 1474f126890aSEmmanuel Vadot }; 1475f126890aSEmmanuel Vadot 1476*b2d2a78aSEmmanuel Vadot vdd_1v8_vio: smps8 { 1477*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_1v8"; 1478f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 1479f126890aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 1480f126890aSEmmanuel Vadot regulator-always-on; 1481f126890aSEmmanuel Vadot regulator-boot-on; 1482f126890aSEmmanuel Vadot }; 1483f126890aSEmmanuel Vadot 1484*b2d2a78aSEmmanuel Vadot vcore_emmc: smps9 { 1485*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_emmc"; 1486f126890aSEmmanuel Vadot regulator-min-microvolt = <2900000>; 1487f126890aSEmmanuel Vadot regulator-max-microvolt = <2900000>; 1488*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1489f126890aSEmmanuel Vadot }; 1490f126890aSEmmanuel Vadot 1491*b2d2a78aSEmmanuel Vadot smps10_out1 { 1492*b2d2a78aSEmmanuel Vadot regulator-name = "vd_smps10_out1"; 1493f126890aSEmmanuel Vadot regulator-min-microvolt = <5000000>; 1494f126890aSEmmanuel Vadot regulator-max-microvolt = <5000000>; 1495f126890aSEmmanuel Vadot regulator-always-on; 1496f126890aSEmmanuel Vadot regulator-boot-on; 1497f126890aSEmmanuel Vadot }; 1498f126890aSEmmanuel Vadot 1499*b2d2a78aSEmmanuel Vadot vdd_smps10_out2: smps10_out2 { 1500*b2d2a78aSEmmanuel Vadot regulator-name = "vd_smps10_out2"; 1501f126890aSEmmanuel Vadot regulator-min-microvolt = <5000000>; 1502f126890aSEmmanuel Vadot regulator-max-microvolt = <5000000>; 1503f126890aSEmmanuel Vadot regulator-always-on; 1504f126890aSEmmanuel Vadot regulator-boot-on; 1505f126890aSEmmanuel Vadot }; 1506f126890aSEmmanuel Vadot 1507*b2d2a78aSEmmanuel Vadot avdd_hdmi_pll: ldo1 { 1508*b2d2a78aSEmmanuel Vadot regulator-name = "avdd_hdmi_pll"; 1509f126890aSEmmanuel Vadot regulator-min-microvolt = <1050000>; 1510f126890aSEmmanuel Vadot regulator-max-microvolt = <1050000>; 1511f126890aSEmmanuel Vadot regulator-always-on; 1512*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1513f126890aSEmmanuel Vadot ti,roof-floor = <3>; 1514f126890aSEmmanuel Vadot }; 1515f126890aSEmmanuel Vadot 1516*b2d2a78aSEmmanuel Vadot avdd_dsi_csi: ldo2 { 1517*b2d2a78aSEmmanuel Vadot regulator-name = "avdd_dsi_csi"; 1518f126890aSEmmanuel Vadot regulator-min-microvolt = <1200000>; 1519f126890aSEmmanuel Vadot regulator-max-microvolt = <1200000>; 1520f126890aSEmmanuel Vadot regulator-boot-on; 1521f126890aSEmmanuel Vadot }; 1522f126890aSEmmanuel Vadot 1523f126890aSEmmanuel Vadot ldo3 { 1524*b2d2a78aSEmmanuel Vadot regulator-name = "vpp_fuse"; 1525f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 1526f126890aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 1527f126890aSEmmanuel Vadot }; 1528f126890aSEmmanuel Vadot 1529*b2d2a78aSEmmanuel Vadot vdd_1v2_cam: ldo4 { 1530*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_1v2_cam"; 1531f126890aSEmmanuel Vadot regulator-min-microvolt = <1200000>; 1532f126890aSEmmanuel Vadot regulator-max-microvolt = <1200000>; 1533f126890aSEmmanuel Vadot }; 1534f126890aSEmmanuel Vadot 1535*b2d2a78aSEmmanuel Vadot avdd_2v8_cam: ldo5 { 1536*b2d2a78aSEmmanuel Vadot regulator-name = "avdd_cam2"; 1537f126890aSEmmanuel Vadot regulator-min-microvolt = <2800000>; 1538f126890aSEmmanuel Vadot regulator-max-microvolt = <2800000>; 1539f126890aSEmmanuel Vadot }; 1540f126890aSEmmanuel Vadot 1541*b2d2a78aSEmmanuel Vadot vdd_2v85_sen: ldo6 { 1542*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_dev"; 1543f126890aSEmmanuel Vadot regulator-min-microvolt = <2850000>; 1544f126890aSEmmanuel Vadot regulator-max-microvolt = <2850000>; 1545f126890aSEmmanuel Vadot }; 1546f126890aSEmmanuel Vadot 1547*b2d2a78aSEmmanuel Vadot avdd_2v8_af: ldo7 { 1548*b2d2a78aSEmmanuel Vadot regulator-name = "avdd_2v8_cam"; 1549f126890aSEmmanuel Vadot regulator-min-microvolt = <2800000>; 1550f126890aSEmmanuel Vadot regulator-max-microvolt = <2800000>; 1551f126890aSEmmanuel Vadot }; 1552f126890aSEmmanuel Vadot 1553*b2d2a78aSEmmanuel Vadot ldo8 { 1554*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_rtc"; 1555f126890aSEmmanuel Vadot regulator-min-microvolt = <950000>; 1556f126890aSEmmanuel Vadot regulator-max-microvolt = <950000>; 1557f126890aSEmmanuel Vadot regulator-always-on; 1558f126890aSEmmanuel Vadot regulator-boot-on; 1559f126890aSEmmanuel Vadot ti,enable-ldo8-tracking; 1560f126890aSEmmanuel Vadot }; 1561f126890aSEmmanuel Vadot 1562*b2d2a78aSEmmanuel Vadot vddio_usd: ldo9 { 1563*b2d2a78aSEmmanuel Vadot regulator-name = "vddio_usd"; 1564*b2d2a78aSEmmanuel Vadot /* min voltage of 1.8v is not stable */ 1565*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <2900000>; 1566f126890aSEmmanuel Vadot regulator-max-microvolt = <2900000>; 1567f126890aSEmmanuel Vadot }; 1568f126890aSEmmanuel Vadot 1569*b2d2a78aSEmmanuel Vadot avdd_hdmi: ldoln { 1570*b2d2a78aSEmmanuel Vadot regulator-name = "avdd_hdmi"; 1571f126890aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1572f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1573*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1574f126890aSEmmanuel Vadot }; 1575f126890aSEmmanuel Vadot 1576*b2d2a78aSEmmanuel Vadot avdd_usb: ldousb { 1577*b2d2a78aSEmmanuel Vadot regulator-name = "avdd_usb"; 1578f126890aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1579f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1580f126890aSEmmanuel Vadot regulator-boot-on; 1581f126890aSEmmanuel Vadot }; 1582f126890aSEmmanuel Vadot }; 1583f126890aSEmmanuel Vadot }; 1584f126890aSEmmanuel Vadot 1585f126890aSEmmanuel Vadot rtc { 1586f126890aSEmmanuel Vadot compatible = "ti,palmas-rtc"; 1587f126890aSEmmanuel Vadot interrupt-parent = <&palmas>; 1588*b2d2a78aSEmmanuel Vadot interrupts = <8 IRQ_TYPE_NONE>; 1589f126890aSEmmanuel Vadot }; 1590f126890aSEmmanuel Vadot }; 1591f126890aSEmmanuel Vadot }; 1592f126890aSEmmanuel Vadot 1593*b2d2a78aSEmmanuel Vadot pmc@7000e400 { 1594*b2d2a78aSEmmanuel Vadot status = "okay"; 1595*b2d2a78aSEmmanuel Vadot nvidia,suspend-mode = <2>; 1596*b2d2a78aSEmmanuel Vadot nvidia,cpu-pwr-good-time = <300>; 1597*b2d2a78aSEmmanuel Vadot nvidia,cpu-pwr-off-time = <300>; 1598*b2d2a78aSEmmanuel Vadot nvidia,core-pwr-good-time = <641 3845>; 1599*b2d2a78aSEmmanuel Vadot nvidia,core-pwr-off-time = <2000>; 1600*b2d2a78aSEmmanuel Vadot nvidia,core-power-req-active-high; 1601*b2d2a78aSEmmanuel Vadot nvidia,sys-clock-req-active-high; 1602*b2d2a78aSEmmanuel Vadot 1603*b2d2a78aSEmmanuel Vadot /* Clear DEV_ON bit in DEV_CTRL register of TPS65913 PMIC */ 1604*b2d2a78aSEmmanuel Vadot i2c-thermtrip { 1605*b2d2a78aSEmmanuel Vadot nvidia,i2c-controller-id = <4>; 1606*b2d2a78aSEmmanuel Vadot nvidia,bus-addr = <0x58>; 1607*b2d2a78aSEmmanuel Vadot nvidia,reg-addr = <0xA0>; 1608*b2d2a78aSEmmanuel Vadot nvidia,reg-data = <0x00>; 1609*b2d2a78aSEmmanuel Vadot }; 1610*b2d2a78aSEmmanuel Vadot }; 1611*b2d2a78aSEmmanuel Vadot 1612f126890aSEmmanuel Vadot ahub@70080000 { 1613*b2d2a78aSEmmanuel Vadot /* HIFI CODEC (i2s1) */ 1614*b2d2a78aSEmmanuel Vadot i2s@70080400 { 1615*b2d2a78aSEmmanuel Vadot status = "okay"; 1616*b2d2a78aSEmmanuel Vadot }; 1617*b2d2a78aSEmmanuel Vadot 1618*b2d2a78aSEmmanuel Vadot /* BT SCO (i2s3) */ 1619*b2d2a78aSEmmanuel Vadot i2s@70080600 { 1620f126890aSEmmanuel Vadot status = "okay"; 1621f126890aSEmmanuel Vadot }; 1622f126890aSEmmanuel Vadot }; 1623f126890aSEmmanuel Vadot 1624*b2d2a78aSEmmanuel Vadot brcm_wifi_pwrseq: pwrseq-wifi { 1625*b2d2a78aSEmmanuel Vadot compatible = "mmc-pwrseq-simple"; 1626*b2d2a78aSEmmanuel Vadot 1627*b2d2a78aSEmmanuel Vadot clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 1628*b2d2a78aSEmmanuel Vadot clock-names = "ext_clock"; 1629*b2d2a78aSEmmanuel Vadot 1630*b2d2a78aSEmmanuel Vadot reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; 1631*b2d2a78aSEmmanuel Vadot post-power-on-delay-ms = <300>; 1632*b2d2a78aSEmmanuel Vadot power-off-delay-us = <300>; 1633*b2d2a78aSEmmanuel Vadot }; 1634*b2d2a78aSEmmanuel Vadot 1635f126890aSEmmanuel Vadot /* WiFi */ 1636*b2d2a78aSEmmanuel Vadot mmc@78000000 { 1637*b2d2a78aSEmmanuel Vadot status = "okay"; 1638*b2d2a78aSEmmanuel Vadot 1639*b2d2a78aSEmmanuel Vadot #address-cells = <1>; 1640*b2d2a78aSEmmanuel Vadot #size-cells = <0>; 1641*b2d2a78aSEmmanuel Vadot 1642*b2d2a78aSEmmanuel Vadot assigned-clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 1643*b2d2a78aSEmmanuel Vadot assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_P>; 1644*b2d2a78aSEmmanuel Vadot assigned-clock-rates = <82000000>; 1645*b2d2a78aSEmmanuel Vadot 1646*b2d2a78aSEmmanuel Vadot max-frequency = <82000000>; 1647*b2d2a78aSEmmanuel Vadot keep-power-in-suspend; 1648*b2d2a78aSEmmanuel Vadot bus-width = <4>; 1649*b2d2a78aSEmmanuel Vadot non-removable; 1650*b2d2a78aSEmmanuel Vadot 1651*b2d2a78aSEmmanuel Vadot sd-uhs-ddr50; 1652*b2d2a78aSEmmanuel Vadot mmc-ddr-1_8v; 1653*b2d2a78aSEmmanuel Vadot 1654*b2d2a78aSEmmanuel Vadot power-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_HIGH>; 1655*b2d2a78aSEmmanuel Vadot 1656*b2d2a78aSEmmanuel Vadot nvidia,default-tap = <0x2>; 1657*b2d2a78aSEmmanuel Vadot nvidia,default-trim = <0x2>; 1658*b2d2a78aSEmmanuel Vadot 1659*b2d2a78aSEmmanuel Vadot mmc-pwrseq = <&brcm_wifi_pwrseq>; 1660*b2d2a78aSEmmanuel Vadot vmmc-supply = <&vdd_3v3_com>; 1661*b2d2a78aSEmmanuel Vadot vqmmc-supply = <&vdd_1v8_vio>; 1662*b2d2a78aSEmmanuel Vadot 1663*b2d2a78aSEmmanuel Vadot wifi@1 { 1664*b2d2a78aSEmmanuel Vadot compatible = "brcm,bcm4329-fmac"; 1665*b2d2a78aSEmmanuel Vadot reg = <1>; 1666*b2d2a78aSEmmanuel Vadot 1667*b2d2a78aSEmmanuel Vadot interrupt-parent = <&gpio>; 1668*b2d2a78aSEmmanuel Vadot interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_LEVEL_HIGH>; 1669*b2d2a78aSEmmanuel Vadot interrupt-names = "host-wake"; 1670*b2d2a78aSEmmanuel Vadot }; 1671f126890aSEmmanuel Vadot }; 1672f126890aSEmmanuel Vadot 1673f126890aSEmmanuel Vadot /* MicroSD card */ 1674f126890aSEmmanuel Vadot mmc@78000400 { 1675f126890aSEmmanuel Vadot status = "okay"; 1676f126890aSEmmanuel Vadot 1677f126890aSEmmanuel Vadot bus-width = <4>; 1678f126890aSEmmanuel Vadot cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 1679f126890aSEmmanuel Vadot 1680f126890aSEmmanuel Vadot nvidia,default-tap = <0x3>; 1681f126890aSEmmanuel Vadot nvidia,default-trim = <0x3>; 1682f126890aSEmmanuel Vadot 1683*b2d2a78aSEmmanuel Vadot vmmc-supply = <&vdd_2v9_usd>; 1684*b2d2a78aSEmmanuel Vadot vqmmc-supply = <&vddio_usd>; 1685f126890aSEmmanuel Vadot }; 1686f126890aSEmmanuel Vadot 1687f126890aSEmmanuel Vadot /* eMMC */ 1688*b2d2a78aSEmmanuel Vadot mmc@78000600 { 1689*b2d2a78aSEmmanuel Vadot status = "okay"; 1690*b2d2a78aSEmmanuel Vadot bus-width = <8>; 1691*b2d2a78aSEmmanuel Vadot 1692*b2d2a78aSEmmanuel Vadot non-removable; 1693*b2d2a78aSEmmanuel Vadot mmc-ddr-1_8v; 1694*b2d2a78aSEmmanuel Vadot 1695*b2d2a78aSEmmanuel Vadot vmmc-supply = <&vcore_emmc>; 1696*b2d2a78aSEmmanuel Vadot vqmmc-supply = <&vdd_1v8_vio>; 1697f126890aSEmmanuel Vadot }; 1698f126890aSEmmanuel Vadot 1699*b2d2a78aSEmmanuel Vadot /* Peripheral USB via ASUS connector */ 1700f126890aSEmmanuel Vadot usb@7d000000 { 1701f126890aSEmmanuel Vadot compatible = "nvidia,tegra114-udc"; 1702f126890aSEmmanuel Vadot status = "okay"; 1703f126890aSEmmanuel Vadot dr_mode = "peripheral"; 1704f126890aSEmmanuel Vadot }; 1705f126890aSEmmanuel Vadot 1706f126890aSEmmanuel Vadot usb-phy@7d000000 { 1707f126890aSEmmanuel Vadot status = "okay"; 1708*b2d2a78aSEmmanuel Vadot dr_mode = "peripheral"; 1709*b2d2a78aSEmmanuel Vadot vbus-supply = <&avdd_usb>; 1710f126890aSEmmanuel Vadot }; 1711f126890aSEmmanuel Vadot 1712*b2d2a78aSEmmanuel Vadot /* Host USB via dock */ 1713f126890aSEmmanuel Vadot usb@7d008000 { 1714f126890aSEmmanuel Vadot status = "okay"; 1715f126890aSEmmanuel Vadot }; 1716f126890aSEmmanuel Vadot 1717f126890aSEmmanuel Vadot usb-phy@7d008000 { 1718f126890aSEmmanuel Vadot status = "okay"; 1719f126890aSEmmanuel Vadot vbus-supply = <&vdd_5v0_sys>; 1720f126890aSEmmanuel Vadot }; 1721f126890aSEmmanuel Vadot 1722f126890aSEmmanuel Vadot backlight: backlight { 1723f126890aSEmmanuel Vadot compatible = "pwm-backlight"; 1724f126890aSEmmanuel Vadot 1725*b2d2a78aSEmmanuel Vadot power-supply = <&vdd_3v7_bl>; 1726f126890aSEmmanuel Vadot pwms = <&pwm 1 1000000>; 1727f126890aSEmmanuel Vadot 1728f126890aSEmmanuel Vadot brightness-levels = <1 255>; 1729f126890aSEmmanuel Vadot num-interpolated-steps = <254>; 1730f126890aSEmmanuel Vadot default-brightness-level = <224>; 1731f126890aSEmmanuel Vadot }; 1732f126890aSEmmanuel Vadot 1733f126890aSEmmanuel Vadot /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 1734f126890aSEmmanuel Vadot clk32k_in: clock-32k { 1735f126890aSEmmanuel Vadot compatible = "fixed-clock"; 1736f126890aSEmmanuel Vadot #clock-cells = <0>; 1737f126890aSEmmanuel Vadot clock-frequency = <32768>; 1738f126890aSEmmanuel Vadot clock-output-names = "pmic-oscillator"; 1739f126890aSEmmanuel Vadot }; 1740f126890aSEmmanuel Vadot 1741*b2d2a78aSEmmanuel Vadot connector { 1742*b2d2a78aSEmmanuel Vadot compatible = "hdmi-connector"; 1743*b2d2a78aSEmmanuel Vadot type = "d"; 1744*b2d2a78aSEmmanuel Vadot 1745*b2d2a78aSEmmanuel Vadot hpd-gpios = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 1746*b2d2a78aSEmmanuel Vadot ddc-i2c-bus = <&hdmi_ddc>; 1747*b2d2a78aSEmmanuel Vadot 1748*b2d2a78aSEmmanuel Vadot port { 1749*b2d2a78aSEmmanuel Vadot connector_in: endpoint { 1750*b2d2a78aSEmmanuel Vadot remote-endpoint = <&hdmi_out>; 1751*b2d2a78aSEmmanuel Vadot }; 1752*b2d2a78aSEmmanuel Vadot }; 1753*b2d2a78aSEmmanuel Vadot }; 1754*b2d2a78aSEmmanuel Vadot 1755*b2d2a78aSEmmanuel Vadot extcon-keys { 1756f126890aSEmmanuel Vadot compatible = "gpio-keys"; 1757f126890aSEmmanuel Vadot 1758f126890aSEmmanuel Vadot switch-hall-sensor { 1759f126890aSEmmanuel Vadot label = "Hall Effect Sensor"; 1760f126890aSEmmanuel Vadot gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; 1761f126890aSEmmanuel Vadot linux,input-type = <EV_SW>; 1762f126890aSEmmanuel Vadot linux,code = <SW_LID>; 1763f126890aSEmmanuel Vadot linux,can-disable; 1764f126890aSEmmanuel Vadot wakeup-source; 1765f126890aSEmmanuel Vadot }; 1766*b2d2a78aSEmmanuel Vadot 1767*b2d2a78aSEmmanuel Vadot switch-lineout-detect { 1768*b2d2a78aSEmmanuel Vadot label = "Audio dock line-out detect"; 1769*b2d2a78aSEmmanuel Vadot gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; 1770*b2d2a78aSEmmanuel Vadot linux,input-type = <EV_SW>; 1771*b2d2a78aSEmmanuel Vadot linux,code = <SW_LINEOUT_INSERT>; 1772*b2d2a78aSEmmanuel Vadot debounce-interval = <10>; 1773*b2d2a78aSEmmanuel Vadot }; 1774f126890aSEmmanuel Vadot }; 1775f126890aSEmmanuel Vadot 1776f126890aSEmmanuel Vadot gpio-keys { 1777f126890aSEmmanuel Vadot compatible = "gpio-keys"; 1778f126890aSEmmanuel Vadot 1779*b2d2a78aSEmmanuel Vadot key-power { 1780f126890aSEmmanuel Vadot label = "Power"; 1781f126890aSEmmanuel Vadot gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 1782f126890aSEmmanuel Vadot linux,code = <KEY_POWER>; 1783f126890aSEmmanuel Vadot debounce-interval = <10>; 1784f126890aSEmmanuel Vadot wakeup-source; 1785f126890aSEmmanuel Vadot }; 1786f126890aSEmmanuel Vadot 1787*b2d2a78aSEmmanuel Vadot key-volume-down { 1788f126890aSEmmanuel Vadot label = "Volume Down"; 1789f126890aSEmmanuel Vadot gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; 1790f126890aSEmmanuel Vadot linux,code = <KEY_VOLUMEDOWN>; 1791f126890aSEmmanuel Vadot debounce-interval = <10>; 1792f126890aSEmmanuel Vadot }; 1793f126890aSEmmanuel Vadot 1794*b2d2a78aSEmmanuel Vadot key-volume-up { 1795f126890aSEmmanuel Vadot label = "Volume Up"; 1796f126890aSEmmanuel Vadot gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; 1797f126890aSEmmanuel Vadot linux,code = <KEY_VOLUMEUP>; 1798f126890aSEmmanuel Vadot debounce-interval = <10>; 1799f126890aSEmmanuel Vadot }; 1800f126890aSEmmanuel Vadot }; 1801f126890aSEmmanuel Vadot 1802f126890aSEmmanuel Vadot sound { 1803f126890aSEmmanuel Vadot compatible = "asus,tegra-audio-rt5639-tf701t", 1804f126890aSEmmanuel Vadot "nvidia,tegra-audio-rt5640"; 1805f126890aSEmmanuel Vadot nvidia,model = "Asus Transformer Pad TF701T RT5639"; 1806f126890aSEmmanuel Vadot 1807f126890aSEmmanuel Vadot nvidia,audio-routing = 1808f126890aSEmmanuel Vadot "Headphones", "HPOR", 1809f126890aSEmmanuel Vadot "Headphones", "HPOL", 1810f126890aSEmmanuel Vadot "Speakers", "SPORP", 1811f126890aSEmmanuel Vadot "Speakers", "SPORN", 1812f126890aSEmmanuel Vadot "Speakers", "SPOLP", 1813f126890aSEmmanuel Vadot "Speakers", "SPOLN", 1814*b2d2a78aSEmmanuel Vadot "IN1P", "Mic Jack", 1815*b2d2a78aSEmmanuel Vadot "IN1N", "Mic Jack", 1816*b2d2a78aSEmmanuel Vadot "DMIC1", "Int Mic", 1817*b2d2a78aSEmmanuel Vadot "DMIC2", "Int Mic"; 1818f126890aSEmmanuel Vadot 1819*b2d2a78aSEmmanuel Vadot nvidia,i2s-controller = <&tegra_i2s1>; 1820f126890aSEmmanuel Vadot nvidia,audio-codec = <&rt5639>; 1821f126890aSEmmanuel Vadot 1822f126890aSEmmanuel Vadot nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>; 1823*b2d2a78aSEmmanuel Vadot nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>; 1824f126890aSEmmanuel Vadot 1825f126890aSEmmanuel Vadot clocks = <&tegra_car TEGRA114_CLK_PLL_A>, 1826f126890aSEmmanuel Vadot <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, 1827f126890aSEmmanuel Vadot <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1828f126890aSEmmanuel Vadot clock-names = "pll_a", "pll_a_out0", "mclk"; 1829f126890aSEmmanuel Vadot 1830f126890aSEmmanuel Vadot assigned-clocks = <&tegra_car TEGRA114_CLK_EXTERN1>, 1831f126890aSEmmanuel Vadot <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 1832f126890aSEmmanuel Vadot 1833f126890aSEmmanuel Vadot assigned-clock-parents = <&tegra_car TEGRA114_CLK_PLL_A_OUT0>, 1834f126890aSEmmanuel Vadot <&tegra_car TEGRA114_CLK_EXTERN1>; 1835f126890aSEmmanuel Vadot }; 1836f126890aSEmmanuel Vadot 1837f126890aSEmmanuel Vadot vdd_5v0_sys: regulator-5v0-sys { 1838f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1839*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_5v0_sys"; 1840f126890aSEmmanuel Vadot regulator-min-microvolt = <5000000>; 1841f126890aSEmmanuel Vadot regulator-max-microvolt = <5000000>; 1842f126890aSEmmanuel Vadot regulator-always-on; 1843f126890aSEmmanuel Vadot regulator-boot-on; 1844f126890aSEmmanuel Vadot }; 1845f126890aSEmmanuel Vadot 1846f126890aSEmmanuel Vadot vdd_3v3_sys: regulator-3v3-sys { 1847f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1848*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_3v3_sys"; 1849f126890aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1850f126890aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1851f126890aSEmmanuel Vadot regulator-always-on; 1852f126890aSEmmanuel Vadot regulator-boot-on; 1853f126890aSEmmanuel Vadot }; 1854f126890aSEmmanuel Vadot 1855*b2d2a78aSEmmanuel Vadot dvdd_1v8_lcd: regulator-vdd-lcd { 1856f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1857*b2d2a78aSEmmanuel Vadot regulator-name = "dvdd_1v8_lcd"; 1858f126890aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 1859f126890aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 1860f126890aSEmmanuel Vadot regulator-boot-on; 1861*b2d2a78aSEmmanuel Vadot gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; 1862*b2d2a78aSEmmanuel Vadot enable-active-high; 1863*b2d2a78aSEmmanuel Vadot vin-supply = <&vdd_1v8_vio>; 1864f126890aSEmmanuel Vadot }; 1865f126890aSEmmanuel Vadot 1866*b2d2a78aSEmmanuel Vadot vdd_3v7_bl: regulator-bl-en { 1867*b2d2a78aSEmmanuel Vadot compatible = "regulator-fixed"; 1868*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_3v7_bl"; 1869*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <3700000>; 1870*b2d2a78aSEmmanuel Vadot regulator-max-microvolt = <3700000>; 1871*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1872*b2d2a78aSEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; 1873*b2d2a78aSEmmanuel Vadot enable-active-high; 1874*b2d2a78aSEmmanuel Vadot vin-supply = <&vdd_5v0_sys>; 1875*b2d2a78aSEmmanuel Vadot }; 1876*b2d2a78aSEmmanuel Vadot 1877*b2d2a78aSEmmanuel Vadot hdmi_5v0_sys: regulator-hdmi { 1878*b2d2a78aSEmmanuel Vadot compatible = "regulator-fixed"; 1879*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_5v0_hdmi"; 1880*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <5000000>; 1881*b2d2a78aSEmmanuel Vadot regulator-max-microvolt = <5000000>; 1882*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1883*b2d2a78aSEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; 1884*b2d2a78aSEmmanuel Vadot enable-active-high; 1885*b2d2a78aSEmmanuel Vadot vin-supply = <&vdd_smps10_out2>; 1886*b2d2a78aSEmmanuel Vadot }; 1887*b2d2a78aSEmmanuel Vadot 1888*b2d2a78aSEmmanuel Vadot vdd_2v9_usd: regulator-vdd-usd { 1889f126890aSEmmanuel Vadot compatible = "regulator-fixed"; 1890f126890aSEmmanuel Vadot regulator-name = "vdd_sd_slot"; 1891f126890aSEmmanuel Vadot regulator-min-microvolt = <2900000>; 1892f126890aSEmmanuel Vadot regulator-max-microvolt = <2900000>; 1893*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1894f126890aSEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 1895*b2d2a78aSEmmanuel Vadot enable-active-high; 1896*b2d2a78aSEmmanuel Vadot vin-supply = <&vcore_emmc>; 1897*b2d2a78aSEmmanuel Vadot }; 1898f126890aSEmmanuel Vadot 1899*b2d2a78aSEmmanuel Vadot vdd_1v8_cam: regulator-cam-vio { 1900*b2d2a78aSEmmanuel Vadot compatible = "regulator-fixed"; 1901*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_1v8_cam"; 1902*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 1903*b2d2a78aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 1904*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1905*b2d2a78aSEmmanuel Vadot gpio = <&palmas_gpio 6 GPIO_ACTIVE_HIGH>; 1906*b2d2a78aSEmmanuel Vadot enable-active-high; 1907*b2d2a78aSEmmanuel Vadot vin-supply = <&vdd_1v8_vio>; 1908*b2d2a78aSEmmanuel Vadot }; 1909*b2d2a78aSEmmanuel Vadot 1910*b2d2a78aSEmmanuel Vadot vdd_1v2_xusb: regulator-xusb-vio { 1911*b2d2a78aSEmmanuel Vadot compatible = "regulator-fixed"; 1912*b2d2a78aSEmmanuel Vadot regulator-name = "avddio_1v2_xusb"; 1913*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <1200000>; 1914*b2d2a78aSEmmanuel Vadot regulator-max-microvolt = <1200000>; 1915*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1916*b2d2a78aSEmmanuel Vadot gpio = <&palmas_gpio 3 GPIO_ACTIVE_HIGH>; 1917*b2d2a78aSEmmanuel Vadot enable-active-high; 1918*b2d2a78aSEmmanuel Vadot }; 1919*b2d2a78aSEmmanuel Vadot 1920*b2d2a78aSEmmanuel Vadot vdd_3v3_xusb: regulator-xusb-vdd { 1921*b2d2a78aSEmmanuel Vadot compatible = "regulator-fixed"; 1922*b2d2a78aSEmmanuel Vadot regulator-name = "hvdd_3v3_xusb"; 1923*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1924*b2d2a78aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1925*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1926*b2d2a78aSEmmanuel Vadot gpio = <&palmas_gpio 1 GPIO_ACTIVE_HIGH>; 1927*b2d2a78aSEmmanuel Vadot enable-active-high; 1928*b2d2a78aSEmmanuel Vadot }; 1929*b2d2a78aSEmmanuel Vadot 1930*b2d2a78aSEmmanuel Vadot vdd_3v3_com: regulator-com { 1931*b2d2a78aSEmmanuel Vadot compatible = "regulator-fixed"; 1932*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_3v3_com"; 1933*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1934*b2d2a78aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1935*b2d2a78aSEmmanuel Vadot regulator-always-on; 1936*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1937*b2d2a78aSEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 1938*b2d2a78aSEmmanuel Vadot enable-active-high; 1939*b2d2a78aSEmmanuel Vadot vin-supply = <&vdd_3v3_sys>; 1940*b2d2a78aSEmmanuel Vadot }; 1941*b2d2a78aSEmmanuel Vadot 1942*b2d2a78aSEmmanuel Vadot vdd_3v3_touch: regulator-touch-pwr { 1943*b2d2a78aSEmmanuel Vadot compatible = "regulator-fixed"; 1944*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_3v3_touch"; 1945*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <3300000>; 1946*b2d2a78aSEmmanuel Vadot regulator-max-microvolt = <3300000>; 1947*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1948*b2d2a78aSEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; 1949*b2d2a78aSEmmanuel Vadot enable-active-high; 1950*b2d2a78aSEmmanuel Vadot vin-supply = <&vdd_3v3_sys>; 1951*b2d2a78aSEmmanuel Vadot }; 1952*b2d2a78aSEmmanuel Vadot 1953*b2d2a78aSEmmanuel Vadot vdd_1v8_touch: regulator-touch-vio { 1954*b2d2a78aSEmmanuel Vadot compatible = "regulator-fixed"; 1955*b2d2a78aSEmmanuel Vadot regulator-name = "vdd_1v8_touch"; 1956*b2d2a78aSEmmanuel Vadot regulator-min-microvolt = <1800000>; 1957*b2d2a78aSEmmanuel Vadot regulator-max-microvolt = <1800000>; 1958*b2d2a78aSEmmanuel Vadot regulator-boot-on; 1959*b2d2a78aSEmmanuel Vadot gpio = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; 1960*b2d2a78aSEmmanuel Vadot enable-active-high; 1961*b2d2a78aSEmmanuel Vadot vin-supply = <&vdd_3v3_sys>; 1962f126890aSEmmanuel Vadot }; 1963f126890aSEmmanuel Vadot}; 1964