1*f126890aSEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2*f126890aSEmmanuel Vadot// Copyright (c) 2020 Nuvoton Technology 3*f126890aSEmmanuel Vadot 4*f126890aSEmmanuel Vadot#include "nuvoton-common-npcm7xx.dtsi" 5*f126890aSEmmanuel Vadot 6*f126890aSEmmanuel Vadot/ { 7*f126890aSEmmanuel Vadot #address-cells = <1>; 8*f126890aSEmmanuel Vadot #size-cells = <1>; 9*f126890aSEmmanuel Vadot interrupt-parent = <&gic>; 10*f126890aSEmmanuel Vadot 11*f126890aSEmmanuel Vadot cpus { 12*f126890aSEmmanuel Vadot #address-cells = <1>; 13*f126890aSEmmanuel Vadot #size-cells = <0>; 14*f126890aSEmmanuel Vadot enable-method = "nuvoton,npcm750-smp"; 15*f126890aSEmmanuel Vadot 16*f126890aSEmmanuel Vadot cpu@0 { 17*f126890aSEmmanuel Vadot device_type = "cpu"; 18*f126890aSEmmanuel Vadot compatible = "arm,cortex-a9"; 19*f126890aSEmmanuel Vadot clocks = <&clk NPCM7XX_CLK_CPU>; 20*f126890aSEmmanuel Vadot clock-names = "clk_cpu"; 21*f126890aSEmmanuel Vadot reg = <0>; 22*f126890aSEmmanuel Vadot next-level-cache = <&l2>; 23*f126890aSEmmanuel Vadot }; 24*f126890aSEmmanuel Vadot 25*f126890aSEmmanuel Vadot cpu@1 { 26*f126890aSEmmanuel Vadot device_type = "cpu"; 27*f126890aSEmmanuel Vadot compatible = "arm,cortex-a9"; 28*f126890aSEmmanuel Vadot clocks = <&clk NPCM7XX_CLK_CPU>; 29*f126890aSEmmanuel Vadot clock-names = "clk_cpu"; 30*f126890aSEmmanuel Vadot reg = <1>; 31*f126890aSEmmanuel Vadot next-level-cache = <&l2>; 32*f126890aSEmmanuel Vadot }; 33*f126890aSEmmanuel Vadot }; 34*f126890aSEmmanuel Vadot 35*f126890aSEmmanuel Vadot soc { 36*f126890aSEmmanuel Vadot timer@3fe600 { 37*f126890aSEmmanuel Vadot compatible = "arm,cortex-a9-twd-timer"; 38*f126890aSEmmanuel Vadot reg = <0x3fe600 0x20>; 39*f126890aSEmmanuel Vadot interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 40*f126890aSEmmanuel Vadot IRQ_TYPE_LEVEL_HIGH)>; 41*f126890aSEmmanuel Vadot clocks = <&clk NPCM7XX_CLK_AHB>; 42*f126890aSEmmanuel Vadot }; 43*f126890aSEmmanuel Vadot }; 44*f126890aSEmmanuel Vadot}; 45