1*f126890aSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*f126890aSEmmanuel Vadot #define PINMUX_PIN(no, func, ioset) \ 3*f126890aSEmmanuel Vadot (((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) 4*f126890aSEmmanuel Vadot 5*f126890aSEmmanuel Vadot #define PIN_PA0 0 6*f126890aSEmmanuel Vadot #define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) 7*f126890aSEmmanuel Vadot #define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) 8*f126890aSEmmanuel Vadot #define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) 9*f126890aSEmmanuel Vadot #define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) 10*f126890aSEmmanuel Vadot #define PIN_PA1 1 11*f126890aSEmmanuel Vadot #define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) 12*f126890aSEmmanuel Vadot #define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) 13*f126890aSEmmanuel Vadot #define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) 14*f126890aSEmmanuel Vadot #define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) 15*f126890aSEmmanuel Vadot #define PIN_PA2 2 16*f126890aSEmmanuel Vadot #define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) 17*f126890aSEmmanuel Vadot #define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) 18*f126890aSEmmanuel Vadot #define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) 19*f126890aSEmmanuel Vadot #define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) 20*f126890aSEmmanuel Vadot #define PIN_PA3 3 21*f126890aSEmmanuel Vadot #define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) 22*f126890aSEmmanuel Vadot #define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) 23*f126890aSEmmanuel Vadot #define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) 24*f126890aSEmmanuel Vadot #define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) 25*f126890aSEmmanuel Vadot #define PIN_PA4 4 26*f126890aSEmmanuel Vadot #define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) 27*f126890aSEmmanuel Vadot #define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) 28*f126890aSEmmanuel Vadot #define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) 29*f126890aSEmmanuel Vadot #define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) 30*f126890aSEmmanuel Vadot #define PIN_PA5 5 31*f126890aSEmmanuel Vadot #define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) 32*f126890aSEmmanuel Vadot #define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) 33*f126890aSEmmanuel Vadot #define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) 34*f126890aSEmmanuel Vadot #define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) 35*f126890aSEmmanuel Vadot #define PIN_PA6 6 36*f126890aSEmmanuel Vadot #define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) 37*f126890aSEmmanuel Vadot #define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) 38*f126890aSEmmanuel Vadot #define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) 39*f126890aSEmmanuel Vadot #define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) 40*f126890aSEmmanuel Vadot #define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) 41*f126890aSEmmanuel Vadot #define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) 42*f126890aSEmmanuel Vadot #define PIN_PA7 7 43*f126890aSEmmanuel Vadot #define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) 44*f126890aSEmmanuel Vadot #define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) 45*f126890aSEmmanuel Vadot #define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) 46*f126890aSEmmanuel Vadot #define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) 47*f126890aSEmmanuel Vadot #define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) 48*f126890aSEmmanuel Vadot #define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) 49*f126890aSEmmanuel Vadot #define PIN_PA8 8 50*f126890aSEmmanuel Vadot #define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) 51*f126890aSEmmanuel Vadot #define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) 52*f126890aSEmmanuel Vadot #define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) 53*f126890aSEmmanuel Vadot #define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) 54*f126890aSEmmanuel Vadot #define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) 55*f126890aSEmmanuel Vadot #define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) 56*f126890aSEmmanuel Vadot #define PIN_PA9 9 57*f126890aSEmmanuel Vadot #define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) 58*f126890aSEmmanuel Vadot #define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) 59*f126890aSEmmanuel Vadot #define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) 60*f126890aSEmmanuel Vadot #define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) 61*f126890aSEmmanuel Vadot #define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) 62*f126890aSEmmanuel Vadot #define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) 63*f126890aSEmmanuel Vadot #define PIN_PA10 10 64*f126890aSEmmanuel Vadot #define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) 65*f126890aSEmmanuel Vadot #define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) 66*f126890aSEmmanuel Vadot #define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) 67*f126890aSEmmanuel Vadot #define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) 68*f126890aSEmmanuel Vadot #define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) 69*f126890aSEmmanuel Vadot #define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) 70*f126890aSEmmanuel Vadot #define PIN_PA11 11 71*f126890aSEmmanuel Vadot #define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) 72*f126890aSEmmanuel Vadot #define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) 73*f126890aSEmmanuel Vadot #define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) 74*f126890aSEmmanuel Vadot #define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) 75*f126890aSEmmanuel Vadot #define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) 76*f126890aSEmmanuel Vadot #define PIN_PA12 12 77*f126890aSEmmanuel Vadot #define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) 78*f126890aSEmmanuel Vadot #define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) 79*f126890aSEmmanuel Vadot #define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) 80*f126890aSEmmanuel Vadot #define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) 81*f126890aSEmmanuel Vadot #define PIN_PA13 13 82*f126890aSEmmanuel Vadot #define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) 83*f126890aSEmmanuel Vadot #define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) 84*f126890aSEmmanuel Vadot #define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) 85*f126890aSEmmanuel Vadot #define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) 86*f126890aSEmmanuel Vadot #define PIN_PA14 14 87*f126890aSEmmanuel Vadot #define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) 88*f126890aSEmmanuel Vadot #define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) 89*f126890aSEmmanuel Vadot #define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) 90*f126890aSEmmanuel Vadot #define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) 91*f126890aSEmmanuel Vadot #define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) 92*f126890aSEmmanuel Vadot #define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) 93*f126890aSEmmanuel Vadot #define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) 94*f126890aSEmmanuel Vadot #define PIN_PA15 15 95*f126890aSEmmanuel Vadot #define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) 96*f126890aSEmmanuel Vadot #define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) 97*f126890aSEmmanuel Vadot #define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) 98*f126890aSEmmanuel Vadot #define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) 99*f126890aSEmmanuel Vadot #define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) 100*f126890aSEmmanuel Vadot #define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) 101*f126890aSEmmanuel Vadot #define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) 102*f126890aSEmmanuel Vadot #define PIN_PA16 16 103*f126890aSEmmanuel Vadot #define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) 104*f126890aSEmmanuel Vadot #define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) 105*f126890aSEmmanuel Vadot #define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) 106*f126890aSEmmanuel Vadot #define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) 107*f126890aSEmmanuel Vadot #define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) 108*f126890aSEmmanuel Vadot #define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) 109*f126890aSEmmanuel Vadot #define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) 110*f126890aSEmmanuel Vadot #define PIN_PA17 17 111*f126890aSEmmanuel Vadot #define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) 112*f126890aSEmmanuel Vadot #define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) 113*f126890aSEmmanuel Vadot #define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) 114*f126890aSEmmanuel Vadot #define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) 115*f126890aSEmmanuel Vadot #define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) 116*f126890aSEmmanuel Vadot #define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) 117*f126890aSEmmanuel Vadot #define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) 118*f126890aSEmmanuel Vadot #define PIN_PA18 18 119*f126890aSEmmanuel Vadot #define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) 120*f126890aSEmmanuel Vadot #define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) 121*f126890aSEmmanuel Vadot #define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) 122*f126890aSEmmanuel Vadot #define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) 123*f126890aSEmmanuel Vadot #define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) 124*f126890aSEmmanuel Vadot #define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) 125*f126890aSEmmanuel Vadot #define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) 126*f126890aSEmmanuel Vadot #define PIN_PA19 19 127*f126890aSEmmanuel Vadot #define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) 128*f126890aSEmmanuel Vadot #define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) 129*f126890aSEmmanuel Vadot #define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) 130*f126890aSEmmanuel Vadot #define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) 131*f126890aSEmmanuel Vadot #define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) 132*f126890aSEmmanuel Vadot #define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) 133*f126890aSEmmanuel Vadot #define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) 134*f126890aSEmmanuel Vadot #define PIN_PA20 20 135*f126890aSEmmanuel Vadot #define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) 136*f126890aSEmmanuel Vadot #define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) 137*f126890aSEmmanuel Vadot #define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) 138*f126890aSEmmanuel Vadot #define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) 139*f126890aSEmmanuel Vadot #define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) 140*f126890aSEmmanuel Vadot #define PIN_PA21 21 141*f126890aSEmmanuel Vadot #define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) 142*f126890aSEmmanuel Vadot #define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) 143*f126890aSEmmanuel Vadot #define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) 144*f126890aSEmmanuel Vadot #define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) 145*f126890aSEmmanuel Vadot #define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) 146*f126890aSEmmanuel Vadot #define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) 147*f126890aSEmmanuel Vadot #define PIN_PA22 22 148*f126890aSEmmanuel Vadot #define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) 149*f126890aSEmmanuel Vadot #define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) 150*f126890aSEmmanuel Vadot #define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) 151*f126890aSEmmanuel Vadot #define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) 152*f126890aSEmmanuel Vadot #define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) 153*f126890aSEmmanuel Vadot #define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) 154*f126890aSEmmanuel Vadot #define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) 155*f126890aSEmmanuel Vadot #define PIN_PA23 23 156*f126890aSEmmanuel Vadot #define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) 157*f126890aSEmmanuel Vadot #define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) 158*f126890aSEmmanuel Vadot #define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) 159*f126890aSEmmanuel Vadot #define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) 160*f126890aSEmmanuel Vadot #define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) 161*f126890aSEmmanuel Vadot #define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) 162*f126890aSEmmanuel Vadot #define PIN_PA24 24 163*f126890aSEmmanuel Vadot #define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) 164*f126890aSEmmanuel Vadot #define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) 165*f126890aSEmmanuel Vadot #define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) 166*f126890aSEmmanuel Vadot #define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) 167*f126890aSEmmanuel Vadot #define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) 168*f126890aSEmmanuel Vadot #define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) 169*f126890aSEmmanuel Vadot #define PIN_PA25 25 170*f126890aSEmmanuel Vadot #define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) 171*f126890aSEmmanuel Vadot #define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) 172*f126890aSEmmanuel Vadot #define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) 173*f126890aSEmmanuel Vadot #define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) 174*f126890aSEmmanuel Vadot #define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) 175*f126890aSEmmanuel Vadot #define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) 176*f126890aSEmmanuel Vadot #define PIN_PA26 26 177*f126890aSEmmanuel Vadot #define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) 178*f126890aSEmmanuel Vadot #define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) 179*f126890aSEmmanuel Vadot #define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) 180*f126890aSEmmanuel Vadot #define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) 181*f126890aSEmmanuel Vadot #define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) 182*f126890aSEmmanuel Vadot #define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) 183*f126890aSEmmanuel Vadot #define PIN_PA27 27 184*f126890aSEmmanuel Vadot #define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) 185*f126890aSEmmanuel Vadot #define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) 186*f126890aSEmmanuel Vadot #define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) 187*f126890aSEmmanuel Vadot #define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) 188*f126890aSEmmanuel Vadot #define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) 189*f126890aSEmmanuel Vadot #define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) 190*f126890aSEmmanuel Vadot #define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) 191*f126890aSEmmanuel Vadot #define PIN_PA28 28 192*f126890aSEmmanuel Vadot #define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) 193*f126890aSEmmanuel Vadot #define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) 194*f126890aSEmmanuel Vadot #define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) 195*f126890aSEmmanuel Vadot #define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) 196*f126890aSEmmanuel Vadot #define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) 197*f126890aSEmmanuel Vadot #define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) 198*f126890aSEmmanuel Vadot #define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) 199*f126890aSEmmanuel Vadot #define PIN_PA29 29 200*f126890aSEmmanuel Vadot #define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) 201*f126890aSEmmanuel Vadot #define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) 202*f126890aSEmmanuel Vadot #define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) 203*f126890aSEmmanuel Vadot #define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) 204*f126890aSEmmanuel Vadot #define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) 205*f126890aSEmmanuel Vadot #define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) 206*f126890aSEmmanuel Vadot #define PIN_PA30 30 207*f126890aSEmmanuel Vadot #define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) 208*f126890aSEmmanuel Vadot #define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) 209*f126890aSEmmanuel Vadot #define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) 210*f126890aSEmmanuel Vadot #define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) 211*f126890aSEmmanuel Vadot #define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) 212*f126890aSEmmanuel Vadot #define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) 213*f126890aSEmmanuel Vadot #define PIN_PA31 31 214*f126890aSEmmanuel Vadot #define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) 215*f126890aSEmmanuel Vadot #define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) 216*f126890aSEmmanuel Vadot #define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) 217*f126890aSEmmanuel Vadot #define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) 218*f126890aSEmmanuel Vadot #define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) 219*f126890aSEmmanuel Vadot #define PIN_PB0 32 220*f126890aSEmmanuel Vadot #define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) 221*f126890aSEmmanuel Vadot #define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) 222*f126890aSEmmanuel Vadot #define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) 223*f126890aSEmmanuel Vadot #define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) 224*f126890aSEmmanuel Vadot #define PIN_PB1 33 225*f126890aSEmmanuel Vadot #define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) 226*f126890aSEmmanuel Vadot #define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) 227*f126890aSEmmanuel Vadot #define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) 228*f126890aSEmmanuel Vadot #define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) 229*f126890aSEmmanuel Vadot #define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) 230*f126890aSEmmanuel Vadot #define PIN_PB2 34 231*f126890aSEmmanuel Vadot #define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) 232*f126890aSEmmanuel Vadot #define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) 233*f126890aSEmmanuel Vadot #define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) 234*f126890aSEmmanuel Vadot #define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) 235*f126890aSEmmanuel Vadot #define PIN_PB3 35 236*f126890aSEmmanuel Vadot #define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) 237*f126890aSEmmanuel Vadot #define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) 238*f126890aSEmmanuel Vadot #define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) 239*f126890aSEmmanuel Vadot #define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) 240*f126890aSEmmanuel Vadot #define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) 241*f126890aSEmmanuel Vadot #define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) 242*f126890aSEmmanuel Vadot #define PIN_PB4 36 243*f126890aSEmmanuel Vadot #define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) 244*f126890aSEmmanuel Vadot #define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) 245*f126890aSEmmanuel Vadot #define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) 246*f126890aSEmmanuel Vadot #define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) 247*f126890aSEmmanuel Vadot #define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) 248*f126890aSEmmanuel Vadot #define PIN_PB5 37 249*f126890aSEmmanuel Vadot #define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) 250*f126890aSEmmanuel Vadot #define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) 251*f126890aSEmmanuel Vadot #define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) 252*f126890aSEmmanuel Vadot #define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) 253*f126890aSEmmanuel Vadot #define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) 254*f126890aSEmmanuel Vadot #define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) 255*f126890aSEmmanuel Vadot #define PIN_PB6 38 256*f126890aSEmmanuel Vadot #define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) 257*f126890aSEmmanuel Vadot #define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) 258*f126890aSEmmanuel Vadot #define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) 259*f126890aSEmmanuel Vadot #define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) 260*f126890aSEmmanuel Vadot #define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) 261*f126890aSEmmanuel Vadot #define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) 262*f126890aSEmmanuel Vadot #define PIN_PB7 39 263*f126890aSEmmanuel Vadot #define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) 264*f126890aSEmmanuel Vadot #define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) 265*f126890aSEmmanuel Vadot #define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) 266*f126890aSEmmanuel Vadot #define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) 267*f126890aSEmmanuel Vadot #define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) 268*f126890aSEmmanuel Vadot #define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) 269*f126890aSEmmanuel Vadot #define PIN_PB8 40 270*f126890aSEmmanuel Vadot #define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) 271*f126890aSEmmanuel Vadot #define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) 272*f126890aSEmmanuel Vadot #define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) 273*f126890aSEmmanuel Vadot #define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) 274*f126890aSEmmanuel Vadot #define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) 275*f126890aSEmmanuel Vadot #define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) 276*f126890aSEmmanuel Vadot #define PIN_PB9 41 277*f126890aSEmmanuel Vadot #define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) 278*f126890aSEmmanuel Vadot #define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) 279*f126890aSEmmanuel Vadot #define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) 280*f126890aSEmmanuel Vadot #define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) 281*f126890aSEmmanuel Vadot #define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) 282*f126890aSEmmanuel Vadot #define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) 283*f126890aSEmmanuel Vadot #define PIN_PB10 42 284*f126890aSEmmanuel Vadot #define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) 285*f126890aSEmmanuel Vadot #define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) 286*f126890aSEmmanuel Vadot #define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) 287*f126890aSEmmanuel Vadot #define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) 288*f126890aSEmmanuel Vadot #define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) 289*f126890aSEmmanuel Vadot #define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) 290*f126890aSEmmanuel Vadot #define PIN_PB11 43 291*f126890aSEmmanuel Vadot #define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) 292*f126890aSEmmanuel Vadot #define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) 293*f126890aSEmmanuel Vadot #define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) 294*f126890aSEmmanuel Vadot #define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) 295*f126890aSEmmanuel Vadot #define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) 296*f126890aSEmmanuel Vadot #define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) 297*f126890aSEmmanuel Vadot #define PIN_PB12 44 298*f126890aSEmmanuel Vadot #define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) 299*f126890aSEmmanuel Vadot #define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) 300*f126890aSEmmanuel Vadot #define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) 301*f126890aSEmmanuel Vadot #define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) 302*f126890aSEmmanuel Vadot #define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) 303*f126890aSEmmanuel Vadot #define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) 304*f126890aSEmmanuel Vadot #define PIN_PB13 45 305*f126890aSEmmanuel Vadot #define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) 306*f126890aSEmmanuel Vadot #define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) 307*f126890aSEmmanuel Vadot #define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) 308*f126890aSEmmanuel Vadot #define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) 309*f126890aSEmmanuel Vadot #define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) 310*f126890aSEmmanuel Vadot #define PIN_PB14 46 311*f126890aSEmmanuel Vadot #define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) 312*f126890aSEmmanuel Vadot #define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) 313*f126890aSEmmanuel Vadot #define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) 314*f126890aSEmmanuel Vadot #define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) 315*f126890aSEmmanuel Vadot #define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) 316*f126890aSEmmanuel Vadot #define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) 317*f126890aSEmmanuel Vadot #define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) 318*f126890aSEmmanuel Vadot #define PIN_PB15 47 319*f126890aSEmmanuel Vadot #define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) 320*f126890aSEmmanuel Vadot #define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) 321*f126890aSEmmanuel Vadot #define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) 322*f126890aSEmmanuel Vadot #define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) 323*f126890aSEmmanuel Vadot #define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) 324*f126890aSEmmanuel Vadot #define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) 325*f126890aSEmmanuel Vadot #define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) 326*f126890aSEmmanuel Vadot #define PIN_PB16 48 327*f126890aSEmmanuel Vadot #define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) 328*f126890aSEmmanuel Vadot #define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) 329*f126890aSEmmanuel Vadot #define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) 330*f126890aSEmmanuel Vadot #define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) 331*f126890aSEmmanuel Vadot #define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) 332*f126890aSEmmanuel Vadot #define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) 333*f126890aSEmmanuel Vadot #define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) 334*f126890aSEmmanuel Vadot #define PIN_PB17 49 335*f126890aSEmmanuel Vadot #define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) 336*f126890aSEmmanuel Vadot #define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) 337*f126890aSEmmanuel Vadot #define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) 338*f126890aSEmmanuel Vadot #define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) 339*f126890aSEmmanuel Vadot #define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) 340*f126890aSEmmanuel Vadot #define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) 341*f126890aSEmmanuel Vadot #define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) 342*f126890aSEmmanuel Vadot #define PIN_PB18 50 343*f126890aSEmmanuel Vadot #define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) 344*f126890aSEmmanuel Vadot #define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) 345*f126890aSEmmanuel Vadot #define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) 346*f126890aSEmmanuel Vadot #define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) 347*f126890aSEmmanuel Vadot #define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) 348*f126890aSEmmanuel Vadot #define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) 349*f126890aSEmmanuel Vadot #define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) 350*f126890aSEmmanuel Vadot #define PIN_PB19 51 351*f126890aSEmmanuel Vadot #define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) 352*f126890aSEmmanuel Vadot #define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) 353*f126890aSEmmanuel Vadot #define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) 354*f126890aSEmmanuel Vadot #define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) 355*f126890aSEmmanuel Vadot #define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) 356*f126890aSEmmanuel Vadot #define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) 357*f126890aSEmmanuel Vadot #define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) 358*f126890aSEmmanuel Vadot #define PIN_PB20 52 359*f126890aSEmmanuel Vadot #define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) 360*f126890aSEmmanuel Vadot #define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) 361*f126890aSEmmanuel Vadot #define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) 362*f126890aSEmmanuel Vadot #define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) 363*f126890aSEmmanuel Vadot #define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) 364*f126890aSEmmanuel Vadot #define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) 365*f126890aSEmmanuel Vadot #define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) 366*f126890aSEmmanuel Vadot #define PIN_PB21 53 367*f126890aSEmmanuel Vadot #define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) 368*f126890aSEmmanuel Vadot #define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) 369*f126890aSEmmanuel Vadot #define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) 370*f126890aSEmmanuel Vadot #define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) 371*f126890aSEmmanuel Vadot #define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) 372*f126890aSEmmanuel Vadot #define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) 373*f126890aSEmmanuel Vadot #define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) 374*f126890aSEmmanuel Vadot #define PIN_PB22 54 375*f126890aSEmmanuel Vadot #define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) 376*f126890aSEmmanuel Vadot #define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) 377*f126890aSEmmanuel Vadot #define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) 378*f126890aSEmmanuel Vadot #define PIN_PB22__TD0 PINMUX_PIN(PIN_PB22, 3, 1) 379*f126890aSEmmanuel Vadot #define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) 380*f126890aSEmmanuel Vadot #define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) 381*f126890aSEmmanuel Vadot #define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) 382*f126890aSEmmanuel Vadot #define PIN_PB23 55 383*f126890aSEmmanuel Vadot #define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) 384*f126890aSEmmanuel Vadot #define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) 385*f126890aSEmmanuel Vadot #define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) 386*f126890aSEmmanuel Vadot #define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) 387*f126890aSEmmanuel Vadot #define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) 388*f126890aSEmmanuel Vadot #define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) 389*f126890aSEmmanuel Vadot #define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) 390*f126890aSEmmanuel Vadot #define PIN_PB24 56 391*f126890aSEmmanuel Vadot #define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) 392*f126890aSEmmanuel Vadot #define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) 393*f126890aSEmmanuel Vadot #define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) 394*f126890aSEmmanuel Vadot #define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) 395*f126890aSEmmanuel Vadot #define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) 396*f126890aSEmmanuel Vadot #define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) 397*f126890aSEmmanuel Vadot #define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) 398*f126890aSEmmanuel Vadot #define PIN_PB25 57 399*f126890aSEmmanuel Vadot #define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) 400*f126890aSEmmanuel Vadot #define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) 401*f126890aSEmmanuel Vadot #define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) 402*f126890aSEmmanuel Vadot #define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) 403*f126890aSEmmanuel Vadot #define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) 404*f126890aSEmmanuel Vadot #define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) 405*f126890aSEmmanuel Vadot #define PIN_PB26 58 406*f126890aSEmmanuel Vadot #define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) 407*f126890aSEmmanuel Vadot #define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) 408*f126890aSEmmanuel Vadot #define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) 409*f126890aSEmmanuel Vadot #define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) 410*f126890aSEmmanuel Vadot #define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) 411*f126890aSEmmanuel Vadot #define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) 412*f126890aSEmmanuel Vadot #define PIN_PB27 59 413*f126890aSEmmanuel Vadot #define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) 414*f126890aSEmmanuel Vadot #define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) 415*f126890aSEmmanuel Vadot #define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) 416*f126890aSEmmanuel Vadot #define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) 417*f126890aSEmmanuel Vadot #define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) 418*f126890aSEmmanuel Vadot #define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) 419*f126890aSEmmanuel Vadot #define PIN_PB28 60 420*f126890aSEmmanuel Vadot #define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) 421*f126890aSEmmanuel Vadot #define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) 422*f126890aSEmmanuel Vadot #define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) 423*f126890aSEmmanuel Vadot #define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) 424*f126890aSEmmanuel Vadot #define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) 425*f126890aSEmmanuel Vadot #define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) 426*f126890aSEmmanuel Vadot #define PIN_PB29 61 427*f126890aSEmmanuel Vadot #define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) 428*f126890aSEmmanuel Vadot #define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) 429*f126890aSEmmanuel Vadot #define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) 430*f126890aSEmmanuel Vadot #define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) 431*f126890aSEmmanuel Vadot #define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) 432*f126890aSEmmanuel Vadot #define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) 433*f126890aSEmmanuel Vadot #define PIN_PB30 62 434*f126890aSEmmanuel Vadot #define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) 435*f126890aSEmmanuel Vadot #define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) 436*f126890aSEmmanuel Vadot #define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) 437*f126890aSEmmanuel Vadot #define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) 438*f126890aSEmmanuel Vadot #define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) 439*f126890aSEmmanuel Vadot #define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) 440*f126890aSEmmanuel Vadot #define PIN_PB31 63 441*f126890aSEmmanuel Vadot #define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) 442*f126890aSEmmanuel Vadot #define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) 443*f126890aSEmmanuel Vadot #define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) 444*f126890aSEmmanuel Vadot #define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) 445*f126890aSEmmanuel Vadot #define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) 446*f126890aSEmmanuel Vadot #define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) 447*f126890aSEmmanuel Vadot #define PIN_PC0 64 448*f126890aSEmmanuel Vadot #define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) 449*f126890aSEmmanuel Vadot #define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) 450*f126890aSEmmanuel Vadot #define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) 451*f126890aSEmmanuel Vadot #define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) 452*f126890aSEmmanuel Vadot #define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) 453*f126890aSEmmanuel Vadot #define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) 454*f126890aSEmmanuel Vadot #define PIN_PC1 65 455*f126890aSEmmanuel Vadot #define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) 456*f126890aSEmmanuel Vadot #define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) 457*f126890aSEmmanuel Vadot #define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) 458*f126890aSEmmanuel Vadot #define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) 459*f126890aSEmmanuel Vadot #define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) 460*f126890aSEmmanuel Vadot #define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) 461*f126890aSEmmanuel Vadot #define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) 462*f126890aSEmmanuel Vadot #define PIN_PC2 66 463*f126890aSEmmanuel Vadot #define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) 464*f126890aSEmmanuel Vadot #define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) 465*f126890aSEmmanuel Vadot #define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) 466*f126890aSEmmanuel Vadot #define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) 467*f126890aSEmmanuel Vadot #define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) 468*f126890aSEmmanuel Vadot #define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) 469*f126890aSEmmanuel Vadot #define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) 470*f126890aSEmmanuel Vadot #define PIN_PC3 67 471*f126890aSEmmanuel Vadot #define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) 472*f126890aSEmmanuel Vadot #define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) 473*f126890aSEmmanuel Vadot #define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) 474*f126890aSEmmanuel Vadot #define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) 475*f126890aSEmmanuel Vadot #define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) 476*f126890aSEmmanuel Vadot #define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) 477*f126890aSEmmanuel Vadot #define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) 478*f126890aSEmmanuel Vadot #define PIN_PC4 68 479*f126890aSEmmanuel Vadot #define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) 480*f126890aSEmmanuel Vadot #define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) 481*f126890aSEmmanuel Vadot #define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) 482*f126890aSEmmanuel Vadot #define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) 483*f126890aSEmmanuel Vadot #define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) 484*f126890aSEmmanuel Vadot #define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) 485*f126890aSEmmanuel Vadot #define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) 486*f126890aSEmmanuel Vadot #define PIN_PC5 69 487*f126890aSEmmanuel Vadot #define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) 488*f126890aSEmmanuel Vadot #define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) 489*f126890aSEmmanuel Vadot #define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) 490*f126890aSEmmanuel Vadot #define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) 491*f126890aSEmmanuel Vadot #define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) 492*f126890aSEmmanuel Vadot #define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) 493*f126890aSEmmanuel Vadot #define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) 494*f126890aSEmmanuel Vadot #define PIN_PC6 70 495*f126890aSEmmanuel Vadot #define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) 496*f126890aSEmmanuel Vadot #define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) 497*f126890aSEmmanuel Vadot #define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) 498*f126890aSEmmanuel Vadot #define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) 499*f126890aSEmmanuel Vadot #define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) 500*f126890aSEmmanuel Vadot #define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) 501*f126890aSEmmanuel Vadot #define PIN_PC7 71 502*f126890aSEmmanuel Vadot #define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) 503*f126890aSEmmanuel Vadot #define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) 504*f126890aSEmmanuel Vadot #define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) 505*f126890aSEmmanuel Vadot #define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) 506*f126890aSEmmanuel Vadot #define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) 507*f126890aSEmmanuel Vadot #define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) 508*f126890aSEmmanuel Vadot #define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) 509*f126890aSEmmanuel Vadot #define PIN_PC8 72 510*f126890aSEmmanuel Vadot #define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) 511*f126890aSEmmanuel Vadot #define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) 512*f126890aSEmmanuel Vadot #define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) 513*f126890aSEmmanuel Vadot #define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) 514*f126890aSEmmanuel Vadot #define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) 515*f126890aSEmmanuel Vadot #define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) 516*f126890aSEmmanuel Vadot #define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) 517*f126890aSEmmanuel Vadot #define PIN_PC9 73 518*f126890aSEmmanuel Vadot #define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) 519*f126890aSEmmanuel Vadot #define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) 520*f126890aSEmmanuel Vadot #define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) 521*f126890aSEmmanuel Vadot #define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 3, 1) 522*f126890aSEmmanuel Vadot #define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) 523*f126890aSEmmanuel Vadot #define PIN_PC10 74 524*f126890aSEmmanuel Vadot #define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) 525*f126890aSEmmanuel Vadot #define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) 526*f126890aSEmmanuel Vadot #define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) 527*f126890aSEmmanuel Vadot #define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) 528*f126890aSEmmanuel Vadot #define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) 529*f126890aSEmmanuel Vadot #define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) 530*f126890aSEmmanuel Vadot #define PIN_PC11 75 531*f126890aSEmmanuel Vadot #define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) 532*f126890aSEmmanuel Vadot #define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) 533*f126890aSEmmanuel Vadot #define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) 534*f126890aSEmmanuel Vadot #define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) 535*f126890aSEmmanuel Vadot #define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) 536*f126890aSEmmanuel Vadot #define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) 537*f126890aSEmmanuel Vadot #define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) 538*f126890aSEmmanuel Vadot #define PIN_PC12 76 539*f126890aSEmmanuel Vadot #define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) 540*f126890aSEmmanuel Vadot #define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) 541*f126890aSEmmanuel Vadot #define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) 542*f126890aSEmmanuel Vadot #define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) 543*f126890aSEmmanuel Vadot #define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) 544*f126890aSEmmanuel Vadot #define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) 545*f126890aSEmmanuel Vadot #define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) 546*f126890aSEmmanuel Vadot #define PIN_PC13 77 547*f126890aSEmmanuel Vadot #define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) 548*f126890aSEmmanuel Vadot #define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) 549*f126890aSEmmanuel Vadot #define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) 550*f126890aSEmmanuel Vadot #define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) 551*f126890aSEmmanuel Vadot #define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) 552*f126890aSEmmanuel Vadot #define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) 553*f126890aSEmmanuel Vadot #define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) 554*f126890aSEmmanuel Vadot #define PIN_PC14 78 555*f126890aSEmmanuel Vadot #define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) 556*f126890aSEmmanuel Vadot #define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) 557*f126890aSEmmanuel Vadot #define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) 558*f126890aSEmmanuel Vadot #define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) 559*f126890aSEmmanuel Vadot #define PIN_PC14__TD0 PINMUX_PIN(PIN_PC14, 5, 2) 560*f126890aSEmmanuel Vadot #define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) 561*f126890aSEmmanuel Vadot #define PIN_PC15 79 562*f126890aSEmmanuel Vadot #define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) 563*f126890aSEmmanuel Vadot #define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) 564*f126890aSEmmanuel Vadot #define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) 565*f126890aSEmmanuel Vadot #define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) 566*f126890aSEmmanuel Vadot #define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) 567*f126890aSEmmanuel Vadot #define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) 568*f126890aSEmmanuel Vadot #define PIN_PC16 80 569*f126890aSEmmanuel Vadot #define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) 570*f126890aSEmmanuel Vadot #define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) 571*f126890aSEmmanuel Vadot #define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) 572*f126890aSEmmanuel Vadot #define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) 573*f126890aSEmmanuel Vadot #define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) 574*f126890aSEmmanuel Vadot #define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) 575*f126890aSEmmanuel Vadot #define PIN_PC17 81 576*f126890aSEmmanuel Vadot #define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) 577*f126890aSEmmanuel Vadot #define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) 578*f126890aSEmmanuel Vadot #define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) 579*f126890aSEmmanuel Vadot #define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) 580*f126890aSEmmanuel Vadot #define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) 581*f126890aSEmmanuel Vadot #define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) 582*f126890aSEmmanuel Vadot #define PIN_PC18 82 583*f126890aSEmmanuel Vadot #define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) 584*f126890aSEmmanuel Vadot #define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) 585*f126890aSEmmanuel Vadot #define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) 586*f126890aSEmmanuel Vadot #define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) 587*f126890aSEmmanuel Vadot #define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) 588*f126890aSEmmanuel Vadot #define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) 589*f126890aSEmmanuel Vadot #define PIN_PC19 83 590*f126890aSEmmanuel Vadot #define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) 591*f126890aSEmmanuel Vadot #define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) 592*f126890aSEmmanuel Vadot #define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) 593*f126890aSEmmanuel Vadot #define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) 594*f126890aSEmmanuel Vadot #define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) 595*f126890aSEmmanuel Vadot #define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) 596*f126890aSEmmanuel Vadot #define PIN_PC20 84 597*f126890aSEmmanuel Vadot #define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) 598*f126890aSEmmanuel Vadot #define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) 599*f126890aSEmmanuel Vadot #define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) 600*f126890aSEmmanuel Vadot #define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) 601*f126890aSEmmanuel Vadot #define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) 602*f126890aSEmmanuel Vadot #define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) 603*f126890aSEmmanuel Vadot #define PIN_PC21 85 604*f126890aSEmmanuel Vadot #define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) 605*f126890aSEmmanuel Vadot #define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) 606*f126890aSEmmanuel Vadot #define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) 607*f126890aSEmmanuel Vadot #define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) 608*f126890aSEmmanuel Vadot #define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) 609*f126890aSEmmanuel Vadot #define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) 610*f126890aSEmmanuel Vadot #define PIN_PC22 86 611*f126890aSEmmanuel Vadot #define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) 612*f126890aSEmmanuel Vadot #define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) 613*f126890aSEmmanuel Vadot #define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) 614*f126890aSEmmanuel Vadot #define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) 615*f126890aSEmmanuel Vadot #define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) 616*f126890aSEmmanuel Vadot #define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) 617*f126890aSEmmanuel Vadot #define PIN_PC23 87 618*f126890aSEmmanuel Vadot #define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) 619*f126890aSEmmanuel Vadot #define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) 620*f126890aSEmmanuel Vadot #define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) 621*f126890aSEmmanuel Vadot #define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) 622*f126890aSEmmanuel Vadot #define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) 623*f126890aSEmmanuel Vadot #define PIN_PC24 88 624*f126890aSEmmanuel Vadot #define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) 625*f126890aSEmmanuel Vadot #define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) 626*f126890aSEmmanuel Vadot #define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) 627*f126890aSEmmanuel Vadot #define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) 628*f126890aSEmmanuel Vadot #define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) 629*f126890aSEmmanuel Vadot #define PIN_PC25 89 630*f126890aSEmmanuel Vadot #define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) 631*f126890aSEmmanuel Vadot #define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) 632*f126890aSEmmanuel Vadot #define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) 633*f126890aSEmmanuel Vadot #define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) 634*f126890aSEmmanuel Vadot #define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) 635*f126890aSEmmanuel Vadot #define PIN_PC26 90 636*f126890aSEmmanuel Vadot #define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) 637*f126890aSEmmanuel Vadot #define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) 638*f126890aSEmmanuel Vadot #define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) 639*f126890aSEmmanuel Vadot #define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) 640*f126890aSEmmanuel Vadot #define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) 641*f126890aSEmmanuel Vadot #define PIN_PC27 91 642*f126890aSEmmanuel Vadot #define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) 643*f126890aSEmmanuel Vadot #define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) 644*f126890aSEmmanuel Vadot #define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) 645*f126890aSEmmanuel Vadot #define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) 646*f126890aSEmmanuel Vadot #define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) 647*f126890aSEmmanuel Vadot #define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) 648*f126890aSEmmanuel Vadot #define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) 649*f126890aSEmmanuel Vadot #define PIN_PC28 92 650*f126890aSEmmanuel Vadot #define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) 651*f126890aSEmmanuel Vadot #define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) 652*f126890aSEmmanuel Vadot #define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) 653*f126890aSEmmanuel Vadot #define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) 654*f126890aSEmmanuel Vadot #define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) 655*f126890aSEmmanuel Vadot #define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) 656*f126890aSEmmanuel Vadot #define PIN_PC29 93 657*f126890aSEmmanuel Vadot #define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) 658*f126890aSEmmanuel Vadot #define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) 659*f126890aSEmmanuel Vadot #define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) 660*f126890aSEmmanuel Vadot #define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) 661*f126890aSEmmanuel Vadot #define PIN_PC30 94 662*f126890aSEmmanuel Vadot #define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) 663*f126890aSEmmanuel Vadot #define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) 664*f126890aSEmmanuel Vadot #define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) 665*f126890aSEmmanuel Vadot #define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) 666*f126890aSEmmanuel Vadot #define PIN_PC31 95 667*f126890aSEmmanuel Vadot #define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) 668*f126890aSEmmanuel Vadot #define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) 669*f126890aSEmmanuel Vadot #define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) 670*f126890aSEmmanuel Vadot #define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) 671*f126890aSEmmanuel Vadot #define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) 672*f126890aSEmmanuel Vadot #define PIN_PD0 96 673*f126890aSEmmanuel Vadot #define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) 674*f126890aSEmmanuel Vadot #define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) 675*f126890aSEmmanuel Vadot #define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) 676*f126890aSEmmanuel Vadot #define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) 677*f126890aSEmmanuel Vadot #define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) 678*f126890aSEmmanuel Vadot #define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) 679*f126890aSEmmanuel Vadot #define PIN_PD1 97 680*f126890aSEmmanuel Vadot #define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) 681*f126890aSEmmanuel Vadot #define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) 682*f126890aSEmmanuel Vadot #define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) 683*f126890aSEmmanuel Vadot #define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) 684*f126890aSEmmanuel Vadot #define PIN_PD2 98 685*f126890aSEmmanuel Vadot #define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) 686*f126890aSEmmanuel Vadot #define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) 687*f126890aSEmmanuel Vadot #define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) 688*f126890aSEmmanuel Vadot #define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) 689*f126890aSEmmanuel Vadot #define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) 690*f126890aSEmmanuel Vadot #define PIN_PD3 99 691*f126890aSEmmanuel Vadot #define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) 692*f126890aSEmmanuel Vadot #define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) 693*f126890aSEmmanuel Vadot #define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) 694*f126890aSEmmanuel Vadot #define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) 695*f126890aSEmmanuel Vadot #define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) 696*f126890aSEmmanuel Vadot #define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) 697*f126890aSEmmanuel Vadot #define PIN_PD4 100 698*f126890aSEmmanuel Vadot #define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) 699*f126890aSEmmanuel Vadot #define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) 700*f126890aSEmmanuel Vadot #define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) 701*f126890aSEmmanuel Vadot #define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) 702*f126890aSEmmanuel Vadot #define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) 703*f126890aSEmmanuel Vadot #define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) 704*f126890aSEmmanuel Vadot #define PIN_PD5 101 705*f126890aSEmmanuel Vadot #define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) 706*f126890aSEmmanuel Vadot #define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) 707*f126890aSEmmanuel Vadot #define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) 708*f126890aSEmmanuel Vadot #define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) 709*f126890aSEmmanuel Vadot #define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) 710*f126890aSEmmanuel Vadot #define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) 711*f126890aSEmmanuel Vadot #define PIN_PD6 102 712*f126890aSEmmanuel Vadot #define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) 713*f126890aSEmmanuel Vadot #define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) 714*f126890aSEmmanuel Vadot #define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) 715*f126890aSEmmanuel Vadot #define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) 716*f126890aSEmmanuel Vadot #define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) 717*f126890aSEmmanuel Vadot #define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) 718*f126890aSEmmanuel Vadot #define PIN_PD7 103 719*f126890aSEmmanuel Vadot #define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) 720*f126890aSEmmanuel Vadot #define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) 721*f126890aSEmmanuel Vadot #define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) 722*f126890aSEmmanuel Vadot #define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) 723*f126890aSEmmanuel Vadot #define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) 724*f126890aSEmmanuel Vadot #define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) 725*f126890aSEmmanuel Vadot #define PIN_PD8 104 726*f126890aSEmmanuel Vadot #define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) 727*f126890aSEmmanuel Vadot #define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) 728*f126890aSEmmanuel Vadot #define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) 729*f126890aSEmmanuel Vadot #define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) 730*f126890aSEmmanuel Vadot #define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) 731*f126890aSEmmanuel Vadot #define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) 732*f126890aSEmmanuel Vadot #define PIN_PD9 105 733*f126890aSEmmanuel Vadot #define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) 734*f126890aSEmmanuel Vadot #define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) 735*f126890aSEmmanuel Vadot #define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) 736*f126890aSEmmanuel Vadot #define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) 737*f126890aSEmmanuel Vadot #define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) 738*f126890aSEmmanuel Vadot #define PIN_PD10 106 739*f126890aSEmmanuel Vadot #define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) 740*f126890aSEmmanuel Vadot #define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) 741*f126890aSEmmanuel Vadot #define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) 742*f126890aSEmmanuel Vadot #define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) 743*f126890aSEmmanuel Vadot #define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) 744*f126890aSEmmanuel Vadot #define PIN_PD11 107 745*f126890aSEmmanuel Vadot #define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) 746*f126890aSEmmanuel Vadot #define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) 747*f126890aSEmmanuel Vadot #define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) 748*f126890aSEmmanuel Vadot #define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) 749*f126890aSEmmanuel Vadot #define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) 750*f126890aSEmmanuel Vadot #define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) 751*f126890aSEmmanuel Vadot #define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) 752*f126890aSEmmanuel Vadot #define PIN_PD12 108 753*f126890aSEmmanuel Vadot #define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) 754*f126890aSEmmanuel Vadot #define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) 755*f126890aSEmmanuel Vadot #define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) 756*f126890aSEmmanuel Vadot #define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) 757*f126890aSEmmanuel Vadot #define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) 758*f126890aSEmmanuel Vadot #define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) 759*f126890aSEmmanuel Vadot #define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) 760*f126890aSEmmanuel Vadot #define PIN_PD13 109 761*f126890aSEmmanuel Vadot #define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) 762*f126890aSEmmanuel Vadot #define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) 763*f126890aSEmmanuel Vadot #define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) 764*f126890aSEmmanuel Vadot #define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) 765*f126890aSEmmanuel Vadot #define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) 766*f126890aSEmmanuel Vadot #define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) 767*f126890aSEmmanuel Vadot #define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) 768*f126890aSEmmanuel Vadot #define PIN_PD14 110 769*f126890aSEmmanuel Vadot #define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) 770*f126890aSEmmanuel Vadot #define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) 771*f126890aSEmmanuel Vadot #define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) 772*f126890aSEmmanuel Vadot #define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) 773*f126890aSEmmanuel Vadot #define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) 774*f126890aSEmmanuel Vadot #define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) 775*f126890aSEmmanuel Vadot #define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) 776*f126890aSEmmanuel Vadot #define PIN_PD15 111 777*f126890aSEmmanuel Vadot #define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) 778*f126890aSEmmanuel Vadot #define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) 779*f126890aSEmmanuel Vadot #define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) 780*f126890aSEmmanuel Vadot #define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) 781*f126890aSEmmanuel Vadot #define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) 782*f126890aSEmmanuel Vadot #define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) 783*f126890aSEmmanuel Vadot #define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) 784*f126890aSEmmanuel Vadot #define PIN_PD16 112 785*f126890aSEmmanuel Vadot #define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) 786*f126890aSEmmanuel Vadot #define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) 787*f126890aSEmmanuel Vadot #define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) 788*f126890aSEmmanuel Vadot #define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) 789*f126890aSEmmanuel Vadot #define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) 790*f126890aSEmmanuel Vadot #define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) 791*f126890aSEmmanuel Vadot #define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) 792*f126890aSEmmanuel Vadot #define PIN_PD17 113 793*f126890aSEmmanuel Vadot #define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) 794*f126890aSEmmanuel Vadot #define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) 795*f126890aSEmmanuel Vadot #define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) 796*f126890aSEmmanuel Vadot #define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) 797*f126890aSEmmanuel Vadot #define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) 798*f126890aSEmmanuel Vadot #define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) 799*f126890aSEmmanuel Vadot #define PIN_PD18 114 800*f126890aSEmmanuel Vadot #define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) 801*f126890aSEmmanuel Vadot #define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) 802*f126890aSEmmanuel Vadot #define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) 803*f126890aSEmmanuel Vadot #define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) 804*f126890aSEmmanuel Vadot #define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) 805*f126890aSEmmanuel Vadot #define PIN_PD19 115 806*f126890aSEmmanuel Vadot #define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) 807*f126890aSEmmanuel Vadot #define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) 808*f126890aSEmmanuel Vadot #define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) 809*f126890aSEmmanuel Vadot #define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) 810*f126890aSEmmanuel Vadot #define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) 811*f126890aSEmmanuel Vadot #define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) 812*f126890aSEmmanuel Vadot #define PIN_PD20 116 813*f126890aSEmmanuel Vadot #define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) 814*f126890aSEmmanuel Vadot #define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) 815*f126890aSEmmanuel Vadot #define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) 816*f126890aSEmmanuel Vadot #define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) 817*f126890aSEmmanuel Vadot #define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) 818*f126890aSEmmanuel Vadot #define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) 819*f126890aSEmmanuel Vadot #define PIN_PD21 117 820*f126890aSEmmanuel Vadot #define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) 821*f126890aSEmmanuel Vadot #define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) 822*f126890aSEmmanuel Vadot #define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) 823*f126890aSEmmanuel Vadot #define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) 824*f126890aSEmmanuel Vadot #define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) 825*f126890aSEmmanuel Vadot #define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) 826*f126890aSEmmanuel Vadot #define PIN_PD22 118 827*f126890aSEmmanuel Vadot #define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) 828*f126890aSEmmanuel Vadot #define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) 829*f126890aSEmmanuel Vadot #define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) 830*f126890aSEmmanuel Vadot #define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) 831*f126890aSEmmanuel Vadot #define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) 832*f126890aSEmmanuel Vadot #define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) 833*f126890aSEmmanuel Vadot #define PIN_PD23 119 834*f126890aSEmmanuel Vadot #define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) 835*f126890aSEmmanuel Vadot #define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) 836*f126890aSEmmanuel Vadot #define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) 837*f126890aSEmmanuel Vadot #define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) 838*f126890aSEmmanuel Vadot #define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) 839*f126890aSEmmanuel Vadot #define PIN_PD24 120 840*f126890aSEmmanuel Vadot #define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) 841*f126890aSEmmanuel Vadot #define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD24, 1, 2) 842*f126890aSEmmanuel Vadot #define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD24, 3, 3) 843*f126890aSEmmanuel Vadot #define PIN_PD25 121 844*f126890aSEmmanuel Vadot #define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) 845*f126890aSEmmanuel Vadot #define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) 846*f126890aSEmmanuel Vadot #define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) 847*f126890aSEmmanuel Vadot #define PIN_PD26 122 848*f126890aSEmmanuel Vadot #define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) 849*f126890aSEmmanuel Vadot #define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) 850*f126890aSEmmanuel Vadot #define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) 851*f126890aSEmmanuel Vadot #define PIN_PD27 123 852*f126890aSEmmanuel Vadot #define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) 853*f126890aSEmmanuel Vadot #define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) 854*f126890aSEmmanuel Vadot #define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) 855*f126890aSEmmanuel Vadot #define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) 856*f126890aSEmmanuel Vadot #define PIN_PD28 124 857*f126890aSEmmanuel Vadot #define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) 858*f126890aSEmmanuel Vadot #define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) 859*f126890aSEmmanuel Vadot #define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) 860*f126890aSEmmanuel Vadot #define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) 861*f126890aSEmmanuel Vadot #define PIN_PD29 125 862*f126890aSEmmanuel Vadot #define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) 863*f126890aSEmmanuel Vadot #define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) 864*f126890aSEmmanuel Vadot #define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) 865*f126890aSEmmanuel Vadot #define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) 866*f126890aSEmmanuel Vadot #define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) 867*f126890aSEmmanuel Vadot #define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) 868*f126890aSEmmanuel Vadot #define PIN_PD30 126 869*f126890aSEmmanuel Vadot #define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) 870*f126890aSEmmanuel Vadot #define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) 871*f126890aSEmmanuel Vadot #define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) 872*f126890aSEmmanuel Vadot #define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) 873*f126890aSEmmanuel Vadot #define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) 874*f126890aSEmmanuel Vadot #define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) 875*f126890aSEmmanuel Vadot #define PIN_PD31 127 876*f126890aSEmmanuel Vadot #define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) 877*f126890aSEmmanuel Vadot #define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) 878*f126890aSEmmanuel Vadot #define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) 879*f126890aSEmmanuel Vadot #define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) 880*f126890aSEmmanuel Vadot #define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) 881*f126890aSEmmanuel Vadot #define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) 882