1f126890aSEmmanuel Vadot#include "bcm283x.dtsi" 2f126890aSEmmanuel Vadot#include "bcm2835-common.dtsi" 3f126890aSEmmanuel Vadot 4f126890aSEmmanuel Vadot/ { 5f126890aSEmmanuel Vadot compatible = "brcm,bcm2837"; 6f126890aSEmmanuel Vadot 7f126890aSEmmanuel Vadot soc { 8f126890aSEmmanuel Vadot ranges = <0x7e000000 0x3f000000 0x1000000>, 9f126890aSEmmanuel Vadot <0x40000000 0x40000000 0x00001000>; 10f126890aSEmmanuel Vadot dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 11f126890aSEmmanuel Vadot 12*b2d2a78aSEmmanuel Vadot local_intc: interrupt-controller@40000000 { 13f126890aSEmmanuel Vadot compatible = "brcm,bcm2836-l1-intc"; 14f126890aSEmmanuel Vadot reg = <0x40000000 0x100>; 15f126890aSEmmanuel Vadot interrupt-controller; 16f126890aSEmmanuel Vadot #interrupt-cells = <2>; 17f126890aSEmmanuel Vadot interrupt-parent = <&local_intc>; 18f126890aSEmmanuel Vadot }; 19f126890aSEmmanuel Vadot }; 20f126890aSEmmanuel Vadot 21f126890aSEmmanuel Vadot arm-pmu { 22f126890aSEmmanuel Vadot compatible = "arm,cortex-a53-pmu"; 23f126890aSEmmanuel Vadot interrupt-parent = <&local_intc>; 24f126890aSEmmanuel Vadot interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 25f126890aSEmmanuel Vadot }; 26f126890aSEmmanuel Vadot 27f126890aSEmmanuel Vadot timer { 28f126890aSEmmanuel Vadot compatible = "arm,armv7-timer"; 29f126890aSEmmanuel Vadot interrupt-parent = <&local_intc>; 30f126890aSEmmanuel Vadot interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI 31f126890aSEmmanuel Vadot <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI 32f126890aSEmmanuel Vadot <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI 33f126890aSEmmanuel Vadot <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI 34f126890aSEmmanuel Vadot always-on; 35f126890aSEmmanuel Vadot }; 36f126890aSEmmanuel Vadot 37f126890aSEmmanuel Vadot cpus: cpus { 38f126890aSEmmanuel Vadot #address-cells = <1>; 39f126890aSEmmanuel Vadot #size-cells = <0>; 40f126890aSEmmanuel Vadot enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 41f126890aSEmmanuel Vadot 42f126890aSEmmanuel Vadot /* Source for d/i-cache-line-size and d/i-cache-sets 43f126890aSEmmanuel Vadot * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system 44f126890aSEmmanuel Vadot * /about-the-l1-memory-system?lang=en 45f126890aSEmmanuel Vadot * 46f126890aSEmmanuel Vadot * Source for d/i-cache-size 47f126890aSEmmanuel Vadot * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks 48f126890aSEmmanuel Vadot */ 49f126890aSEmmanuel Vadot cpu0: cpu@0 { 50f126890aSEmmanuel Vadot device_type = "cpu"; 51f126890aSEmmanuel Vadot compatible = "arm,cortex-a53"; 52f126890aSEmmanuel Vadot reg = <0>; 53f126890aSEmmanuel Vadot enable-method = "spin-table"; 54f126890aSEmmanuel Vadot cpu-release-addr = <0x0 0x000000d8>; 55f126890aSEmmanuel Vadot d-cache-size = <0x8000>; 56f126890aSEmmanuel Vadot d-cache-line-size = <64>; 57f126890aSEmmanuel Vadot d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 58f126890aSEmmanuel Vadot i-cache-size = <0x8000>; 59f126890aSEmmanuel Vadot i-cache-line-size = <64>; 60f126890aSEmmanuel Vadot i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 61f126890aSEmmanuel Vadot next-level-cache = <&l2>; 62f126890aSEmmanuel Vadot }; 63f126890aSEmmanuel Vadot 64f126890aSEmmanuel Vadot cpu1: cpu@1 { 65f126890aSEmmanuel Vadot device_type = "cpu"; 66f126890aSEmmanuel Vadot compatible = "arm,cortex-a53"; 67f126890aSEmmanuel Vadot reg = <1>; 68f126890aSEmmanuel Vadot enable-method = "spin-table"; 69f126890aSEmmanuel Vadot cpu-release-addr = <0x0 0x000000e0>; 70f126890aSEmmanuel Vadot d-cache-size = <0x8000>; 71f126890aSEmmanuel Vadot d-cache-line-size = <64>; 72f126890aSEmmanuel Vadot d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 73f126890aSEmmanuel Vadot i-cache-size = <0x8000>; 74f126890aSEmmanuel Vadot i-cache-line-size = <64>; 75f126890aSEmmanuel Vadot i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 76f126890aSEmmanuel Vadot next-level-cache = <&l2>; 77f126890aSEmmanuel Vadot }; 78f126890aSEmmanuel Vadot 79f126890aSEmmanuel Vadot cpu2: cpu@2 { 80f126890aSEmmanuel Vadot device_type = "cpu"; 81f126890aSEmmanuel Vadot compatible = "arm,cortex-a53"; 82f126890aSEmmanuel Vadot reg = <2>; 83f126890aSEmmanuel Vadot enable-method = "spin-table"; 84f126890aSEmmanuel Vadot cpu-release-addr = <0x0 0x000000e8>; 85f126890aSEmmanuel Vadot d-cache-size = <0x8000>; 86f126890aSEmmanuel Vadot d-cache-line-size = <64>; 87f126890aSEmmanuel Vadot d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 88f126890aSEmmanuel Vadot i-cache-size = <0x8000>; 89f126890aSEmmanuel Vadot i-cache-line-size = <64>; 90f126890aSEmmanuel Vadot i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 91f126890aSEmmanuel Vadot next-level-cache = <&l2>; 92f126890aSEmmanuel Vadot }; 93f126890aSEmmanuel Vadot 94f126890aSEmmanuel Vadot cpu3: cpu@3 { 95f126890aSEmmanuel Vadot device_type = "cpu"; 96f126890aSEmmanuel Vadot compatible = "arm,cortex-a53"; 97f126890aSEmmanuel Vadot reg = <3>; 98f126890aSEmmanuel Vadot enable-method = "spin-table"; 99f126890aSEmmanuel Vadot cpu-release-addr = <0x0 0x000000f0>; 100f126890aSEmmanuel Vadot d-cache-size = <0x8000>; 101f126890aSEmmanuel Vadot d-cache-line-size = <64>; 102f126890aSEmmanuel Vadot d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 103f126890aSEmmanuel Vadot i-cache-size = <0x8000>; 104f126890aSEmmanuel Vadot i-cache-line-size = <64>; 105f126890aSEmmanuel Vadot i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 106f126890aSEmmanuel Vadot next-level-cache = <&l2>; 107f126890aSEmmanuel Vadot }; 108f126890aSEmmanuel Vadot 109f126890aSEmmanuel Vadot /* Source for cache-line-size + cache-sets 110f126890aSEmmanuel Vadot * https://developer.arm.com/documentation/ddi0500 111f126890aSEmmanuel Vadot * /e/level-2-memory-system/about-the-l2-memory-system?lang=en 112f126890aSEmmanuel Vadot * Source for cache-size 113f126890aSEmmanuel Vadot * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf 114f126890aSEmmanuel Vadot */ 115f126890aSEmmanuel Vadot l2: l2-cache0 { 116f126890aSEmmanuel Vadot compatible = "cache"; 117f126890aSEmmanuel Vadot cache-unified; 118f126890aSEmmanuel Vadot cache-size = <0x80000>; 119f126890aSEmmanuel Vadot cache-line-size = <64>; 120f126890aSEmmanuel Vadot cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set 121f126890aSEmmanuel Vadot cache-level = <2>; 122f126890aSEmmanuel Vadot }; 123f126890aSEmmanuel Vadot }; 124f126890aSEmmanuel Vadot}; 125f126890aSEmmanuel Vadot 126f126890aSEmmanuel Vadot/* Make the BCM2835-style global interrupt controller be a child of the 127f126890aSEmmanuel Vadot * CPU-local interrupt controller. 128f126890aSEmmanuel Vadot */ 129f126890aSEmmanuel Vadot&intc { 130f126890aSEmmanuel Vadot compatible = "brcm,bcm2836-armctrl-ic"; 131f126890aSEmmanuel Vadot reg = <0x7e00b200 0x200>; 132f126890aSEmmanuel Vadot interrupt-parent = <&local_intc>; 133f126890aSEmmanuel Vadot interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 134f126890aSEmmanuel Vadot}; 135f126890aSEmmanuel Vadot 136f126890aSEmmanuel Vadot&cpu_thermal { 137f126890aSEmmanuel Vadot coefficients = <(-538) 412000>; 138f126890aSEmmanuel Vadot}; 139f126890aSEmmanuel Vadot 140f126890aSEmmanuel Vadot/* enable thermal sensor with the correct compatible property set */ 141f126890aSEmmanuel Vadot&thermal { 142f126890aSEmmanuel Vadot compatible = "brcm,bcm2837-thermal"; 143f126890aSEmmanuel Vadot status = "okay"; 144f126890aSEmmanuel Vadot}; 145