1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_SAMSUNG_I2S_H 3*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_SAMSUNG_I2S_H 4*c66ec88fSEmmanuel Vadot 5*c66ec88fSEmmanuel Vadot #define CLK_I2S_CDCLK 0 /* the CDCLK (CODECLKO) gate clock */ 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadot #define CLK_I2S_RCLK_SRC 1 /* the RCLKSRC mux clock (corresponding to 8*c66ec88fSEmmanuel Vadot * RCLKSRC bit in IISMOD register) 9*c66ec88fSEmmanuel Vadot */ 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel Vadot #define CLK_I2S_RCLK_PSR 2 /* the RCLK prescaler divider clock 12*c66ec88fSEmmanuel Vadot * (corresponding to the IISPSR register) 13*c66ec88fSEmmanuel Vadot */ 14*c66ec88fSEmmanuel Vadot 15*c66ec88fSEmmanuel Vadot #endif /* _DT_BINDINGS_SAMSUNG_I2S_H */ 16