1*5def4c47SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*5def4c47SEmmanuel Vadot /* 3*5def4c47SEmmanuel Vadot * Copyright (c) 2020 MediaTek Inc. 4*5def4c47SEmmanuel Vadot * Author: Yong Liang <yong.liang@mediatek.com> 5*5def4c47SEmmanuel Vadot */ 6*5def4c47SEmmanuel Vadot 7*5def4c47SEmmanuel Vadot #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 8*5def4c47SEmmanuel Vadot #define _DT_BINDINGS_RESET_CONTROLLER_MT8192 9*5def4c47SEmmanuel Vadot 10*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_MM_SW_RST 1 11*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_MFG_SW_RST 2 12*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_VENC_SW_RST 3 13*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_VDEC_SW_RST 4 14*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_IMG_SW_RST 5 15*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_MD_SW_RST 7 16*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_CONN_SW_RST 9 17*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_CONN_MCU_SW_RST 12 18*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_IPU0_SW_RST 14 19*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_IPU1_SW_RST 15 20*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_AUDIO_SW_RST 17 21*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_CAMSYS_SW_RST 18 22*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_MJC_SW_RST 19 23*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_C2K_S2_SW_RST 20 24*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_C2K_SW_RST 21 25*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_PERI_SW_RST 22 26*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_PERI_AO_SW_RST 23 27*5def4c47SEmmanuel Vadot 28*5def4c47SEmmanuel Vadot #define MT8192_TOPRGU_SW_RST_NUM 23 29*5def4c47SEmmanuel Vadot 30*5def4c47SEmmanuel Vadot #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ 31