1c9ccf3a3SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2c9ccf3a3SEmmanuel Vadot /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 3c9ccf3a3SEmmanuel Vadot 4c9ccf3a3SEmmanuel Vadot #ifndef __ABI_MACH_T234_POWERGATE_T234_H_ 5c9ccf3a3SEmmanuel Vadot #define __ABI_MACH_T234_POWERGATE_T234_H_ 6c9ccf3a3SEmmanuel Vadot 7*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_OFA 1U 8c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_AUD 2U 9c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_DISP 3U 10c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX8A 5U 11c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX4A 6U 12c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U 13c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U 14c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX1A 9U 15*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_XUSBA 10U 16*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_XUSBB 11U 17*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_XUSBC 12U 18c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U 19c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U 20c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U 21c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PCIEX8B 16U 22c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_MGBEA 17U 23c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_MGBEB 18U 24c9ccf3a3SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_MGBEC 19U 25b97ee269SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_MGBED 20U 26*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_ISPA 22U 27*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_NVDEC 23U 28*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_NVJPGA 24U 29*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_NVENC 25U 30*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_VI 28U 31b97ee269SEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_VIC 29U 32*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_PVA 30U 33*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_DLAA 32U 34*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_DLAB 33U 35*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_CV 34U 36*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_GPU 35U 37*8bab661aSEmmanuel Vadot #define TEGRA234_POWER_DOMAIN_NVJPGB 36U 38c9ccf3a3SEmmanuel Vadot 39c9ccf3a3SEmmanuel Vadot #endif 40