15def4c47SEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 25def4c47SEmmanuel Vadot /* 35def4c47SEmmanuel Vadot * Copyright (c) 2020 MediaTek Inc. 45def4c47SEmmanuel Vadot * Author: Yong Wu <yong.wu@mediatek.com> 55def4c47SEmmanuel Vadot */ 65def4c47SEmmanuel Vadot #ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ 75def4c47SEmmanuel Vadot #define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_ 85def4c47SEmmanuel Vadot 95def4c47SEmmanuel Vadot #define MTK_LARB_NR_MAX 32 105def4c47SEmmanuel Vadot 115def4c47SEmmanuel Vadot #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) 125def4c47SEmmanuel Vadot #define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x1f) 135def4c47SEmmanuel Vadot #define MTK_M4U_TO_PORT(id) ((id) & 0x1f) 145def4c47SEmmanuel Vadot 15*d5b0e70fSEmmanuel Vadot #define MTK_IFAIOMMU_PERI_ID(port) MTK_M4U_ID(0, port) 16*d5b0e70fSEmmanuel Vadot 175def4c47SEmmanuel Vadot #endif 18