xref: /freebsd-src/sys/contrib/device-tree/include/dt-bindings/interconnect/qcom,sdx75.h (revision 84943d6f38e936ac3b7a3947ca26eeb27a39f938)
1*84943d6fSEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
2*84943d6fSEmmanuel Vadot /*
3*84943d6fSEmmanuel Vadot  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4*84943d6fSEmmanuel Vadot  */
5*84943d6fSEmmanuel Vadot 
6*84943d6fSEmmanuel Vadot #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
7*84943d6fSEmmanuel Vadot #define __DT_BINDINGS_INTERCONNECT_QCOM_SDX75_H
8*84943d6fSEmmanuel Vadot 
9*84943d6fSEmmanuel Vadot #define MASTER_QPIC_CORE		0
10*84943d6fSEmmanuel Vadot #define MASTER_QUP_CORE_0		1
11*84943d6fSEmmanuel Vadot #define SLAVE_QPIC_CORE			2
12*84943d6fSEmmanuel Vadot #define SLAVE_QUP_CORE_0		3
13*84943d6fSEmmanuel Vadot 
14*84943d6fSEmmanuel Vadot #define MASTER_LLCC			0
15*84943d6fSEmmanuel Vadot #define SLAVE_EBI1			1
16*84943d6fSEmmanuel Vadot 
17*84943d6fSEmmanuel Vadot #define MASTER_CNOC_DC_NOC		0
18*84943d6fSEmmanuel Vadot #define SLAVE_LAGG_CFG			1
19*84943d6fSEmmanuel Vadot #define SLAVE_MCCC_MASTER		2
20*84943d6fSEmmanuel Vadot #define SLAVE_GEM_NOC_CFG		3
21*84943d6fSEmmanuel Vadot #define SLAVE_SNOOP_BWMON		4
22*84943d6fSEmmanuel Vadot 
23*84943d6fSEmmanuel Vadot #define MASTER_SYS_TCU			0
24*84943d6fSEmmanuel Vadot #define MASTER_APPSS_PROC		1
25*84943d6fSEmmanuel Vadot #define MASTER_GEM_NOC_CFG		2
26*84943d6fSEmmanuel Vadot #define MASTER_MSS_PROC			3
27*84943d6fSEmmanuel Vadot #define MASTER_ANOC_PCIE_GEM_NOC	4
28*84943d6fSEmmanuel Vadot #define MASTER_SNOC_SF_MEM_NOC		5
29*84943d6fSEmmanuel Vadot #define MASTER_GIC			6
30*84943d6fSEmmanuel Vadot #define MASTER_IPA_PCIE			7
31*84943d6fSEmmanuel Vadot #define SLAVE_GEM_NOC_CNOC		8
32*84943d6fSEmmanuel Vadot #define SLAVE_LLCC			9
33*84943d6fSEmmanuel Vadot #define SLAVE_MEM_NOC_PCIE_SNOC		10
34*84943d6fSEmmanuel Vadot #define SLAVE_SERVICE_GEM_NOC		11
35*84943d6fSEmmanuel Vadot 
36*84943d6fSEmmanuel Vadot #define MASTER_PCIE_0			0
37*84943d6fSEmmanuel Vadot #define MASTER_PCIE_1			1
38*84943d6fSEmmanuel Vadot #define MASTER_PCIE_2			2
39*84943d6fSEmmanuel Vadot #define SLAVE_ANOC_PCIE_GEM_NOC		3
40*84943d6fSEmmanuel Vadot 
41*84943d6fSEmmanuel Vadot #define MASTER_AUDIO			0
42*84943d6fSEmmanuel Vadot #define MASTER_GIC_AHB			1
43*84943d6fSEmmanuel Vadot #define MASTER_PCIE_RSCC		2
44*84943d6fSEmmanuel Vadot #define MASTER_QDSS_BAM			3
45*84943d6fSEmmanuel Vadot #define MASTER_QPIC			4
46*84943d6fSEmmanuel Vadot #define MASTER_QUP_0			5
47*84943d6fSEmmanuel Vadot #define MASTER_ANOC_SNOC		6
48*84943d6fSEmmanuel Vadot #define MASTER_GEM_NOC_CNOC		7
49*84943d6fSEmmanuel Vadot #define MASTER_GEM_NOC_PCIE_SNOC	8
50*84943d6fSEmmanuel Vadot #define MASTER_SNOC_CFG			9
51*84943d6fSEmmanuel Vadot #define MASTER_PCIE_ANOC_CFG		10
52*84943d6fSEmmanuel Vadot #define MASTER_CRYPTO			11
53*84943d6fSEmmanuel Vadot #define MASTER_IPA			12
54*84943d6fSEmmanuel Vadot #define MASTER_MVMSS			13
55*84943d6fSEmmanuel Vadot #define MASTER_EMAC_0			14
56*84943d6fSEmmanuel Vadot #define MASTER_EMAC_1			15
57*84943d6fSEmmanuel Vadot #define MASTER_QDSS_ETR			16
58*84943d6fSEmmanuel Vadot #define MASTER_QDSS_ETR_1		17
59*84943d6fSEmmanuel Vadot #define MASTER_SDCC_1			18
60*84943d6fSEmmanuel Vadot #define MASTER_SDCC_4			19
61*84943d6fSEmmanuel Vadot #define MASTER_USB3_0			20
62*84943d6fSEmmanuel Vadot #define SLAVE_ETH0_CFG			21
63*84943d6fSEmmanuel Vadot #define SLAVE_ETH1_CFG			22
64*84943d6fSEmmanuel Vadot #define SLAVE_AUDIO			23
65*84943d6fSEmmanuel Vadot #define SLAVE_CLK_CTL			24
66*84943d6fSEmmanuel Vadot #define SLAVE_CRYPTO_0_CFG		25
67*84943d6fSEmmanuel Vadot #define SLAVE_IMEM_CFG			26
68*84943d6fSEmmanuel Vadot #define SLAVE_IPA_CFG			27
69*84943d6fSEmmanuel Vadot #define SLAVE_IPC_ROUTER_CFG		28
70*84943d6fSEmmanuel Vadot #define SLAVE_CNOC_MSS			29
71*84943d6fSEmmanuel Vadot #define SLAVE_ICBDI_MVMSS_CFG		30
72*84943d6fSEmmanuel Vadot #define SLAVE_PCIE_0_CFG		31
73*84943d6fSEmmanuel Vadot #define SLAVE_PCIE_1_CFG		32
74*84943d6fSEmmanuel Vadot #define SLAVE_PCIE_2_CFG		33
75*84943d6fSEmmanuel Vadot #define SLAVE_PCIE_RSC_CFG		34
76*84943d6fSEmmanuel Vadot #define SLAVE_PDM			35
77*84943d6fSEmmanuel Vadot #define SLAVE_PRNG			36
78*84943d6fSEmmanuel Vadot #define SLAVE_QDSS_CFG			37
79*84943d6fSEmmanuel Vadot #define SLAVE_QPIC			38
80*84943d6fSEmmanuel Vadot #define SLAVE_QUP_0			39
81*84943d6fSEmmanuel Vadot #define SLAVE_SDCC_1			40
82*84943d6fSEmmanuel Vadot #define SLAVE_SDCC_4			41
83*84943d6fSEmmanuel Vadot #define SLAVE_SPMI_VGI_COEX		42
84*84943d6fSEmmanuel Vadot #define SLAVE_TCSR			43
85*84943d6fSEmmanuel Vadot #define SLAVE_TLMM			44
86*84943d6fSEmmanuel Vadot #define SLAVE_USB3			45
87*84943d6fSEmmanuel Vadot #define SLAVE_USB3_PHY_CFG		46
88*84943d6fSEmmanuel Vadot #define SLAVE_A1NOC_CFG			47
89*84943d6fSEmmanuel Vadot #define SLAVE_DDRSS_CFG			48
90*84943d6fSEmmanuel Vadot #define SLAVE_SNOC_GEM_NOC_SF		49
91*84943d6fSEmmanuel Vadot #define SLAVE_SNOC_CFG			50
92*84943d6fSEmmanuel Vadot #define SLAVE_PCIE_ANOC_CFG		51
93*84943d6fSEmmanuel Vadot #define SLAVE_IMEM			52
94*84943d6fSEmmanuel Vadot #define SLAVE_SERVICE_PCIE_ANOC		53
95*84943d6fSEmmanuel Vadot #define SLAVE_SERVICE_SNOC		54
96*84943d6fSEmmanuel Vadot #define SLAVE_PCIE_0			55
97*84943d6fSEmmanuel Vadot #define SLAVE_PCIE_1			56
98*84943d6fSEmmanuel Vadot #define SLAVE_PCIE_2			57
99*84943d6fSEmmanuel Vadot #define SLAVE_QDSS_STM			58
100*84943d6fSEmmanuel Vadot #define SLAVE_TCU			59
101*84943d6fSEmmanuel Vadot 
102*84943d6fSEmmanuel Vadot #endif
103