15def4c47SEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 25def4c47SEmmanuel Vadot /* 35def4c47SEmmanuel Vadot * Copyright (C) 2019 SiFive, Inc. 45def4c47SEmmanuel Vadot * Wesley Terpstra 55def4c47SEmmanuel Vadot * Paul Walmsley 65def4c47SEmmanuel Vadot * Zong Li 75def4c47SEmmanuel Vadot */ 85def4c47SEmmanuel Vadot 95def4c47SEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H 105def4c47SEmmanuel Vadot #define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H 115def4c47SEmmanuel Vadot 125def4c47SEmmanuel Vadot /* Clock indexes for use by Device Tree data and the PRCI driver */ 135def4c47SEmmanuel Vadot 14*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_COREPLL 0 15*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_DDRPLL 1 16*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_GEMGXLPLL 2 17*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_DVFSCOREPLL 3 18*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_HFPCLKPLL 4 19*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_CLTXPLL 5 20*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_TLCLK 6 21*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_PCLK 7 22*c9ccf3a3SEmmanuel Vadot #define FU740_PRCI_CLK_PCIE_AUX 8 235def4c47SEmmanuel Vadot 245def4c47SEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ 25