1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 4*c66ec88fSEmmanuel Vadot * 5*c66ec88fSEmmanuel Vadot * Device Tree binding constants clock controllers of Samsung S3C2410 and later. 6*c66ec88fSEmmanuel Vadot */ 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H 9*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2410_CLOCK_H 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel Vadot /* 12*c66ec88fSEmmanuel Vadot * Let each exported clock get a unique index, which is used on DT-enabled 13*c66ec88fSEmmanuel Vadot * platforms to lookup the clock from a clock specifier. These indices are 14*c66ec88fSEmmanuel Vadot * therefore considered an ABI and so must not be changed. This implies 15*c66ec88fSEmmanuel Vadot * that new clocks should be added either in free spaces between clock groups 16*c66ec88fSEmmanuel Vadot * or at the end. 17*c66ec88fSEmmanuel Vadot */ 18*c66ec88fSEmmanuel Vadot 19*c66ec88fSEmmanuel Vadot /* Core clocks. */ 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadot /* id 1 is reserved */ 22*c66ec88fSEmmanuel Vadot #define MPLL 2 23*c66ec88fSEmmanuel Vadot #define UPLL 3 24*c66ec88fSEmmanuel Vadot #define FCLK 4 25*c66ec88fSEmmanuel Vadot #define HCLK 5 26*c66ec88fSEmmanuel Vadot #define PCLK 6 27*c66ec88fSEmmanuel Vadot #define UCLK 7 28*c66ec88fSEmmanuel Vadot #define ARMCLK 8 29*c66ec88fSEmmanuel Vadot 30*c66ec88fSEmmanuel Vadot /* pclk-gates */ 31*c66ec88fSEmmanuel Vadot #define PCLK_UART0 16 32*c66ec88fSEmmanuel Vadot #define PCLK_UART1 17 33*c66ec88fSEmmanuel Vadot #define PCLK_UART2 18 34*c66ec88fSEmmanuel Vadot #define PCLK_I2C 19 35*c66ec88fSEmmanuel Vadot #define PCLK_SDI 20 36*c66ec88fSEmmanuel Vadot #define PCLK_SPI 21 37*c66ec88fSEmmanuel Vadot #define PCLK_ADC 22 38*c66ec88fSEmmanuel Vadot #define PCLK_AC97 23 39*c66ec88fSEmmanuel Vadot #define PCLK_I2S 24 40*c66ec88fSEmmanuel Vadot #define PCLK_PWM 25 41*c66ec88fSEmmanuel Vadot #define PCLK_RTC 26 42*c66ec88fSEmmanuel Vadot #define PCLK_GPIO 27 43*c66ec88fSEmmanuel Vadot 44*c66ec88fSEmmanuel Vadot 45*c66ec88fSEmmanuel Vadot /* hclk-gates */ 46*c66ec88fSEmmanuel Vadot #define HCLK_LCD 32 47*c66ec88fSEmmanuel Vadot #define HCLK_USBH 33 48*c66ec88fSEmmanuel Vadot #define HCLK_USBD 34 49*c66ec88fSEmmanuel Vadot #define HCLK_NAND 35 50*c66ec88fSEmmanuel Vadot #define HCLK_CAM 36 51*c66ec88fSEmmanuel Vadot 52*c66ec88fSEmmanuel Vadot 53*c66ec88fSEmmanuel Vadot #define CAMIF 40 54*c66ec88fSEmmanuel Vadot 55*c66ec88fSEmmanuel Vadot 56*c66ec88fSEmmanuel Vadot /* Total number of clocks. */ 57*c66ec88fSEmmanuel Vadot #define NR_CLKS (CAMIF + 1) 58*c66ec88fSEmmanuel Vadot 59*c66ec88fSEmmanuel Vadot #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ 60