1*b2d2a78aSEmmanuel Vadot /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b2d2a78aSEmmanuel Vadot * 3*b2d2a78aSEmmanuel Vadot * Copyright (C) 2024 Renesas Electronics Corp. 4*b2d2a78aSEmmanuel Vadot */ 5*b2d2a78aSEmmanuel Vadot #ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ 6*b2d2a78aSEmmanuel Vadot #define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ 7*b2d2a78aSEmmanuel Vadot 8*b2d2a78aSEmmanuel Vadot #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*b2d2a78aSEmmanuel Vadot 10*b2d2a78aSEmmanuel Vadot /* Core Clock list */ 11*b2d2a78aSEmmanuel Vadot #define R9A09G057_SYS_0_PCLK 0 12*b2d2a78aSEmmanuel Vadot #define R9A09G057_CA55_0_CORE_CLK0 1 13*b2d2a78aSEmmanuel Vadot #define R9A09G057_CA55_0_CORE_CLK1 2 14*b2d2a78aSEmmanuel Vadot #define R9A09G057_CA55_0_CORE_CLK2 3 15*b2d2a78aSEmmanuel Vadot #define R9A09G057_CA55_0_CORE_CLK3 4 16*b2d2a78aSEmmanuel Vadot #define R9A09G057_CA55_0_PERIPHCLK 5 17*b2d2a78aSEmmanuel Vadot #define R9A09G057_CM33_CLK0 6 18*b2d2a78aSEmmanuel Vadot #define R9A09G057_CST_0_SWCLKTCK 7 19*b2d2a78aSEmmanuel Vadot #define R9A09G057_IOTOP_0_SHCLK 8 20*b2d2a78aSEmmanuel Vadot 21*b2d2a78aSEmmanuel Vadot #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ 22