1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H 7*c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot #define GPLL0 0 10*c66ec88fSEmmanuel Vadot #define GPLL0_MAIN 1 11*c66ec88fSEmmanuel Vadot #define GCC_SLEEP_CLK_SRC 2 12*c66ec88fSEmmanuel Vadot #define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 13*c66ec88fSEmmanuel Vadot #define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 14*c66ec88fSEmmanuel Vadot #define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 15*c66ec88fSEmmanuel Vadot #define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 16*c66ec88fSEmmanuel Vadot #define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 17*c66ec88fSEmmanuel Vadot #define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 18*c66ec88fSEmmanuel Vadot #define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 19*c66ec88fSEmmanuel Vadot #define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 20*c66ec88fSEmmanuel Vadot #define BLSP1_QUP5_I2C_APPS_CLK_SRC 11 21*c66ec88fSEmmanuel Vadot #define BLSP1_QUP5_SPI_APPS_CLK_SRC 12 22*c66ec88fSEmmanuel Vadot #define BLSP1_QUP6_I2C_APPS_CLK_SRC 13 23*c66ec88fSEmmanuel Vadot #define BLSP1_QUP6_SPI_APPS_CLK_SRC 14 24*c66ec88fSEmmanuel Vadot #define BLSP1_UART1_APPS_CLK_SRC 15 25*c66ec88fSEmmanuel Vadot #define BLSP1_UART2_APPS_CLK_SRC 16 26*c66ec88fSEmmanuel Vadot #define BLSP1_UART3_APPS_CLK_SRC 17 27*c66ec88fSEmmanuel Vadot #define BLSP1_UART4_APPS_CLK_SRC 18 28*c66ec88fSEmmanuel Vadot #define BLSP1_UART5_APPS_CLK_SRC 19 29*c66ec88fSEmmanuel Vadot #define BLSP1_UART6_APPS_CLK_SRC 20 30*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_AHB_CLK 21 31*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 32*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 33*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 34*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 35*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_I2C_APPS_CLK 26 36*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_SPI_APPS_CLK 27 37*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_I2C_APPS_CLK 28 38*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_SPI_APPS_CLK 29 39*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_I2C_APPS_CLK 30 40*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_SPI_APPS_CLK 31 41*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_I2C_APPS_CLK 32 42*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_SPI_APPS_CLK 33 43*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART1_APPS_CLK 34 44*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART2_APPS_CLK 35 45*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART3_APPS_CLK 36 46*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART4_APPS_CLK 37 47*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART5_APPS_CLK 38 48*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART6_APPS_CLK 39 49*c66ec88fSEmmanuel Vadot #define GCC_PRNG_AHB_CLK 40 50*c66ec88fSEmmanuel Vadot #define GCC_QPIC_AHB_CLK 41 51*c66ec88fSEmmanuel Vadot #define GCC_QPIC_CLK 42 52*c66ec88fSEmmanuel Vadot #define PCNOC_BFDCD_CLK_SRC 43 53*c66ec88fSEmmanuel Vadot #define GPLL2_MAIN 44 54*c66ec88fSEmmanuel Vadot #define GPLL2 45 55*c66ec88fSEmmanuel Vadot #define GPLL4_MAIN 46 56*c66ec88fSEmmanuel Vadot #define GPLL4 47 57*c66ec88fSEmmanuel Vadot #define GPLL6_MAIN 48 58*c66ec88fSEmmanuel Vadot #define GPLL6 49 59*c66ec88fSEmmanuel Vadot #define UBI32_PLL_MAIN 50 60*c66ec88fSEmmanuel Vadot #define UBI32_PLL 51 61*c66ec88fSEmmanuel Vadot #define NSS_CRYPTO_PLL_MAIN 52 62*c66ec88fSEmmanuel Vadot #define NSS_CRYPTO_PLL 53 63*c66ec88fSEmmanuel Vadot #define PCIE0_AXI_CLK_SRC 54 64*c66ec88fSEmmanuel Vadot #define PCIE0_AUX_CLK_SRC 55 65*c66ec88fSEmmanuel Vadot #define PCIE0_PIPE_CLK_SRC 56 66*c66ec88fSEmmanuel Vadot #define PCIE1_AXI_CLK_SRC 57 67*c66ec88fSEmmanuel Vadot #define PCIE1_AUX_CLK_SRC 58 68*c66ec88fSEmmanuel Vadot #define PCIE1_PIPE_CLK_SRC 59 69*c66ec88fSEmmanuel Vadot #define SDCC1_APPS_CLK_SRC 60 70*c66ec88fSEmmanuel Vadot #define SDCC1_ICE_CORE_CLK_SRC 61 71*c66ec88fSEmmanuel Vadot #define SDCC2_APPS_CLK_SRC 62 72*c66ec88fSEmmanuel Vadot #define USB0_MASTER_CLK_SRC 63 73*c66ec88fSEmmanuel Vadot #define USB0_AUX_CLK_SRC 64 74*c66ec88fSEmmanuel Vadot #define USB0_MOCK_UTMI_CLK_SRC 65 75*c66ec88fSEmmanuel Vadot #define USB0_PIPE_CLK_SRC 66 76*c66ec88fSEmmanuel Vadot #define USB1_MASTER_CLK_SRC 67 77*c66ec88fSEmmanuel Vadot #define USB1_AUX_CLK_SRC 68 78*c66ec88fSEmmanuel Vadot #define USB1_MOCK_UTMI_CLK_SRC 69 79*c66ec88fSEmmanuel Vadot #define USB1_PIPE_CLK_SRC 70 80*c66ec88fSEmmanuel Vadot #define GCC_XO_CLK_SRC 71 81*c66ec88fSEmmanuel Vadot #define SYSTEM_NOC_BFDCD_CLK_SRC 72 82*c66ec88fSEmmanuel Vadot #define NSS_CE_CLK_SRC 73 83*c66ec88fSEmmanuel Vadot #define NSS_NOC_BFDCD_CLK_SRC 74 84*c66ec88fSEmmanuel Vadot #define NSS_CRYPTO_CLK_SRC 75 85*c66ec88fSEmmanuel Vadot #define NSS_UBI0_CLK_SRC 76 86*c66ec88fSEmmanuel Vadot #define NSS_UBI0_DIV_CLK_SRC 77 87*c66ec88fSEmmanuel Vadot #define NSS_UBI1_CLK_SRC 78 88*c66ec88fSEmmanuel Vadot #define NSS_UBI1_DIV_CLK_SRC 79 89*c66ec88fSEmmanuel Vadot #define UBI_MPT_CLK_SRC 80 90*c66ec88fSEmmanuel Vadot #define NSS_IMEM_CLK_SRC 81 91*c66ec88fSEmmanuel Vadot #define NSS_PPE_CLK_SRC 82 92*c66ec88fSEmmanuel Vadot #define NSS_PORT1_RX_CLK_SRC 83 93*c66ec88fSEmmanuel Vadot #define NSS_PORT1_RX_DIV_CLK_SRC 84 94*c66ec88fSEmmanuel Vadot #define NSS_PORT1_TX_CLK_SRC 85 95*c66ec88fSEmmanuel Vadot #define NSS_PORT1_TX_DIV_CLK_SRC 86 96*c66ec88fSEmmanuel Vadot #define NSS_PORT2_RX_CLK_SRC 87 97*c66ec88fSEmmanuel Vadot #define NSS_PORT2_RX_DIV_CLK_SRC 88 98*c66ec88fSEmmanuel Vadot #define NSS_PORT2_TX_CLK_SRC 89 99*c66ec88fSEmmanuel Vadot #define NSS_PORT2_TX_DIV_CLK_SRC 90 100*c66ec88fSEmmanuel Vadot #define NSS_PORT3_RX_CLK_SRC 91 101*c66ec88fSEmmanuel Vadot #define NSS_PORT3_RX_DIV_CLK_SRC 92 102*c66ec88fSEmmanuel Vadot #define NSS_PORT3_TX_CLK_SRC 93 103*c66ec88fSEmmanuel Vadot #define NSS_PORT3_TX_DIV_CLK_SRC 94 104*c66ec88fSEmmanuel Vadot #define NSS_PORT4_RX_CLK_SRC 95 105*c66ec88fSEmmanuel Vadot #define NSS_PORT4_RX_DIV_CLK_SRC 96 106*c66ec88fSEmmanuel Vadot #define NSS_PORT4_TX_CLK_SRC 97 107*c66ec88fSEmmanuel Vadot #define NSS_PORT4_TX_DIV_CLK_SRC 98 108*c66ec88fSEmmanuel Vadot #define NSS_PORT5_RX_CLK_SRC 99 109*c66ec88fSEmmanuel Vadot #define NSS_PORT5_RX_DIV_CLK_SRC 100 110*c66ec88fSEmmanuel Vadot #define NSS_PORT5_TX_CLK_SRC 101 111*c66ec88fSEmmanuel Vadot #define NSS_PORT5_TX_DIV_CLK_SRC 102 112*c66ec88fSEmmanuel Vadot #define NSS_PORT6_RX_CLK_SRC 103 113*c66ec88fSEmmanuel Vadot #define NSS_PORT6_RX_DIV_CLK_SRC 104 114*c66ec88fSEmmanuel Vadot #define NSS_PORT6_TX_CLK_SRC 105 115*c66ec88fSEmmanuel Vadot #define NSS_PORT6_TX_DIV_CLK_SRC 106 116*c66ec88fSEmmanuel Vadot #define CRYPTO_CLK_SRC 107 117*c66ec88fSEmmanuel Vadot #define GP1_CLK_SRC 108 118*c66ec88fSEmmanuel Vadot #define GP2_CLK_SRC 109 119*c66ec88fSEmmanuel Vadot #define GP3_CLK_SRC 110 120*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AHB_CLK 111 121*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AUX_CLK 112 122*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AXI_M_CLK 113 123*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AXI_S_CLK 114 124*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_PIPE_CLK 115 125*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_PCIE0_AXI_CLK 116 126*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_AHB_CLK 117 127*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_AUX_CLK 118 128*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_AXI_M_CLK 119 129*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_AXI_S_CLK 120 130*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_PIPE_CLK 121 131*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_PCIE1_AXI_CLK 122 132*c66ec88fSEmmanuel Vadot #define GCC_USB0_AUX_CLK 123 133*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_USB0_AXI_CLK 124 134*c66ec88fSEmmanuel Vadot #define GCC_USB0_MASTER_CLK 125 135*c66ec88fSEmmanuel Vadot #define GCC_USB0_MOCK_UTMI_CLK 126 136*c66ec88fSEmmanuel Vadot #define GCC_USB0_PHY_CFG_AHB_CLK 127 137*c66ec88fSEmmanuel Vadot #define GCC_USB0_PIPE_CLK 128 138*c66ec88fSEmmanuel Vadot #define GCC_USB0_SLEEP_CLK 129 139*c66ec88fSEmmanuel Vadot #define GCC_USB1_AUX_CLK 130 140*c66ec88fSEmmanuel Vadot #define GCC_SYS_NOC_USB1_AXI_CLK 131 141*c66ec88fSEmmanuel Vadot #define GCC_USB1_MASTER_CLK 132 142*c66ec88fSEmmanuel Vadot #define GCC_USB1_MOCK_UTMI_CLK 133 143*c66ec88fSEmmanuel Vadot #define GCC_USB1_PHY_CFG_AHB_CLK 134 144*c66ec88fSEmmanuel Vadot #define GCC_USB1_PIPE_CLK 135 145*c66ec88fSEmmanuel Vadot #define GCC_USB1_SLEEP_CLK 136 146*c66ec88fSEmmanuel Vadot #define GCC_SDCC1_AHB_CLK 137 147*c66ec88fSEmmanuel Vadot #define GCC_SDCC1_APPS_CLK 138 148*c66ec88fSEmmanuel Vadot #define GCC_SDCC1_ICE_CORE_CLK 139 149*c66ec88fSEmmanuel Vadot #define GCC_SDCC2_AHB_CLK 140 150*c66ec88fSEmmanuel Vadot #define GCC_SDCC2_APPS_CLK 141 151*c66ec88fSEmmanuel Vadot #define GCC_MEM_NOC_NSS_AXI_CLK 142 152*c66ec88fSEmmanuel Vadot #define GCC_NSS_CE_APB_CLK 143 153*c66ec88fSEmmanuel Vadot #define GCC_NSS_CE_AXI_CLK 144 154*c66ec88fSEmmanuel Vadot #define GCC_NSS_CFG_CLK 145 155*c66ec88fSEmmanuel Vadot #define GCC_NSS_CRYPTO_CLK 146 156*c66ec88fSEmmanuel Vadot #define GCC_NSS_CSR_CLK 147 157*c66ec88fSEmmanuel Vadot #define GCC_NSS_EDMA_CFG_CLK 148 158*c66ec88fSEmmanuel Vadot #define GCC_NSS_EDMA_CLK 149 159*c66ec88fSEmmanuel Vadot #define GCC_NSS_IMEM_CLK 150 160*c66ec88fSEmmanuel Vadot #define GCC_NSS_NOC_CLK 151 161*c66ec88fSEmmanuel Vadot #define GCC_NSS_PPE_BTQ_CLK 152 162*c66ec88fSEmmanuel Vadot #define GCC_NSS_PPE_CFG_CLK 153 163*c66ec88fSEmmanuel Vadot #define GCC_NSS_PPE_CLK 154 164*c66ec88fSEmmanuel Vadot #define GCC_NSS_PPE_IPE_CLK 155 165*c66ec88fSEmmanuel Vadot #define GCC_NSS_PTP_REF_CLK 156 166*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_CE_APB_CLK 157 167*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_CE_AXI_CLK 158 168*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_CRYPTO_CLK 159 169*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_PPE_CFG_CLK 160 170*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_PPE_CLK 161 171*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_QOSGEN_REF_CLK 162 172*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_SNOC_CLK 163 173*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_TIMEOUT_REF_CLK 164 174*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_UBI0_AHB_CLK 165 175*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_UBI1_AHB_CLK 166 176*c66ec88fSEmmanuel Vadot #define GCC_UBI0_AHB_CLK 167 177*c66ec88fSEmmanuel Vadot #define GCC_UBI0_AXI_CLK 168 178*c66ec88fSEmmanuel Vadot #define GCC_UBI0_NC_AXI_CLK 169 179*c66ec88fSEmmanuel Vadot #define GCC_UBI0_CORE_CLK 170 180*c66ec88fSEmmanuel Vadot #define GCC_UBI0_MPT_CLK 171 181*c66ec88fSEmmanuel Vadot #define GCC_UBI1_AHB_CLK 172 182*c66ec88fSEmmanuel Vadot #define GCC_UBI1_AXI_CLK 173 183*c66ec88fSEmmanuel Vadot #define GCC_UBI1_NC_AXI_CLK 174 184*c66ec88fSEmmanuel Vadot #define GCC_UBI1_CORE_CLK 175 185*c66ec88fSEmmanuel Vadot #define GCC_UBI1_MPT_CLK 176 186*c66ec88fSEmmanuel Vadot #define GCC_CMN_12GPLL_AHB_CLK 177 187*c66ec88fSEmmanuel Vadot #define GCC_CMN_12GPLL_SYS_CLK 178 188*c66ec88fSEmmanuel Vadot #define GCC_MDIO_AHB_CLK 179 189*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_AHB_CLK 180 190*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_SYS_CLK 181 191*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY1_AHB_CLK 182 192*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY1_SYS_CLK 183 193*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY2_AHB_CLK 184 194*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY2_SYS_CLK 185 195*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT1_RX_CLK 186 196*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT1_TX_CLK 187 197*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT2_RX_CLK 188 198*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT2_TX_CLK 189 199*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT3_RX_CLK 190 200*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT3_TX_CLK 191 201*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT4_RX_CLK 192 202*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT4_TX_CLK 193 203*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT5_RX_CLK 194 204*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT5_TX_CLK 195 205*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT6_RX_CLK 196 206*c66ec88fSEmmanuel Vadot #define GCC_NSS_PORT6_TX_CLK 197 207*c66ec88fSEmmanuel Vadot #define GCC_PORT1_MAC_CLK 198 208*c66ec88fSEmmanuel Vadot #define GCC_PORT2_MAC_CLK 199 209*c66ec88fSEmmanuel Vadot #define GCC_PORT3_MAC_CLK 200 210*c66ec88fSEmmanuel Vadot #define GCC_PORT4_MAC_CLK 201 211*c66ec88fSEmmanuel Vadot #define GCC_PORT5_MAC_CLK 202 212*c66ec88fSEmmanuel Vadot #define GCC_PORT6_MAC_CLK 203 213*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT1_RX_CLK 204 214*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT1_TX_CLK 205 215*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT2_RX_CLK 206 216*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT2_TX_CLK 207 217*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT3_RX_CLK 208 218*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT3_TX_CLK 209 219*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT4_RX_CLK 210 220*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT4_TX_CLK 211 221*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT5_RX_CLK 212 222*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_PORT5_TX_CLK 213 223*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY1_PORT5_RX_CLK 214 224*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY1_PORT5_TX_CLK 215 225*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY2_PORT6_RX_CLK 216 226*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY2_PORT6_TX_CLK 217 227*c66ec88fSEmmanuel Vadot #define GCC_CRYPTO_AHB_CLK 218 228*c66ec88fSEmmanuel Vadot #define GCC_CRYPTO_AXI_CLK 219 229*c66ec88fSEmmanuel Vadot #define GCC_CRYPTO_CLK 220 230*c66ec88fSEmmanuel Vadot #define GCC_GP1_CLK 221 231*c66ec88fSEmmanuel Vadot #define GCC_GP2_CLK 222 232*c66ec88fSEmmanuel Vadot #define GCC_GP3_CLK 223 233*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 234*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_RCHNG_CLK_SRC 225 235*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_RCHNG_CLK 226 236*c66ec88fSEmmanuel Vadot 237*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_BCR 0 238*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP1_BCR 1 239*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART1_BCR 2 240*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP2_BCR 3 241*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART2_BCR 4 242*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP3_BCR 5 243*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART3_BCR 6 244*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP4_BCR 7 245*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART4_BCR 8 246*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP5_BCR 9 247*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART5_BCR 10 248*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_QUP6_BCR 11 249*c66ec88fSEmmanuel Vadot #define GCC_BLSP1_UART6_BCR 12 250*c66ec88fSEmmanuel Vadot #define GCC_IMEM_BCR 13 251*c66ec88fSEmmanuel Vadot #define GCC_SMMU_BCR 14 252*c66ec88fSEmmanuel Vadot #define GCC_APSS_TCU_BCR 15 253*c66ec88fSEmmanuel Vadot #define GCC_SMMU_XPU_BCR 16 254*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_TBU_BCR 17 255*c66ec88fSEmmanuel Vadot #define GCC_SMMU_CFG_BCR 18 256*c66ec88fSEmmanuel Vadot #define GCC_PRNG_BCR 19 257*c66ec88fSEmmanuel Vadot #define GCC_BOOT_ROM_BCR 20 258*c66ec88fSEmmanuel Vadot #define GCC_CRYPTO_BCR 21 259*c66ec88fSEmmanuel Vadot #define GCC_WCSS_BCR 22 260*c66ec88fSEmmanuel Vadot #define GCC_WCSS_Q6_BCR 23 261*c66ec88fSEmmanuel Vadot #define GCC_NSS_BCR 24 262*c66ec88fSEmmanuel Vadot #define GCC_SEC_CTRL_BCR 25 263*c66ec88fSEmmanuel Vadot #define GCC_ADSS_BCR 26 264*c66ec88fSEmmanuel Vadot #define GCC_DDRSS_BCR 27 265*c66ec88fSEmmanuel Vadot #define GCC_SYSTEM_NOC_BCR 28 266*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BCR 29 267*c66ec88fSEmmanuel Vadot #define GCC_TCSR_BCR 30 268*c66ec88fSEmmanuel Vadot #define GCC_QDSS_BCR 31 269*c66ec88fSEmmanuel Vadot #define GCC_DCD_BCR 32 270*c66ec88fSEmmanuel Vadot #define GCC_MSG_RAM_BCR 33 271*c66ec88fSEmmanuel Vadot #define GCC_MPM_BCR 34 272*c66ec88fSEmmanuel Vadot #define GCC_SPMI_BCR 35 273*c66ec88fSEmmanuel Vadot #define GCC_SPDM_BCR 36 274*c66ec88fSEmmanuel Vadot #define GCC_RBCPR_BCR 37 275*c66ec88fSEmmanuel Vadot #define GCC_RBCPR_MX_BCR 38 276*c66ec88fSEmmanuel Vadot #define GCC_TLMM_BCR 39 277*c66ec88fSEmmanuel Vadot #define GCC_RBCPR_WCSS_BCR 40 278*c66ec88fSEmmanuel Vadot #define GCC_USB0_PHY_BCR 41 279*c66ec88fSEmmanuel Vadot #define GCC_USB3PHY_0_PHY_BCR 42 280*c66ec88fSEmmanuel Vadot #define GCC_USB0_BCR 43 281*c66ec88fSEmmanuel Vadot #define GCC_USB1_PHY_BCR 44 282*c66ec88fSEmmanuel Vadot #define GCC_USB3PHY_1_PHY_BCR 45 283*c66ec88fSEmmanuel Vadot #define GCC_USB1_BCR 46 284*c66ec88fSEmmanuel Vadot #define GCC_QUSB2_0_PHY_BCR 47 285*c66ec88fSEmmanuel Vadot #define GCC_QUSB2_1_PHY_BCR 48 286*c66ec88fSEmmanuel Vadot #define GCC_SDCC1_BCR 49 287*c66ec88fSEmmanuel Vadot #define GCC_SDCC2_BCR 50 288*c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT0_BCR 51 289*c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT2_BCR 52 290*c66ec88fSEmmanuel Vadot #define GCC_SNOC_BUS_TIMEOUT3_BCR 53 291*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 292*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 293*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 294*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 295*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 296*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 297*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 298*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 299*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 300*c66ec88fSEmmanuel Vadot #define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 301*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY0_BCR 64 302*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY1_BCR 65 303*c66ec88fSEmmanuel Vadot #define GCC_UNIPHY2_BCR 66 304*c66ec88fSEmmanuel Vadot #define GCC_CMN_12GPLL_BCR 67 305*c66ec88fSEmmanuel Vadot #define GCC_QPIC_BCR 68 306*c66ec88fSEmmanuel Vadot #define GCC_MDIO_BCR 69 307*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_TBU_BCR 70 308*c66ec88fSEmmanuel Vadot #define GCC_WCSS_CORE_TBU_BCR 71 309*c66ec88fSEmmanuel Vadot #define GCC_WCSS_Q6_TBU_BCR 72 310*c66ec88fSEmmanuel Vadot #define GCC_USB0_TBU_BCR 73 311*c66ec88fSEmmanuel Vadot #define GCC_USB1_TBU_BCR 74 312*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_TBU_BCR 75 313*c66ec88fSEmmanuel Vadot #define GCC_NSS_NOC_TBU_BCR 76 314*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_BCR 77 315*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_PHY_BCR 78 316*c66ec88fSEmmanuel Vadot #define GCC_PCIE0PHY_PHY_BCR 79 317*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_LINK_DOWN_BCR 80 318*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_BCR 81 319*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_PHY_BCR 82 320*c66ec88fSEmmanuel Vadot #define GCC_PCIE1PHY_PHY_BCR 83 321*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_LINK_DOWN_BCR 84 322*c66ec88fSEmmanuel Vadot #define GCC_DCC_BCR 85 323*c66ec88fSEmmanuel Vadot #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86 324*c66ec88fSEmmanuel Vadot #define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87 325*c66ec88fSEmmanuel Vadot #define GCC_SMMU_CATS_BCR 88 326*c66ec88fSEmmanuel Vadot #define GCC_UBI0_AXI_ARES 89 327*c66ec88fSEmmanuel Vadot #define GCC_UBI0_AHB_ARES 90 328*c66ec88fSEmmanuel Vadot #define GCC_UBI0_NC_AXI_ARES 91 329*c66ec88fSEmmanuel Vadot #define GCC_UBI0_DBG_ARES 92 330*c66ec88fSEmmanuel Vadot #define GCC_UBI0_CORE_CLAMP_ENABLE 93 331*c66ec88fSEmmanuel Vadot #define GCC_UBI0_CLKRST_CLAMP_ENABLE 94 332*c66ec88fSEmmanuel Vadot #define GCC_UBI1_AXI_ARES 95 333*c66ec88fSEmmanuel Vadot #define GCC_UBI1_AHB_ARES 96 334*c66ec88fSEmmanuel Vadot #define GCC_UBI1_NC_AXI_ARES 97 335*c66ec88fSEmmanuel Vadot #define GCC_UBI1_DBG_ARES 98 336*c66ec88fSEmmanuel Vadot #define GCC_UBI1_CORE_CLAMP_ENABLE 99 337*c66ec88fSEmmanuel Vadot #define GCC_UBI1_CLKRST_CLAMP_ENABLE 100 338*c66ec88fSEmmanuel Vadot #define GCC_NSS_CFG_ARES 101 339*c66ec88fSEmmanuel Vadot #define GCC_NSS_IMEM_ARES 102 340*c66ec88fSEmmanuel Vadot #define GCC_NSS_NOC_ARES 103 341*c66ec88fSEmmanuel Vadot #define GCC_NSS_CRYPTO_ARES 104 342*c66ec88fSEmmanuel Vadot #define GCC_NSS_CSR_ARES 105 343*c66ec88fSEmmanuel Vadot #define GCC_NSS_CE_APB_ARES 106 344*c66ec88fSEmmanuel Vadot #define GCC_NSS_CE_AXI_ARES 107 345*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_CE_APB_ARES 108 346*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_CE_AXI_ARES 109 347*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_UBI0_AHB_ARES 110 348*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_UBI1_AHB_ARES 111 349*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_SNOC_ARES 112 350*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_CRYPTO_ARES 113 351*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_ATB_ARES 114 352*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_QOSGEN_REF_ARES 115 353*c66ec88fSEmmanuel Vadot #define GCC_NSSNOC_TIMEOUT_REF_ARES 116 354*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_PIPE_ARES 117 355*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_SLEEP_ARES 118 356*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_CORE_STICKY_ARES 119 357*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AXI_MASTER_ARES 120 358*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AXI_SLAVE_ARES 121 359*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AHB_ARES 122 360*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123 361*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_PIPE_ARES 124 362*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_SLEEP_ARES 125 363*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_CORE_STICKY_ARES 126 364*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_AXI_MASTER_ARES 127 365*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_AXI_SLAVE_ARES 128 366*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_AHB_ARES 129 367*c66ec88fSEmmanuel Vadot #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 368*c66ec88fSEmmanuel Vadot #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 369*c66ec88fSEmmanuel Vadot 370*c66ec88fSEmmanuel Vadot #endif 371