1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (c) 2015 HiSilicon Technologies Co., Ltd. 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot #ifndef __DTS_HI3519_CLOCK_H 7*c66ec88fSEmmanuel Vadot #define __DTS_HI3519_CLOCK_H 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot #define HI3519_FMC_CLK 1 10*c66ec88fSEmmanuel Vadot #define HI3519_SPI0_CLK 2 11*c66ec88fSEmmanuel Vadot #define HI3519_SPI1_CLK 3 12*c66ec88fSEmmanuel Vadot #define HI3519_SPI2_CLK 4 13*c66ec88fSEmmanuel Vadot #define HI3519_UART0_CLK 5 14*c66ec88fSEmmanuel Vadot #define HI3519_UART1_CLK 6 15*c66ec88fSEmmanuel Vadot #define HI3519_UART2_CLK 7 16*c66ec88fSEmmanuel Vadot #define HI3519_UART3_CLK 8 17*c66ec88fSEmmanuel Vadot #define HI3519_UART4_CLK 9 18*c66ec88fSEmmanuel Vadot #define HI3519_PWM_CLK 10 19*c66ec88fSEmmanuel Vadot #define HI3519_DMA_CLK 11 20*c66ec88fSEmmanuel Vadot #define HI3519_IR_CLK 12 21*c66ec88fSEmmanuel Vadot #define HI3519_ETH_PHY_CLK 13 22*c66ec88fSEmmanuel Vadot #define HI3519_ETH_MAC_CLK 14 23*c66ec88fSEmmanuel Vadot #define HI3519_ETH_MACIF_CLK 15 24*c66ec88fSEmmanuel Vadot #define HI3519_USB2_BUS_CLK 16 25*c66ec88fSEmmanuel Vadot #define HI3519_USB2_PORT_CLK 17 26*c66ec88fSEmmanuel Vadot #define HI3519_USB3_CLK 18 27*c66ec88fSEmmanuel Vadot 28*c66ec88fSEmmanuel Vadot #endif /* __DTS_HI3519_CLOCK_H */ 29