1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright 2017 Texas Instruments, Inc. 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLK_DM816_H 6*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLK_DM816_H 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot #define DM816_CLKCTRL_OFFSET 0x0 9*c66ec88fSEmmanuel Vadot #define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET) 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel Vadot /* default clocks */ 12*c66ec88fSEmmanuel Vadot #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel Vadot /* alwon clocks */ 15*c66ec88fSEmmanuel Vadot #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16*c66ec88fSEmmanuel Vadot #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17*c66ec88fSEmmanuel Vadot #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18*c66ec88fSEmmanuel Vadot #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19*c66ec88fSEmmanuel Vadot #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20*c66ec88fSEmmanuel Vadot #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21*c66ec88fSEmmanuel Vadot #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22*c66ec88fSEmmanuel Vadot #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) 23*c66ec88fSEmmanuel Vadot #define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174) 24*c66ec88fSEmmanuel Vadot #define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178) 25*c66ec88fSEmmanuel Vadot #define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c) 26*c66ec88fSEmmanuel Vadot #define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180) 27*c66ec88fSEmmanuel Vadot #define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184) 28*c66ec88fSEmmanuel Vadot #define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188) 29*c66ec88fSEmmanuel Vadot #define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c) 30*c66ec88fSEmmanuel Vadot #define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190) 31*c66ec88fSEmmanuel Vadot #define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194) 32*c66ec88fSEmmanuel Vadot #define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198) 33*c66ec88fSEmmanuel Vadot #define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0) 34*c66ec88fSEmmanuel Vadot #define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0) 35*c66ec88fSEmmanuel Vadot #define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4) 36*c66ec88fSEmmanuel Vadot #define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8) 37*c66ec88fSEmmanuel Vadot #define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc) 38*c66ec88fSEmmanuel Vadot #define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0) 39*c66ec88fSEmmanuel Vadot #define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4) 40*c66ec88fSEmmanuel Vadot #define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8) 41*c66ec88fSEmmanuel Vadot #define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc) 42*c66ec88fSEmmanuel Vadot #define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200) 43*c66ec88fSEmmanuel Vadot #define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204) 44*c66ec88fSEmmanuel Vadot 45*c66ec88fSEmmanuel Vadot #endif 46