xref: /freebsd-src/sys/contrib/device-tree/include/dt-bindings/clock/am3.h (revision c9ccf3a32da427475985b85d7df023ccfb138c27)
1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */
2*c66ec88fSEmmanuel Vadot /*
3*c66ec88fSEmmanuel Vadot  * Copyright 2017 Texas Instruments, Inc.
4*c66ec88fSEmmanuel Vadot  */
5*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_CLK_AM3_H
6*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_CLK_AM3_H
7*c66ec88fSEmmanuel Vadot 
8*c66ec88fSEmmanuel Vadot #define AM3_CLKCTRL_OFFSET	0x0
9*c66ec88fSEmmanuel Vadot #define AM3_CLKCTRL_INDEX(offset)	((offset) - AM3_CLKCTRL_OFFSET)
10*c66ec88fSEmmanuel Vadot 
11*c66ec88fSEmmanuel Vadot /* l4ls clocks */
12*c66ec88fSEmmanuel Vadot #define AM3_L4LS_CLKCTRL_OFFSET	0x38
13*c66ec88fSEmmanuel Vadot #define AM3_L4LS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4LS_CLKCTRL_OFFSET)
14*c66ec88fSEmmanuel Vadot #define AM3_L4LS_UART6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x38)
15*c66ec88fSEmmanuel Vadot #define AM3_L4LS_MMC1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x3c)
16*c66ec88fSEmmanuel Vadot #define AM3_L4LS_ELM_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x40)
17*c66ec88fSEmmanuel Vadot #define AM3_L4LS_I2C3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x44)
18*c66ec88fSEmmanuel Vadot #define AM3_L4LS_I2C2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x48)
19*c66ec88fSEmmanuel Vadot #define AM3_L4LS_SPI0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x4c)
20*c66ec88fSEmmanuel Vadot #define AM3_L4LS_SPI1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x50)
21*c66ec88fSEmmanuel Vadot #define AM3_L4LS_L4_LS_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x60)
22*c66ec88fSEmmanuel Vadot #define AM3_L4LS_UART2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x6c)
23*c66ec88fSEmmanuel Vadot #define AM3_L4LS_UART3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x70)
24*c66ec88fSEmmanuel Vadot #define AM3_L4LS_UART4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x74)
25*c66ec88fSEmmanuel Vadot #define AM3_L4LS_UART5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x78)
26*c66ec88fSEmmanuel Vadot #define AM3_L4LS_TIMER7_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x7c)
27*c66ec88fSEmmanuel Vadot #define AM3_L4LS_TIMER2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x80)
28*c66ec88fSEmmanuel Vadot #define AM3_L4LS_TIMER3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x84)
29*c66ec88fSEmmanuel Vadot #define AM3_L4LS_TIMER4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x88)
30*c66ec88fSEmmanuel Vadot #define AM3_L4LS_RNG_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x90)
31*c66ec88fSEmmanuel Vadot #define AM3_L4LS_GPIO2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xac)
32*c66ec88fSEmmanuel Vadot #define AM3_L4LS_GPIO3_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb0)
33*c66ec88fSEmmanuel Vadot #define AM3_L4LS_GPIO4_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xb4)
34*c66ec88fSEmmanuel Vadot #define AM3_L4LS_D_CAN0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc0)
35*c66ec88fSEmmanuel Vadot #define AM3_L4LS_D_CAN1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xc4)
36*c66ec88fSEmmanuel Vadot #define AM3_L4LS_EPWMSS1_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xcc)
37*c66ec88fSEmmanuel Vadot #define AM3_L4LS_EPWMSS0_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd4)
38*c66ec88fSEmmanuel Vadot #define AM3_L4LS_EPWMSS2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xd8)
39*c66ec88fSEmmanuel Vadot #define AM3_L4LS_TIMER5_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xec)
40*c66ec88fSEmmanuel Vadot #define AM3_L4LS_TIMER6_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf0)
41*c66ec88fSEmmanuel Vadot #define AM3_L4LS_MMC2_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0xf4)
42*c66ec88fSEmmanuel Vadot #define AM3_L4LS_SPINLOCK_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x10c)
43*c66ec88fSEmmanuel Vadot #define AM3_L4LS_MAILBOX_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x110)
44*c66ec88fSEmmanuel Vadot #define AM3_L4LS_OCPWP_CLKCTRL	AM3_L4LS_CLKCTRL_INDEX(0x130)
45*c66ec88fSEmmanuel Vadot 
46*c66ec88fSEmmanuel Vadot /* l3s clocks */
47*c66ec88fSEmmanuel Vadot #define AM3_L3S_CLKCTRL_OFFSET	0x1c
48*c66ec88fSEmmanuel Vadot #define AM3_L3S_CLKCTRL_INDEX(offset)	((offset) - AM3_L3S_CLKCTRL_OFFSET)
49*c66ec88fSEmmanuel Vadot #define AM3_L3S_USB_OTG_HS_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x1c)
50*c66ec88fSEmmanuel Vadot #define AM3_L3S_GPMC_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x30)
51*c66ec88fSEmmanuel Vadot #define AM3_L3S_MCASP0_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x34)
52*c66ec88fSEmmanuel Vadot #define AM3_L3S_MCASP1_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0x68)
53*c66ec88fSEmmanuel Vadot #define AM3_L3S_MMC3_CLKCTRL	AM3_L3S_CLKCTRL_INDEX(0xf8)
54*c66ec88fSEmmanuel Vadot 
55*c66ec88fSEmmanuel Vadot /* l3 clocks */
56*c66ec88fSEmmanuel Vadot #define AM3_L3_CLKCTRL_OFFSET	0x24
57*c66ec88fSEmmanuel Vadot #define AM3_L3_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_CLKCTRL_OFFSET)
58*c66ec88fSEmmanuel Vadot #define AM3_L3_TPTC0_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x24)
59*c66ec88fSEmmanuel Vadot #define AM3_L3_EMIF_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x28)
60*c66ec88fSEmmanuel Vadot #define AM3_L3_OCMCRAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x2c)
61*c66ec88fSEmmanuel Vadot #define AM3_L3_AES_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x94)
62*c66ec88fSEmmanuel Vadot #define AM3_L3_SHAM_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xa0)
63*c66ec88fSEmmanuel Vadot #define AM3_L3_TPCC_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xbc)
64*c66ec88fSEmmanuel Vadot #define AM3_L3_L3_INSTR_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xdc)
65*c66ec88fSEmmanuel Vadot #define AM3_L3_L3_MAIN_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xe0)
66*c66ec88fSEmmanuel Vadot #define AM3_L3_TPTC1_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0xfc)
67*c66ec88fSEmmanuel Vadot #define AM3_L3_TPTC2_CLKCTRL	AM3_L3_CLKCTRL_INDEX(0x100)
68*c66ec88fSEmmanuel Vadot 
69*c66ec88fSEmmanuel Vadot /* l4hs clocks */
70*c66ec88fSEmmanuel Vadot #define AM3_L4HS_CLKCTRL_OFFSET	0x120
71*c66ec88fSEmmanuel Vadot #define AM3_L4HS_CLKCTRL_INDEX(offset)	((offset) - AM3_L4HS_CLKCTRL_OFFSET)
72*c66ec88fSEmmanuel Vadot #define AM3_L4HS_L4_HS_CLKCTRL	AM3_L4HS_CLKCTRL_INDEX(0x120)
73*c66ec88fSEmmanuel Vadot 
74*c66ec88fSEmmanuel Vadot /* pruss_ocp clocks */
75*c66ec88fSEmmanuel Vadot #define AM3_PRUSS_OCP_CLKCTRL_OFFSET	0xe8
76*c66ec88fSEmmanuel Vadot #define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset)	((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
77*c66ec88fSEmmanuel Vadot #define AM3_PRUSS_OCP_PRUSS_CLKCTRL	AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
78*c66ec88fSEmmanuel Vadot 
79*c66ec88fSEmmanuel Vadot /* cpsw_125mhz clocks */
80*c66ec88fSEmmanuel Vadot #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL	AM3_CLKCTRL_INDEX(0x14)
81*c66ec88fSEmmanuel Vadot 
82*c66ec88fSEmmanuel Vadot /* lcdc clocks */
83*c66ec88fSEmmanuel Vadot #define AM3_LCDC_CLKCTRL_OFFSET	0x18
84*c66ec88fSEmmanuel Vadot #define AM3_LCDC_CLKCTRL_INDEX(offset)	((offset) - AM3_LCDC_CLKCTRL_OFFSET)
85*c66ec88fSEmmanuel Vadot #define AM3_LCDC_LCDC_CLKCTRL	AM3_LCDC_CLKCTRL_INDEX(0x18)
86*c66ec88fSEmmanuel Vadot 
87*c66ec88fSEmmanuel Vadot /* clk_24mhz clocks */
88*c66ec88fSEmmanuel Vadot #define AM3_CLK_24MHZ_CLKCTRL_OFFSET	0x14c
89*c66ec88fSEmmanuel Vadot #define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset)	((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
90*c66ec88fSEmmanuel Vadot #define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL	AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
91*c66ec88fSEmmanuel Vadot 
92*c66ec88fSEmmanuel Vadot /* l4_wkup clocks */
93*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_CONTROL_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
94*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_GPIO1_CLKCTRL	AM3_CLKCTRL_INDEX(0x8)
95*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_L4_WKUP_CLKCTRL	AM3_CLKCTRL_INDEX(0xc)
96*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_UART1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb4)
97*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_I2C1_CLKCTRL	AM3_CLKCTRL_INDEX(0xb8)
98*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_ADC_TSC_CLKCTRL	AM3_CLKCTRL_INDEX(0xbc)
99*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL	AM3_CLKCTRL_INDEX(0xc0)
100*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_TIMER1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc4)
101*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL	AM3_CLKCTRL_INDEX(0xc8)
102*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_WD_TIMER2_CLKCTRL	AM3_CLKCTRL_INDEX(0xd4)
103*c66ec88fSEmmanuel Vadot 
104*c66ec88fSEmmanuel Vadot /* l3_aon clocks */
105*c66ec88fSEmmanuel Vadot #define AM3_L3_AON_CLKCTRL_OFFSET	0x14
106*c66ec88fSEmmanuel Vadot #define AM3_L3_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
107*c66ec88fSEmmanuel Vadot #define AM3_L3_AON_DEBUGSS_CLKCTRL	AM3_L3_AON_CLKCTRL_INDEX(0x14)
108*c66ec88fSEmmanuel Vadot 
109*c66ec88fSEmmanuel Vadot /* l4_wkup_aon clocks */
110*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET	0xb0
111*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset)	((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
112*c66ec88fSEmmanuel Vadot #define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL	AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
113*c66ec88fSEmmanuel Vadot 
114*c66ec88fSEmmanuel Vadot /* mpu clocks */
115*c66ec88fSEmmanuel Vadot #define AM3_MPU_MPU_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
116*c66ec88fSEmmanuel Vadot 
117*c66ec88fSEmmanuel Vadot /* l4_rtc clocks */
118*c66ec88fSEmmanuel Vadot #define AM3_L4_RTC_RTC_CLKCTRL	AM3_CLKCTRL_INDEX(0x0)
119*c66ec88fSEmmanuel Vadot 
120*c66ec88fSEmmanuel Vadot /* gfx_l3 clocks */
121*c66ec88fSEmmanuel Vadot #define AM3_GFX_L3_GFX_CLKCTRL	AM3_CLKCTRL_INDEX(0x4)
122*c66ec88fSEmmanuel Vadot 
123*c66ec88fSEmmanuel Vadot /* l4_cefuse clocks */
124*c66ec88fSEmmanuel Vadot #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL	AM3_CLKCTRL_INDEX(0x20)
125*c66ec88fSEmmanuel Vadot 
126*c66ec88fSEmmanuel Vadot #endif
127