1*c66ec88fSEmmanuel Vadot* SiRF SoC USP module 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- compatible: "sirf,prima2-usp-pcm" 5*c66ec88fSEmmanuel Vadot- reg: Base address and size entries: 6*c66ec88fSEmmanuel Vadot- dmas: List of DMA controller phandle and DMA request line ordered pairs. 7*c66ec88fSEmmanuel Vadot- dma-names: Identifier string for each DMA request line in the dmas property. 8*c66ec88fSEmmanuel Vadot These strings correspond 1:1 with the ordered pairs in dmas. 9*c66ec88fSEmmanuel Vadot 10*c66ec88fSEmmanuel Vadot One of the DMA channels will be responsible for transmission (should be 11*c66ec88fSEmmanuel Vadot named "tx") and one for reception (should be named "rx"). 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot- clocks: USP controller clock source 14*c66ec88fSEmmanuel Vadot- pinctrl-names: Must contain a "default" entry. 15*c66ec88fSEmmanuel Vadot- pinctrl-NNN: One property must exist for each entry in pinctrl-names. 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel VadotExample: 18*c66ec88fSEmmanuel Vadotusp0: usp@b0080000 { 19*c66ec88fSEmmanuel Vadot compatible = "sirf,prima2-usp-pcm"; 20*c66ec88fSEmmanuel Vadot reg = <0xb0080000 0x10000>; 21*c66ec88fSEmmanuel Vadot clocks = <&clks 28>; 22*c66ec88fSEmmanuel Vadot dmas = <&dmac1 1>, <&dmac1 2>; 23*c66ec88fSEmmanuel Vadot dma-names = "rx", "tx"; 24*c66ec88fSEmmanuel Vadot pinctrl-names = "default"; 25*c66ec88fSEmmanuel Vadot pinctrl-0 = <&usp0_only_utfs_pins_a>; 26*c66ec88fSEmmanuel Vadot}; 27*c66ec88fSEmmanuel Vadot 28