1*c66ec88fSEmmanuel Vadot* CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter * 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart", 5*c66ec88fSEmmanuel Vadot "sirf,atlas7-uart" or "sirf,atlas7-usp-uart". 6*c66ec88fSEmmanuel Vadot- reg : Offset and length of the register set for the device 7*c66ec88fSEmmanuel Vadot- interrupts : Should contain uart interrupt 8*c66ec88fSEmmanuel Vadot- fifosize : Should define hardware rx/tx fifo size 9*c66ec88fSEmmanuel Vadot- clocks : Should contain uart clock number 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel VadotOptional properties: 12*c66ec88fSEmmanuel Vadot- uart-has-rtscts: we have hardware flow controller pins in hardware 13*c66ec88fSEmmanuel Vadot- rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true 14*c66ec88fSEmmanuel Vadot- cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel VadotExample: 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel Vadotuart0: uart@b0050000 { 19*c66ec88fSEmmanuel Vadot cell-index = <0>; 20*c66ec88fSEmmanuel Vadot compatible = "sirf,prima2-uart"; 21*c66ec88fSEmmanuel Vadot reg = <0xb0050000 0x1000>; 22*c66ec88fSEmmanuel Vadot interrupts = <17>; 23*c66ec88fSEmmanuel Vadot fifosize = <128>; 24*c66ec88fSEmmanuel Vadot clocks = <&clks 13>; 25*c66ec88fSEmmanuel Vadot}; 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel VadotOn the board-specific dts, we can put rts-gpios and cts-gpios like 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadotusp@b0090000 { 30*c66ec88fSEmmanuel Vadot compatible = "sirf,prima2-usp-uart"; 31*c66ec88fSEmmanuel Vadot uart-has-rtscts; 32*c66ec88fSEmmanuel Vadot rts-gpios = <&gpio 15 0>; 33*c66ec88fSEmmanuel Vadot cts-gpios = <&gpio 46 0>; 34*c66ec88fSEmmanuel Vadot}; 35