1*c66ec88fSEmmanuel Vadot* MSM Serial UARTDM 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThe MSM serial UARTDM hardware is designed for high-speed use cases where the 4*c66ec88fSEmmanuel Vadottransmit and/or receive channels can be offloaded to a dma-engine. From a 5*c66ec88fSEmmanuel Vadotsoftware perspective it's mostly compatible with the MSM serial UART except 6*c66ec88fSEmmanuel Vadotthat it supports reading and writing multiple characters at a time. 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel VadotRequired properties: 9*c66ec88fSEmmanuel Vadot- compatible: Should contain at least "qcom,msm-uartdm". 10*c66ec88fSEmmanuel Vadot A more specific property should be specified as follows depending 11*c66ec88fSEmmanuel Vadot on the version: 12*c66ec88fSEmmanuel Vadot "qcom,msm-uartdm-v1.1" 13*c66ec88fSEmmanuel Vadot "qcom,msm-uartdm-v1.2" 14*c66ec88fSEmmanuel Vadot "qcom,msm-uartdm-v1.3" 15*c66ec88fSEmmanuel Vadot "qcom,msm-uartdm-v1.4" 16*c66ec88fSEmmanuel Vadot- reg: Should contain UART register locations and lengths. The first 17*c66ec88fSEmmanuel Vadot register shall specify the main control registers. An optional second 18*c66ec88fSEmmanuel Vadot register location shall specify the GSBI control region. 19*c66ec88fSEmmanuel Vadot "qcom,msm-uartdm-v1.3" is the only compatible value that might 20*c66ec88fSEmmanuel Vadot need the GSBI control region. 21*c66ec88fSEmmanuel Vadot- interrupts: Should contain UART interrupt. 22*c66ec88fSEmmanuel Vadot- clocks: Should contain the core clock and the AHB clock. 23*c66ec88fSEmmanuel Vadot- clock-names: Should be "core" for the core clock and "iface" for the 24*c66ec88fSEmmanuel Vadot AHB clock. 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel VadotOptional properties: 27*c66ec88fSEmmanuel Vadot- dmas: Should contain dma specifiers for transmit and receive channels 28*c66ec88fSEmmanuel Vadot- dma-names: Should contain "tx" for transmit and "rx" for receive channels 29*c66ec88fSEmmanuel Vadot- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be 30*c66ec88fSEmmanuel Vadot used with TX DMA channel. Required when using DMA for transmission 31*c66ec88fSEmmanuel Vadot with UARTDM v1.3 and below. 32*c66ec88fSEmmanuel Vadot- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be 33*c66ec88fSEmmanuel Vadot used with RX DMA channel. Required when using DMA for reception 34*c66ec88fSEmmanuel Vadot with UARTDM v1.3 and below. 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel VadotNote: Aliases may be defined to ensure the correct ordering of the UARTs. 37*c66ec88fSEmmanuel VadotThe alias serialN will result in the UART being assigned port N. If any 38*c66ec88fSEmmanuel VadotserialN alias exists, then an alias must exist for each enabled UART. The 39*c66ec88fSEmmanuel VadotserialN aliases should be in a .dts file instead of in a .dtsi file. 40*c66ec88fSEmmanuel Vadot 41*c66ec88fSEmmanuel VadotExamples: 42*c66ec88fSEmmanuel Vadot 43*c66ec88fSEmmanuel Vadot- A uartdm v1.4 device with dma capabilities. 44*c66ec88fSEmmanuel Vadot 45*c66ec88fSEmmanuel Vadot serial@f991e000 { 46*c66ec88fSEmmanuel Vadot compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 47*c66ec88fSEmmanuel Vadot reg = <0xf991e000 0x1000>; 48*c66ec88fSEmmanuel Vadot interrupts = <0 108 0x0>; 49*c66ec88fSEmmanuel Vadot clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; 50*c66ec88fSEmmanuel Vadot clock-names = "core", "iface"; 51*c66ec88fSEmmanuel Vadot dmas = <&dma0 0>, <&dma0 1>; 52*c66ec88fSEmmanuel Vadot dma-names = "tx", "rx"; 53*c66ec88fSEmmanuel Vadot }; 54*c66ec88fSEmmanuel Vadot 55*c66ec88fSEmmanuel Vadot- A uartdm v1.3 device without dma capabilities and part of a GSBI complex. 56*c66ec88fSEmmanuel Vadot 57*c66ec88fSEmmanuel Vadot serial@19c40000 { 58*c66ec88fSEmmanuel Vadot compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 59*c66ec88fSEmmanuel Vadot reg = <0x19c40000 0x1000>, 60*c66ec88fSEmmanuel Vadot <0x19c00000 0x1000>; 61*c66ec88fSEmmanuel Vadot interrupts = <0 195 0x0>; 62*c66ec88fSEmmanuel Vadot clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>; 63*c66ec88fSEmmanuel Vadot clock-names = "core", "iface"; 64*c66ec88fSEmmanuel Vadot }; 65*c66ec88fSEmmanuel Vadot 66*c66ec88fSEmmanuel Vadot- serialN alias. 67*c66ec88fSEmmanuel Vadot 68*c66ec88fSEmmanuel Vadot aliases { 69*c66ec88fSEmmanuel Vadot serial0 = &uarta; 70*c66ec88fSEmmanuel Vadot serial1 = &uartc; 71*c66ec88fSEmmanuel Vadot serial2 = &uartb; 72*c66ec88fSEmmanuel Vadot }; 73*c66ec88fSEmmanuel Vadot 74*c66ec88fSEmmanuel Vadot uarta: serial@12490000 { 75*c66ec88fSEmmanuel Vadot }; 76*c66ec88fSEmmanuel Vadot 77*c66ec88fSEmmanuel Vadot uartb: serial@16340000 { 78*c66ec88fSEmmanuel Vadot }; 79*c66ec88fSEmmanuel Vadot 80*c66ec88fSEmmanuel Vadot uartc: serial@1a240000 { 81*c66ec88fSEmmanuel Vadot }; 82