1*c66ec88fSEmmanuel Vadot* FSL MPIC Message Registers 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThis binding specifies what properties must be available in the device tree 4*c66ec88fSEmmanuel Vadotrepresentation of the message register blocks found in some FSL MPIC 5*c66ec88fSEmmanuel Vadotimplementations. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotRequired properties: 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot - compatible: Specifies the compatibility list for the message register 10*c66ec88fSEmmanuel Vadot block. The type shall be <string-list> and the value shall be of the form 11*c66ec88fSEmmanuel Vadot "fsl,mpic-v<version>-msgr", where <version> is the version number of 12*c66ec88fSEmmanuel Vadot the MPIC containing the message registers. 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel Vadot - reg: Specifies the base physical address(s) and size(s) of the 15*c66ec88fSEmmanuel Vadot message register block's addressable register space. The type shall be 16*c66ec88fSEmmanuel Vadot <prop-encoded-array>. 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel Vadot - interrupts: Specifies a list of interrupt-specifiers which are available 19*c66ec88fSEmmanuel Vadot for receiving interrupts. Interrupt-specifier consists of two cells: first 20*c66ec88fSEmmanuel Vadot cell is interrupt-number and second cell is level-sense. The type shall be 21*c66ec88fSEmmanuel Vadot <prop-encoded-array>. 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel VadotOptional properties: 24*c66ec88fSEmmanuel Vadot 25*c66ec88fSEmmanuel Vadot - mpic-msgr-receive-mask: Specifies what registers in the containing block 26*c66ec88fSEmmanuel Vadot are allowed to receive interrupts. The value is a bit mask where a set 27*c66ec88fSEmmanuel Vadot bit at bit 'n' indicates that message register 'n' can receive interrupts. 28*c66ec88fSEmmanuel Vadot Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall 29*c66ec88fSEmmanuel Vadot be <u32>. If not present, then all of the message registers in the block 30*c66ec88fSEmmanuel Vadot are available. 31*c66ec88fSEmmanuel Vadot 32*c66ec88fSEmmanuel VadotAliases: 33*c66ec88fSEmmanuel Vadot 34*c66ec88fSEmmanuel Vadot An alias should be created for every message register block. They are not 35*c66ec88fSEmmanuel Vadot required, though. However, a particular implementation of this binding 36*c66ec88fSEmmanuel Vadot may require aliases to be present. Aliases are of the form 37*c66ec88fSEmmanuel Vadot 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number. 38*c66ec88fSEmmanuel Vadot Numbers shall start at 0. 39*c66ec88fSEmmanuel Vadot 40*c66ec88fSEmmanuel VadotExample: 41*c66ec88fSEmmanuel Vadot 42*c66ec88fSEmmanuel Vadot aliases { 43*c66ec88fSEmmanuel Vadot mpic-msgr-block0 = &mpic_msgr_block0; 44*c66ec88fSEmmanuel Vadot mpic-msgr-block1 = &mpic_msgr_block1; 45*c66ec88fSEmmanuel Vadot }; 46*c66ec88fSEmmanuel Vadot 47*c66ec88fSEmmanuel Vadot mpic_msgr_block0: mpic-msgr-block@41400 { 48*c66ec88fSEmmanuel Vadot compatible = "fsl,mpic-v3.1-msgr"; 49*c66ec88fSEmmanuel Vadot reg = <0x41400 0x200>; 50*c66ec88fSEmmanuel Vadot // Message registers 0 and 2 in this block can receive interrupts on 51*c66ec88fSEmmanuel Vadot // sources 0xb0 and 0xb2, respectively. 52*c66ec88fSEmmanuel Vadot interrupts = <0xb0 2 0xb2 2>; 53*c66ec88fSEmmanuel Vadot mpic-msgr-receive-mask = <0x5>; 54*c66ec88fSEmmanuel Vadot }; 55*c66ec88fSEmmanuel Vadot 56*c66ec88fSEmmanuel Vadot mpic_msgr_block1: mpic-msgr-block@42400 { 57*c66ec88fSEmmanuel Vadot compatible = "fsl,mpic-v3.1-msgr"; 58*c66ec88fSEmmanuel Vadot reg = <0x42400 0x200>; 59*c66ec88fSEmmanuel Vadot // Message registers 0 and 2 in this block can receive interrupts on 60*c66ec88fSEmmanuel Vadot // sources 0xb4 and 0xb6, respectively. 61*c66ec88fSEmmanuel Vadot interrupts = <0xb4 2 0xb6 2>; 62*c66ec88fSEmmanuel Vadot mpic-msgr-receive-mask = <0x5>; 63*c66ec88fSEmmanuel Vadot }; 64