1*c66ec88fSEmmanuel VadotFreescale Multi Mode DDR controller (MMDC) 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties : 4*c66ec88fSEmmanuel Vadot- compatible : should be one of following: 5*c66ec88fSEmmanuel Vadot for i.MX6Q/i.MX6DL: 6*c66ec88fSEmmanuel Vadot - "fsl,imx6q-mmdc"; 7*c66ec88fSEmmanuel Vadot for i.MX6QP: 8*c66ec88fSEmmanuel Vadot - "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc"; 9*c66ec88fSEmmanuel Vadot for i.MX6SL: 10*c66ec88fSEmmanuel Vadot - "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; 11*c66ec88fSEmmanuel Vadot for i.MX6SLL: 12*c66ec88fSEmmanuel Vadot - "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc"; 13*c66ec88fSEmmanuel Vadot for i.MX6SX: 14*c66ec88fSEmmanuel Vadot - "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 15*c66ec88fSEmmanuel Vadot for i.MX6UL/i.MX6ULL/i.MX6ULZ: 16*c66ec88fSEmmanuel Vadot - "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; 17*c66ec88fSEmmanuel Vadot for i.MX7ULP: 18*c66ec88fSEmmanuel Vadot - "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; 19*c66ec88fSEmmanuel Vadot- reg : address and size of MMDC DDR controller registers 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel VadotOptional properties : 22*c66ec88fSEmmanuel Vadot- clocks : the clock provided by the SoC to access the MMDC registers 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel VadotExample : 25*c66ec88fSEmmanuel Vadot mmdc0: memory-controller@21b0000 { /* MMDC0 */ 26*c66ec88fSEmmanuel Vadot compatible = "fsl,imx6q-mmdc"; 27*c66ec88fSEmmanuel Vadot reg = <0x021b0000 0x4000>; 28*c66ec88fSEmmanuel Vadot clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; 29*c66ec88fSEmmanuel Vadot }; 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel Vadot mmdc1: memory-controller@21b4000 { /* MMDC1 */ 32*c66ec88fSEmmanuel Vadot compatible = "fsl,imx6q-mmdc"; 33*c66ec88fSEmmanuel Vadot reg = <0x021b4000 0x4000>; 34*c66ec88fSEmmanuel Vadot status = "disabled"; 35*c66ec88fSEmmanuel Vadot }; 36