1*c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*c66ec88fSEmmanuel Vadot%YAML 1.2 3*c66ec88fSEmmanuel Vadot--- 4*c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml# 5*c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadottitle: Calxeda DDR memory controller binding 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadotdescription: | 10*c66ec88fSEmmanuel Vadot The Calxeda DDR memory controller is initialised and programmed by the 11*c66ec88fSEmmanuel Vadot firmware, but an OS might want to read its registers for error reporting 12*c66ec88fSEmmanuel Vadot purposes and to learn about the DRAM topology. 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel Vadotmaintainers: 15*c66ec88fSEmmanuel Vadot - Andre Przywara <andre.przywara@arm.com> 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel Vadotproperties: 18*c66ec88fSEmmanuel Vadot compatible: 19*c66ec88fSEmmanuel Vadot enum: 20*c66ec88fSEmmanuel Vadot - calxeda,hb-ddr-ctrl 21*c66ec88fSEmmanuel Vadot - calxeda,ecx-2000-ddr-ctrl 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel Vadot reg: 24*c66ec88fSEmmanuel Vadot maxItems: 1 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel Vadot interrupts: 27*c66ec88fSEmmanuel Vadot maxItems: 1 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadotrequired: 30*c66ec88fSEmmanuel Vadot - compatible 31*c66ec88fSEmmanuel Vadot - reg 32*c66ec88fSEmmanuel Vadot - interrupts 33*c66ec88fSEmmanuel Vadot 34*c66ec88fSEmmanuel VadotadditionalProperties: false 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel Vadotexamples: 37*c66ec88fSEmmanuel Vadot - | 38*c66ec88fSEmmanuel Vadot memory-controller@fff00000 { 39*c66ec88fSEmmanuel Vadot compatible = "calxeda,hb-ddr-ctrl"; 40*c66ec88fSEmmanuel Vadot reg = <0xfff00000 0x1000>; 41*c66ec88fSEmmanuel Vadot interrupts = <0 91 4>; 42*c66ec88fSEmmanuel Vadot }; 43