1*c66ec88fSEmmanuel Vadot* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA) 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotProperties: 4*c66ec88fSEmmanuel Vadot 5*c66ec88fSEmmanuel Vadot- compatible: "snps,archs-intc" 6*c66ec88fSEmmanuel Vadot- interrupt-controller: This is an interrupt controller. 7*c66ec88fSEmmanuel Vadot- #interrupt-cells: Must be <1>. 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot Single Cell "interrupts" property of a device specifies the IRQ number 10*c66ec88fSEmmanuel Vadot between 16 to 256 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel Vadot intc accessed via the special ARC AUX register interface, hence "reg" property 13*c66ec88fSEmmanuel Vadot is not specified. 14*c66ec88fSEmmanuel Vadot 15*c66ec88fSEmmanuel VadotExample: 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel Vadot intc: interrupt-controller { 18*c66ec88fSEmmanuel Vadot compatible = "snps,archs-intc"; 19*c66ec88fSEmmanuel Vadot interrupt-controller; 20*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 21*c66ec88fSEmmanuel Vadot interrupts = <16 17 18 19 20 21 22 23 24 25>; 22*c66ec88fSEmmanuel Vadot }; 23