1*c66ec88fSEmmanuel VadotI2C for Hisilicon hix5hd2 chipset platform 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot- compatible: Must be "hisilicon,hix5hd2-i2c" 5*c66ec88fSEmmanuel Vadot- reg: physical base address of the controller and length of memory mapped 6*c66ec88fSEmmanuel Vadot region. 7*c66ec88fSEmmanuel Vadot- interrupts: interrupt number to the cpu. 8*c66ec88fSEmmanuel Vadot- #address-cells = <1>; 9*c66ec88fSEmmanuel Vadot- #size-cells = <0>; 10*c66ec88fSEmmanuel Vadot- clocks: phandles to input clocks. 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel VadotOptional properties: 13*c66ec88fSEmmanuel Vadot- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 14*c66ec88fSEmmanuel Vadot- Child nodes conforming to i2c bus binding 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel VadotExamples: 17*c66ec88fSEmmanuel VadotI2C0@f8b10000 { 18*c66ec88fSEmmanuel Vadot compatible = "hisilicon,hix5hd2-i2c"; 19*c66ec88fSEmmanuel Vadot reg = <0xf8b10000 0x1000>; 20*c66ec88fSEmmanuel Vadot interrupts = <0 38 4>; 21*c66ec88fSEmmanuel Vadot clocks = <&clock HIX5HD2_I2C0_RST>; 22*c66ec88fSEmmanuel Vadot #address-cells = <1>; 23*c66ec88fSEmmanuel Vadot #size-cells = <0>; 24*c66ec88fSEmmanuel Vadot} 25