1*f126890aSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*f126890aSEmmanuel Vadot%YAML 1.2 3*f126890aSEmmanuel Vadot--- 4*f126890aSEmmanuel Vadot$id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml# 5*f126890aSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f126890aSEmmanuel Vadot 7*f126890aSEmmanuel Vadottitle: Generic MMIO GPIO 8*f126890aSEmmanuel Vadot 9*f126890aSEmmanuel Vadotmaintainers: 10*f126890aSEmmanuel Vadot - Linus Walleij <linus.walleij@linaro.org> 11*f126890aSEmmanuel Vadot - Bartosz Golaszewski <brgl@bgdev.pl> 12*f126890aSEmmanuel Vadot 13*f126890aSEmmanuel Vadotdescription: 14*f126890aSEmmanuel Vadot Some simple GPIO controllers may consist of a single data register or a pair 15*f126890aSEmmanuel Vadot of set/clear-bit registers. Such controllers are common for glue logic in 16*f126890aSEmmanuel Vadot FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped 17*f126890aSEmmanuel Vadot NAND-style parallel busses. 18*f126890aSEmmanuel Vadot 19*f126890aSEmmanuel Vadotproperties: 20*f126890aSEmmanuel Vadot compatible: 21*f126890aSEmmanuel Vadot enum: 22*f126890aSEmmanuel Vadot - brcm,bcm6345-gpio 23*f126890aSEmmanuel Vadot - ni,169445-nand-gpio 24*f126890aSEmmanuel Vadot - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller 25*f126890aSEmmanuel Vadot 26*f126890aSEmmanuel Vadot big-endian: true 27*f126890aSEmmanuel Vadot 28*f126890aSEmmanuel Vadot '#gpio-cells': 29*f126890aSEmmanuel Vadot const: 2 30*f126890aSEmmanuel Vadot 31*f126890aSEmmanuel Vadot gpio-controller: true 32*f126890aSEmmanuel Vadot 33*f126890aSEmmanuel Vadot little-endian: true 34*f126890aSEmmanuel Vadot 35*f126890aSEmmanuel Vadot reg: 36*f126890aSEmmanuel Vadot minItems: 1 37*f126890aSEmmanuel Vadot description: 38*f126890aSEmmanuel Vadot A list of registers in the controller. The width of each register is 39*f126890aSEmmanuel Vadot determined by its size. All registers must have the same width. The number 40*f126890aSEmmanuel Vadot of GPIOs is set by the width, with bit 0 corresponding to GPIO 0. 41*f126890aSEmmanuel Vadot items: 42*f126890aSEmmanuel Vadot - description: 43*f126890aSEmmanuel Vadot Register to READ the value of the GPIO lines. If GPIO line is high, 44*f126890aSEmmanuel Vadot the bit will be set. If the GPIO line is low, the bit will be cleared. 45*f126890aSEmmanuel Vadot This register may also be used to drive GPIOs if the SET register is 46*f126890aSEmmanuel Vadot omitted. 47*f126890aSEmmanuel Vadot - description: 48*f126890aSEmmanuel Vadot Register to SET the value of the GPIO lines. Setting a bit in this 49*f126890aSEmmanuel Vadot register will drive the GPIO line high. 50*f126890aSEmmanuel Vadot - description: 51*f126890aSEmmanuel Vadot Register to CLEAR the value of the GPIO lines. Setting a bit in this 52*f126890aSEmmanuel Vadot register will drive the GPIO line low. If this register is omitted, 53*f126890aSEmmanuel Vadot the SET register will be used to clear the GPIO lines as well, by 54*f126890aSEmmanuel Vadot actively writing the line with 0. 55*f126890aSEmmanuel Vadot - description: 56*f126890aSEmmanuel Vadot Register to set the line as OUTPUT. Setting a bit in this register 57*f126890aSEmmanuel Vadot will turn that line into an output line. Conversely, clearing a bit 58*f126890aSEmmanuel Vadot will turn that line into an input. 59*f126890aSEmmanuel Vadot - description: 60*f126890aSEmmanuel Vadot Register to set this line as INPUT. Setting a bit in this register 61*f126890aSEmmanuel Vadot will turn that line into an input line. Conversely, clearing a bit 62*f126890aSEmmanuel Vadot will turn that line into an output. 63*f126890aSEmmanuel Vadot 64*f126890aSEmmanuel Vadot reg-names: 65*f126890aSEmmanuel Vadot minItems: 1 66*f126890aSEmmanuel Vadot maxItems: 5 67*f126890aSEmmanuel Vadot items: 68*f126890aSEmmanuel Vadot enum: 69*f126890aSEmmanuel Vadot - dat 70*f126890aSEmmanuel Vadot - set 71*f126890aSEmmanuel Vadot - clr 72*f126890aSEmmanuel Vadot - dirout 73*f126890aSEmmanuel Vadot - dirin 74*f126890aSEmmanuel Vadot 75*f126890aSEmmanuel Vadot native-endian: true 76*f126890aSEmmanuel Vadot 77*f126890aSEmmanuel Vadot no-output: 78*f126890aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 79*f126890aSEmmanuel Vadot description: 80*f126890aSEmmanuel Vadot If this property is present, the controller cannot drive the GPIO lines. 81*f126890aSEmmanuel Vadot 82*f126890aSEmmanuel Vadotrequired: 83*f126890aSEmmanuel Vadot - compatible 84*f126890aSEmmanuel Vadot - reg 85*f126890aSEmmanuel Vadot - reg-names 86*f126890aSEmmanuel Vadot - '#gpio-cells' 87*f126890aSEmmanuel Vadot - gpio-controller 88*f126890aSEmmanuel Vadot 89*f126890aSEmmanuel VadotadditionalProperties: false 90*f126890aSEmmanuel Vadot 91*f126890aSEmmanuel Vadotexamples: 92*f126890aSEmmanuel Vadot - | 93*f126890aSEmmanuel Vadot gpio@1f300010 { 94*f126890aSEmmanuel Vadot compatible = "ni,169445-nand-gpio"; 95*f126890aSEmmanuel Vadot reg = <0x1f300010 0x4>; 96*f126890aSEmmanuel Vadot reg-names = "dat"; 97*f126890aSEmmanuel Vadot gpio-controller; 98*f126890aSEmmanuel Vadot #gpio-cells = <2>; 99*f126890aSEmmanuel Vadot }; 100*f126890aSEmmanuel Vadot 101*f126890aSEmmanuel Vadot gpio@e0100000 { 102*f126890aSEmmanuel Vadot compatible = "wd,mbl-gpio"; 103*f126890aSEmmanuel Vadot reg-names = "dat"; 104*f126890aSEmmanuel Vadot reg = <0xe0100000 0x1>; 105*f126890aSEmmanuel Vadot #gpio-cells = <2>; 106*f126890aSEmmanuel Vadot gpio-controller; 107*f126890aSEmmanuel Vadot no-output; 108*f126890aSEmmanuel Vadot }; 109*f126890aSEmmanuel Vadot 110*f126890aSEmmanuel Vadot gpio@fffe0406 { 111*f126890aSEmmanuel Vadot compatible = "brcm,bcm6345-gpio"; 112*f126890aSEmmanuel Vadot reg-names = "dirout", "dat"; 113*f126890aSEmmanuel Vadot reg = <0xfffe0406 2>, <0xfffe040a 2>; 114*f126890aSEmmanuel Vadot native-endian; 115*f126890aSEmmanuel Vadot gpio-controller; 116*f126890aSEmmanuel Vadot #gpio-cells = <2>; 117*f126890aSEmmanuel Vadot }; 118