1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Common Properties for Synopsys DesignWare HDMI TX Controller 8 9maintainers: 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 11 12description: | 13 This document defines device tree properties for the Synopsys DesignWare HDMI 14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree 15 binding specification by itself but is meant to be referenced by device tree 16 bindings for the platform-specific integrations of the DWC HDMI TX. 17 18 When referenced from platform device tree bindings the properties defined in 19 this document are defined as follows. The platform device tree bindings are 20 responsible for defining whether each property is required or optional. 21 22properties: 23 reg: 24 maxItems: 1 25 26 reg-io-width: 27 description: 28 Width (in bytes) of the registers specified by the reg property. 29 allOf: 30 - $ref: /schemas/types.yaml#/definitions/uint32 31 - enum: [1, 4] 32 default: 1 33 34 clocks: 35 minItems: 2 36 maxItems: 5 37 items: 38 - description: The bus clock for either AHB and APB 39 - description: The internal register configuration clock 40 additionalItems: true 41 42 clock-names: 43 minItems: 2 44 maxItems: 5 45 items: 46 - const: iahb 47 - const: isfr 48 additionalItems: true 49 50 interrupts: 51 maxItems: 1 52 53additionalProperties: true 54 55... 56