1c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2c66ec88fSEmmanuel Vadot%YAML 1.2 3c66ec88fSEmmanuel Vadot--- 4c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml# 5c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6c66ec88fSEmmanuel Vadot 7*8bab661aSEmmanuel Vadottitle: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller 8c66ec88fSEmmanuel Vadot 9c66ec88fSEmmanuel Vadotmaintainers: 10c66ec88fSEmmanuel Vadot - A.s. Dong <aisheng.dong@nxp.com> 11c66ec88fSEmmanuel Vadot 12c66ec88fSEmmanuel Vadotdescription: | 13c66ec88fSEmmanuel Vadot i.MX7ULP Clock functions are under joint control of the System 14c66ec88fSEmmanuel Vadot Clock Generation (SCG) modules, Peripheral Clock Control (PCC) 15c66ec88fSEmmanuel Vadot modules, and Core Mode Controller (CMC)1 blocks 16c66ec88fSEmmanuel Vadot 17c66ec88fSEmmanuel Vadot The clocking scheme provides clear separation between M4 domain 18c66ec88fSEmmanuel Vadot and A7 domain. Except for a few clock sources shared between two 19c66ec88fSEmmanuel Vadot domains, such as the System Oscillator clock, the Slow IRC (SIRC), 20c66ec88fSEmmanuel Vadot and and the Fast IRC clock (FIRCLK), clock sources and clock 21c66ec88fSEmmanuel Vadot management are separated and contained within each domain. 22c66ec88fSEmmanuel Vadot 23c66ec88fSEmmanuel Vadot M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. 24c66ec88fSEmmanuel Vadot A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. 25c66ec88fSEmmanuel Vadot 26c66ec88fSEmmanuel Vadot Note: this binding doc is only for A7 clock domain. 27c66ec88fSEmmanuel Vadot 28c66ec88fSEmmanuel Vadot The Peripheral Clock Control (PCC) is responsible for clock selection, 29c66ec88fSEmmanuel Vadot optional division and clock gating mode for peripherals in their 30c66ec88fSEmmanuel Vadot respected power domain. 31c66ec88fSEmmanuel Vadot 32c66ec88fSEmmanuel Vadot The clock consumer should specify the desired clock by having the clock 33c66ec88fSEmmanuel Vadot ID in its "clocks" phandle cell. 34c66ec88fSEmmanuel Vadot See include/dt-bindings/clock/imx7ulp-clock.h for the full list of 35c66ec88fSEmmanuel Vadot i.MX7ULP clock IDs of each module. 36c66ec88fSEmmanuel Vadot 37c66ec88fSEmmanuel Vadotproperties: 38c66ec88fSEmmanuel Vadot compatible: 39c66ec88fSEmmanuel Vadot enum: 40c66ec88fSEmmanuel Vadot - fsl,imx7ulp-pcc2 41c66ec88fSEmmanuel Vadot - fsl,imx7ulp-pcc3 42c66ec88fSEmmanuel Vadot 43c66ec88fSEmmanuel Vadot reg: 44c66ec88fSEmmanuel Vadot maxItems: 1 45c66ec88fSEmmanuel Vadot 46c66ec88fSEmmanuel Vadot '#clock-cells': 47c66ec88fSEmmanuel Vadot const: 1 48c66ec88fSEmmanuel Vadot 49c66ec88fSEmmanuel Vadot clocks: 50c66ec88fSEmmanuel Vadot items: 51c66ec88fSEmmanuel Vadot - description: nic1 bus clock 52c66ec88fSEmmanuel Vadot - description: nic1 clock 53c66ec88fSEmmanuel Vadot - description: ddr clock 54c66ec88fSEmmanuel Vadot - description: apll pfd2 55c66ec88fSEmmanuel Vadot - description: apll pfd1 56c66ec88fSEmmanuel Vadot - description: apll pfd0 57c66ec88fSEmmanuel Vadot - description: usb pll 58c66ec88fSEmmanuel Vadot - description: system osc bus clock 59c66ec88fSEmmanuel Vadot - description: fast internal reference clock bus 60c66ec88fSEmmanuel Vadot - description: rtc osc 61c66ec88fSEmmanuel Vadot - description: system pll bus clock 62c66ec88fSEmmanuel Vadot 63c66ec88fSEmmanuel Vadot clock-names: 64c66ec88fSEmmanuel Vadot items: 65c66ec88fSEmmanuel Vadot - const: nic1_bus_clk 66c66ec88fSEmmanuel Vadot - const: nic1_clk 67c66ec88fSEmmanuel Vadot - const: ddr_clk 68c66ec88fSEmmanuel Vadot - const: apll_pfd2 69c66ec88fSEmmanuel Vadot - const: apll_pfd1 70c66ec88fSEmmanuel Vadot - const: apll_pfd0 71c66ec88fSEmmanuel Vadot - const: upll 72c66ec88fSEmmanuel Vadot - const: sosc_bus_clk 73c66ec88fSEmmanuel Vadot - const: firc_bus_clk 74c66ec88fSEmmanuel Vadot - const: rosc 75c66ec88fSEmmanuel Vadot - const: spll_bus_clk 76c66ec88fSEmmanuel Vadot 77c66ec88fSEmmanuel Vadotrequired: 78c66ec88fSEmmanuel Vadot - compatible 79c66ec88fSEmmanuel Vadot - reg 80c66ec88fSEmmanuel Vadot - '#clock-cells' 81c66ec88fSEmmanuel Vadot - clocks 82c66ec88fSEmmanuel Vadot - clock-names 83c66ec88fSEmmanuel Vadot 84c66ec88fSEmmanuel VadotadditionalProperties: false 85c66ec88fSEmmanuel Vadot 86c66ec88fSEmmanuel Vadotexamples: 87c66ec88fSEmmanuel Vadot - | 88c66ec88fSEmmanuel Vadot #include <dt-bindings/clock/imx7ulp-clock.h> 89c66ec88fSEmmanuel Vadot #include <dt-bindings/interrupt-controller/arm-gic.h> 90c66ec88fSEmmanuel Vadot 91c66ec88fSEmmanuel Vadot clock-controller@403f0000 { 92c66ec88fSEmmanuel Vadot compatible = "fsl,imx7ulp-pcc2"; 93c66ec88fSEmmanuel Vadot reg = <0x403f0000 0x10000>; 94c66ec88fSEmmanuel Vadot #clock-cells = <1>; 95c66ec88fSEmmanuel Vadot clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 96c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_NIC1_DIV>, 97c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_DDR_DIV>, 98c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_APLL_PFD2>, 99c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_APLL_PFD1>, 100c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_APLL_PFD0>, 101c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_UPLL>, 102c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, 103c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, 104c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_ROSC>, 105c66ec88fSEmmanuel Vadot <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; 106c66ec88fSEmmanuel Vadot clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", 107c66ec88fSEmmanuel Vadot "apll_pfd2", "apll_pfd1", "apll_pfd0", 108c66ec88fSEmmanuel Vadot "upll", "sosc_bus_clk", "firc_bus_clk", 109c66ec88fSEmmanuel Vadot "rosc", "spll_bus_clk"; 110c66ec88fSEmmanuel Vadot }; 111